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    							 FUJITSU SEMICONDUCTOR LIMITED 
5.  Operation Mode 3 (LIN Communication Mode) Setting Procedure and Program Flow 
In Operation Mode 3 (LIN communication mode), the LIN interface (Ver. 2.1) can be used for a 
LIN master or LIN slave system. 
 Register settings 
  CPU-to-CPU connection 
Figure 5-1  shows a communication system consisting of  one LIN master and one LIN sl ave. The LIN 
interface (ver. 2.1) can work as  a LIN master or a LIN slave. 
Figure 5-1 An example of LIN bus system communication 
 
LIN masterLIN slave
SOT
SIN SOT
SINtransceiver transceiver
 
 
 
CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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 Example flowchart 
  Master mode operations 
Figure 5-2 An example flowchart of LIN communication in master mode (when FIFO is not used) 
Start
Initial settings:
Set the operation mode to 3 and master mode.
Enable the serial data output, and set a baud rate.
Set an LIN Break length and a Break delimiter length.
TXE=1, TIE=0, RXE=1, RIE=1
Message?
Yes NoWake up ?
Yes
No
LIN Break field transmission: LBR=1
LIN Sync field transmission: TDR=0x55
RDRF=1
Receive interrupt
LIN Sync field reception *1
ID field transmission: TDR=ID
RDRF=1
Receive interrupt
ID field reception *1
Data field 
reception?
Data1 reception *1: RDR
Yes (Receive)
RDRF=1
Receive interrupt
RDRF=1
Receive interrupt
DataN reception *1: RDR No (Transmit)
Set transmit Data1: TDR=Data1
TIE=1
TDRE=1
Transmit interrupt
Set transmit Data2: TDR=Data2
RDRF=1
Receive interrupt
Data1 reception *1: RDR
Set transmit DataN: TDR=DataN TIE=0TDRE=1
Transmit interrupt
Data(N-1) reception *1: RDR
RDRF=1
Receive interrupt
RDRF=1
Receive interrupt
DataN reception *1: RDR
Error existing?
Error processing *2
No
Yes
*1:If an error has occurred, carry out the relevant error recovery action.
*2:If the FRE and ORE bits are 1, set the SSR:REC bit to “1” to clear the error flag.
Precautions:
    Detect any error in each processing, and deal appropriately with any that exist.
 
CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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Figure 5-3 An example flowchart of LIN comm unication in master mode (when FIFO is used) 
Start
Initial settings:
Set the operation mode to 3 and master mode.
Enable the serial data output, and set a baud rate.
Set an LIN Break length and a Break delimiter length.
TXE=1, TIE=0, RXE=1, RIE=1
FSEL=0, FE1=1,FE2=0, FTIE=0
Message?
YesNoWake up ?
Yes
No
LIN Break field transmission: LBR=1
Write N bytes in TDR.
RDRF=1
Receive interrupt
Receive Data1.*1
Error existing?
Error processing *2
No
Yes
*1:If an error has occurred, carry out the relevant error recovery action.
*2:If the FRE and ORE bits are 1, set the SSR:REC bit to “1” to clear the error flag.
Precautions:
    Detect any error in each processing,  and deal appropriately with any that exist.
Receive DataM.*1
 
Data field reception?
Yes (Receive)
FBYTE2 setting, FE2=1
LIN Sync field reception *1
 
RDRF=1
Receive interrupt
ID field reception *1
 
RDRF=1
Receive interrupt
Receive M bytes.*1 RDRF=1
Receive interrupt
RDRF=1
Receive interrupt
RDRF=1
Receive interrupt
No (Transmit)
 
CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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 Slave mode operations 
Figure 5-4 An example flowchart of LIN communica tion in slave mode (when FIFO is not used) 
Start
Initial settings:
Set the operation mode to 3 and 
master mode.
TXE=1,TIE=0,RXE=0,RIE=1
Connect between UART and ICU.
RXE=0, enable ICU interrupt.
LBIE=1
LBD=1
Sync Break interrupt
LBD=0, LBIE=0
Enable ICU interrupt.
ICU interrupt
Read the ICU data.
Clear the ICU interrupt flag.
ICU interrupt
Read the ICU data.
Adjust the baud rate.
RXE=1
Clear the ICU interrupt flag.
Disable an ICU interrupt.
RDRF=1
Receive interrupt
ID field reception *1
Data field 
reception?
Receive Data1.*1RDRF=1
Receive interrupt
RDRF=1
Receive interrupt
Receive DataN.*1
Set transmit Data1: TDR=Data1
TIE=1
Set transmit Data2: TDR=Data2 TDRE=1
Transmit interrupt
RDRF=1
Receive interrupt
Receive Data1.*1
TDRE=1
Transmit interrupt
Set transmit DataN: TDR=DataN TIE=0
RDRF=1
Receive interrupt
Receive DataN.*1
Error existing?Error processing *2
No (Transmit)
Yes (Receive)
Yes
Sleep mode?No
No Yes
No
Wake-up 
reception?
Wake-up 
transmission?Transmit Wake-up code.YesNo
*1:If an error has occurred, carry out the relevant error 
recovery action.
*2:If the FRE and ORE bits are “1”, set the SSR:REC bit to 1 to clear the error flag.
Precautions: Detect any error in each processing, and deal appropriately 
with any that exist.
Yes
  
CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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Figure 5-5 An example flowchart of LIN comm unication in slave mode (when FIFO is used) 
Start
Initial settings:
Set the operation mode to 3 and 
master mode.
TXE=1,TIE=0,RXE=0,RIE=1
FE1=1, FE2=0, FSEL=0
Connect between UART and ICU.
RXE=0, enable ICU interrupt.
LBIE=1
LBD=1
Sync Break interrupt
LBD=0, LBIE=0
Enable ICU interrupt.
ICU interrupt
Read the ICU data.
Clear the ICU interrupt flag.
ICU interrupt
Read the ICU data.
Adjust the baud rate. RXE=1
Clear the ICU interrupt flag. Disable an ICU interrupt.
RDRF=1
Receive interrupt
ID field reception *1
Data field 
reception?
FBYTE2 setting, FE2=1
RDRF=1
Receive interrupt
Receive N bytes.*1
Write N bytes in TDR.
RDRF=1
Receive interrupt
Receive Data1.*1
RDRF=1
Receive interrupt
Receive DataN. *1
Error existing?Error processing *2
No (Transmit)
Yes (Receive)
Yes
Sleep mode?No
No Yes
No
Wake-up 
reception?
Wake-up 
transmission?Transmit Wake-up code.YesNo
*1:If an error has occurred, carry out the relevant error recovery action.
*2:If the FRE and ORE bits are “1”, set the SSR:REC bit to “1” to clear the error flag.
Precautions:
Detect any error in each processing, and deal appropriately with any that exist.
Yes
 
 
 
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6. LIN Interface (ver. 2.1) Registers 
 
6.  LIN Interface (ver. 2.1) Registers 
The following shows a list of LIN interface (ver. 2.1) registers. 
  List of LIN interface  (ver. 2.1) registers 
Table 6-1 List of LIN interface (ver. 2.1) registers 
  bit 15                       bit 8  bit 7                        bit 0 
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control Register)
- RDR/TDR (Transmit/Receive Data Register) 
BGR1 (Baud Rate Generator Register 1)  BGR0 (Baud Rate Generator Register 0) 
LIN 
interface 
(ver. 2.1) 
- - 
FCR1 (FIFO Control Register 1)  FCR0 (FIFO Control Register 0) FIFO 
FBYTE2 (FIFO2 Byte Register)  FBYTE1 (FIFO1 Byte Register) 
 
Table 6-2 LIN interface (ver. 2.1) bit assignment 
 Bit 15  Bit 14 Bit 13Bit 12  Bit 11 Bit 10 Bit 09 Bit 08 Bit 07 Bit 06 Bit 05Bit 04Bit 03  Bit 02 Bit 01Bit 00
SCR/ 
SMR  UPCL MS LBRRIE TIE TBIERXETXEMD2MD1MD0WUCRSBL - - SOE
SSR/ 
ESCR  REC - LBDFRE ORE RDRFTDRETBI- ESBL- LBIELBL1 LBL0 DEL1DEL0
TDR/ 
RDR  - D7D6D5D4D3 D2 D1 D0
BGR1 
EXT B14 B13 B12  B11 B10 B9 B8B7 B6  B5 B4 B3  B2 B1 B0
- -  - 
FCR1/ 
FCR0 FTST1 FTST0 - FLSTE FRIIE FDRQFTIE
FSEL- FLSTFLDFSETFCL2 FCL1 FE2FE1
FBYTE2/ 
FBYTE1 FD15 FD14 
FD13FD12  FD11 FD10 FD9FD8FD7 FD6 FD5FD4FD3  FD2 FD1 FD0
 
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CHAPTER  19-4: LIN Interface  \050Ver. 2.1\051 \050LIN  Communication  Control Interface  Ver. 2.1\051 
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6. LIN Interface (ver. 2.1) Registers 
 
6.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) is used to  enable/disable a transmit/receive interrupt, 
enable/disable a transmit idle interrupt, and enable/disable data transmission and reception. 
Also, the SCR can be used to generate an LIN Break field and reset the LIN interface (ver. 
2.1). 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL MS LBR RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W    
Initial 
value  0 - - 0 0 0 0 0    
 
[bit 15] UPCL: Programmable clear bit  Initializes the internal state of LIN interface (ver. 2.1). 
If set to 1: 
  The LIN interface (ver. 2.1) is reset  directly (Software reset). However, the current register settings are 
maintained. The transmit or receive st ate is disconnected immediately. 
   The baud rate generator reloads the BGR1/0 register value and restarts operation. 
   All of transmit/receive interrup t causes (SSR:TDRE, TBI, RDRF,  FRE, ORE, LBD) are cleared. 
 
If set to 0: 
No effect. 
0 is always read during reading. 
Description Bit  During writing During reading 
0 No  effect. 
1 Programmable  clear 0 is always read. 
 
 
  Disable an  i

nterrupt first, and then execute the progra mm
 able clear instruction. 
   If the FIFO operation is used, disable it (FCR:FE2=0, FE1=0) first and then execute the programmable 
clear instruction. 
   To switch from receive operation to transmit opera tion continuously, execute the programmable clear 
instruction after data is received and write tran smit data to the Transmit Data Register (TDR). 
 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 14] MS: Master/Slave function select bit 
Selects the master or slave mode. 
If set to 0: The master mode is selected. 
If set to 1: The slave mode is selected. 
Bit Description 
0 Master  mode 
1 Slave mode 
 
[bit 13] LBR: LIN Break Field setting bit (valid in master mode only)  If this bit is set to 1, an LIN Break field (having the length set by the ESCR:LBL1/0 bit) is generated. 
Also, an LIN Break delimiter (set by  the ESCR:DEL1/0 bit) is generated. 
When written:  When 0 is written: No effect. 
When 1 is written: An LIN Break field is generated. 
When read:  0 is always read. 
Bit Description 
0 No  effect. 
1 An LIN Break field is generated.  0 is always read. 
 
 
  This  b

it setting is valid in the master mode operation only (MS=0). 
   Do not set this  b

it to 1 when an LIN Break field is being generated. 
 
[bit 12] RIE: Receive interrupt enable bit    This bit enables or  disables a

n output of receive interrupt request to the CPU. 
   If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of the  error flag bits (SSR:FRE, 
ORE) is 1, a receive interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] TIE: Transmit interrupt enable bit 
  This bit enables or disables an output  of transmit interrupt request to the CPU. 
   If the TIE and SSR:TDRE bits are 1, a  transmit interrupt request is output. 
 
Bit Description 
0  Disables a transmit interrupt. 
1  Enables a transmit interrupt. 
 
[bit 10] TBIE: Transmit bus idle interrupt enable bit    This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. 
   If the TBIE bit and SSR:TBI bit are 1, a tr ansmit bus idle interrupt request is output. 
 
Bit Description 
0  Disables the transmit bus idle interrupt. 
1  Enables the transmit bus idle interrupt. 
 
[bit 9] RXE: Data receive enable bit  This bit enables or disables a data r eception by the LIN interface (ver. 2.1). 
   If set to 0: The data frame reception is disabled. 
   If set to 1: The data frame reception is enabled. 
 
Bit Description 
0  Disables data reception. 
1  Enables data reception. 
 
 
  Data reception  

starts only after a fallin
 g edge of the start bit is input even if the data reception is enabled 
(RXE=1). 
   When the an LIN Break field is being sent in the master  mode operation, no data is received even if data 
reception is enabled (RXE=1). 
   If data reception is disabled (RXE=0), the cu rrent data reception is stopped immediately. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 8] TXE: Data transmission enable bit 
This bit enables or disables a data tran smission by the LIN interface (ver. 2.1). 
   If set to 0: The data frame transmission is disabled. 
   If set to 1: The data frame transmission is enabled. 
 
Bit Description 
0  Disables the transmission. 
1  Enables the transmission. 
 
 
If dat a

 transmission is disabled (TXE=0), the current data transmission is stopped immediately. 
  
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