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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 10] RDRF: Receive data full flag bit 
  This flag shows the state of  Receive Data Register (RDR). 
   When the receive data is loaded in  the RDR, this bit is set to 1. When data is read from the Receive 
Data Register (RDR), this bit is cleared to 0. 
   If the RDRF bit and SCR:RIE  bit are 1, a receive interrupt request is output. 
   If receive FIFO is used and if the preset amount of data is received in  receive FIFO, the RDRF bit is set 
to 1. 
   If receive FIFO is used, if both of the following co nditions are satisfied, and if the Receive Idle state 
continues more than 8 baud rate clocks, the RDRF bit is set to 1. 
  The receive FIFO idle detect en able bit (FCR1:FRIIE) is 1. 
   The preset data amount is not received an d some data remains in receive FIFO. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 clocks 
is restarted. 
   If the receive FIFO is used and if this buffer  is emptied, this bit is cleared to 0. 
 
Bit Description 
0  The Receive Data Register (RDR) is empty. 
1 The Receive Data Register (RDR) contains data. 
 
[bit 9] TDRE: Transmit data empty flag bit    This flag shows the state of  Transmit Data Register (TDR). 
   If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data. 
When data is loaded to the transmit shift register and  when the transmission is started, this bit is set to 
1 to indicate that the TDR does not have the valid data. 
   If the TDRE bit and SCR:TIE bit are 1,  a transmit interrupt request is output. 
   When the UPCL bit of the Serial Control Register (S CR) is set to 1, the TDRE bit is set to 1. 
   For the TDRE bit set/reset timing wh en transmit FIFO is used, see 2.4 Interrupt occurrence and flag set 
ti ming wh
en

 transmit FIFO is used . 
 
Bit Description 
0  The Transmit Data Register (TDR) contains data. 
1  The Transmit Data Register (TDR) is empty. 
 
[bit 8] TBI: Transmit bus idle flag bit    This bit indicates that the CSIO is not transmitting data. 
   When data is written in the Transmit Data Register (TDR), this bit is set to 0. 
   If the Transmit Data Register (TDR) is empty (TDRE=1)  and if no transmission is started, this bit is set 
to 1. 
   When the UPCL bit of the Serial Control Register (S CR) is set to 1, the TDRE bit is set to 1. 
   If this bit is 1 and if a transmit bus Idle interrupt  is enabled (SCR:TBIE=1), a transmit interrupt request 
is output. 
 
Bit Description 
0 During  data transmission 
1  No data transmission 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
5.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to set a transmit/receive data 
length and to fix the serial data output to the HIGH state. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field - SOP - - WT1 WT0 L2 L1 L0 
Attribute     R/W  - - R/W R/W R/W  R/W R/W 
Initial 
value     0 - - 0 0 0 0 0 
 
[bit 7] SOP: Serial output pin set bit    This bit sets the serial data output pin to the HIGH st ate. When this bit is set to 1, the SOUT pin is set 
to HIGH. After that, this bit needs not be set to 0. 
   When it is read, 0 is always read. 
 
Description Bit  During writing During reading 
0 No  effect. 
1 Sets the SOT pin to HIGH state.  0 is always read. 
 
 
Do not set t h

is bit during serial data transmission. 
 [bit 6:5] Reserved bits  This bit  val

ue is undefined when read. 
This bit has no effect when written. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 4:3] WT1, WT0: Data transmit/receive wait select bits 
In master operation mode, these bits set a wait count fo r continuous data transmission or reception. In slave 
operation mode, these bits are set to 00. 
   If set to 00: The SCK clocks are output continuously. 
   If set to 01: The SCK clock is output after waiting for a single-bit time. 
   If set to 10: The SCK clock is output after waiting for a two-bit time. 
   If set to 11: The SCK clock is output after waiting for a three-bit time. 
 
Bit 4  Bit 3 Description 
0 0  0 bit 
0 1 1 bit 
1 0 2 bits 
1 1 3 bits 
 
[bit 2:0] L2, L1, L0: Data length select bits  These bits set a length of transmit/receive data. 
  If set to 0b000: The 8-bit data length is set. 
   If set to 0b001: The 5-bit data length is set. 
   If set to 0b010: The 6-bit data length is set. 
   If set to 0b011: The 7-bit data length is set. 
   If set to 0b100: The 9-bit data length is set. 
 
Bit 2  Bit 1Bit 0  Description 
0 0 0  8-bit length 
0 0 1 5-bit length 
0 1 0 6-bit length 
0 1 1 7-bit length 
1 0 0 9-bit length 
 
 
Any b

it setting other than above is inhibited. 
  
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5. CSIO (Clock Sync Serial Interface) registers 
 
5.5.  Receive Data Register/Transmit Data Register 
(RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data is read from it. This register operates as 
the Transmit Data Register when data is written in it. 
 Receive Data Register (RDR) 
 
Bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      R R R R R  R R R R 
Initial 
value     0 0 0 0 0 0 0 0 0 
 
The Receive Data Register (RDR) is a 9-bit data  buffer register for serial data reception. 
   When serial data signals are sent to the Serial Input  pin (SIN pin), they are converted by a shift register 
and stored in the Receive Data Register (RDR). 
   The high-order bits are sequen tially set to 0 according to the data length as follows. 
Data length D8 D7  D6D5 D4D3 D2D1 D0 
9 bits  X X X X X X X X X 
8 bits  0 X X  X X X X X X 
7 bits  0 0 X X  X X X X X 
6 bits  0 0  0 X X  X X X X 
5 bits  0 0 0 0 X X  X X  X 
  When the received data is stored in the Receive Da ta Register (RDR), the receive data full flag bit 
(SSR:RDRF) is set to 1. If a receive interrupt is  enabled (SSR:RIE=1), a receive interrupt request is 
generated. 
   The Receive Data Register (RDR) must be read only  when the receive data full flag bit (SSR:RDRF) is 
1. When data is read from the  Serial Receive Data Register (RDR ), the receive data full flag bit 
(SSR:RDRF) is cleared to 0 automatically. 
   If a receive error occurs (SSR:ORE), data in the Receive Data Register (RDR) is invalid. 
   When the 9-bit length data is transferred, th e RDR must be read in the 16-bit access mode. 
 
 
  If th e 

receive FIFO is used and if a certain count of  data is received by the receive
  FIFO, the RDRF bit is 
set to 1. 
   If receive FIFO is used and if this buffer is  emptied, the RDRF bit is cleared to 0. 
   If receive FIFO is used and if a receive error occurs  (SSR:ORE), the receive FIFO enable bit is cleared 
and the receive data is not stored in receive FIFO. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
  Transmit Data Register (TDR) 
 
Bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      W W W W W  W W W W 
Initial 
value     1 1 1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a 9-bit data buffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to the transmit shift register. Then, the data is converted 
into serial data, and output at the serial data output pin (SOUT pin). 
   The high-order bits are sequentially set to in valid according to the data length as follows. 
Data length D8 D7 D6 D5  D4D3D2  D1 D0 
9 bits  X X X X  X X X  X X 
8 bits  Invalid X X X  X X X  X X 
7 bits  Invalid Invalid X X X X  X X X 
6 bits Invalid Invalid Invalid X X X  X X X 
5 bits Invalid Invalid InvalidInvalid X X  X X X 
  When the transmit data is written in the Transmit Da ta Register (TDR), the transmit data empty flag 
(SSR:TDRE) is cleared to 0. 
   When the transmit data is transferred to the transmit sh ift register and data transmission is started, and if 
transmit FIFO is disabled or if tr ansmit FIFO is empty, the transmit data empty flag (SSR:TDRE) is set 
to 1. 
   If the transmit data empty flag (SSR:TDRE) is 1, the next transmit data can be written in the buffer. If a 
transmit interrupt is enabled, a transmit interrupt o ccurs. The next transmit data must be written only 
after the transmit interrupt has occurred or when  the transmit data empty flag (SSR:TDRE) is 1. 
   If the transmit data empty flag (SSR:TDRE) is  0   and if transm it FIFO is disabled or transmit FIFO is full, the transmit data 
cannot be written in the Transmit Data Register (TDR). 
   When the 9-bit length data is transferred, data must be written in the TDR in the 16-bit access mode. 
 
 
  The T r

ansmit Data Register is a write-only register . While the Receive Data Register is a 
 read-only 
register. As these two registers are  allocated at the same address, the write and read values differ from 
each other. Therefore, the INC/DEC  instruction and other read-modify-write (RMW) instructions cannot 
be used. 
   For the transmit data empty flag (SSR:TDRE)  set timing when transmit FIFO is used, see 2.4 Interrupt 
occurre nce and flag set timing 
when transmi

t FIFO is used . 
 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
5.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and 
BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. 
 
Bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field - (BGR1) (BGR0) 
Attribute  - R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W  R/W R/W R/WR/W
Initial 
value  - 
0 0 0 0 0 0  0 0 0  0 0 0 0 0 0 
 
   These bits set a clock frequency division in Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). 
   The BGR1 register corresponds to the high-order  bits, and the BGR0 register corresponds to the 
low-order bits. The reload value to be counted can  be written, and the BGR1/0 set value can be read. 
   When the reload value is written in Baud Rate  Generator Registers 1 and 0 (BGR1 and BGR0), the 
reload counter starts its counting. 
 
[bit 15] Reserved bit  This bit value is undefined when read. 
This bit has no effect when written. 
 
[bit 14:8] BGR1: Baud Rate Generator Register 1 
Bit 14:8  Description 
Write Write data in reload counter bit 8 to 14. 
Read  Reads the BGR1 set value. 
 
[bit 7:0] BGR0: Baud Rate Generator Register 0 
Bit 7:0  Description 
Write Write data in reload counter bit 0 to 7. 
Read  Reads the BGR0 set value. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
 
  Data must be written in the Baud Rate Generator  Registers (BGR1 and BG
 R0) by 16-bit data accessing. 
   If the reload value is even, the HIGH and LOW width of serial clock are as follows. If the value is 
odd, the serial clock has the same HIGH and LOW signal width. 
If SMR:SCINV=0, the HIGH width of serial clock is longer for 1 cycle of bus clock. 
If SMR:SCINV=1, the LOW width of serial clock is longer for 1 cycle of bus clock. 
   Set the reload value to 3 or more. 
   If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are 
reloaded only after the counter value has reached 15h00. In order to validate the new set values 
immediately, change the BGR1/0 set values and  execute the CSIO reset instruction (SCR:UPCL). 
   If receive FIFO is used and if you wish to set the receive FIFO idle detect enable bit (FCR1:FRIIE) to 
1 and starts the slave mode operation, set the desired baud rate in BGR1/0. 
 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
5.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They must always be set to 0. 
Bit 15:14  Description 
0 Disables the FIFO test. 
1  Enables the FIFO test. 
 
 
If this 

bit is set to 1, the FIFO test is executed. 
 [bit 13] Reserved bit  This bit  val

ue is undefined when read. 
This bit has no effect when written. 
 
[bit 12] FLSTE: Re-transmit data lost detect enable bit  This bit enables the FLST bit detection. 
If set to 0: The FLST bit detection is disabled. 
If set to 1: The FLST bit detection is enabled. 
Bit Description 
0  Disables the Data Lost detection. 
1  Enables the Data Lost detection. 
 
 
If you wish

 to set this bit to 1, set the FSET bit to 1 first, and then set this bit to 1. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 11] FRIIE: Receive FIFO idle detection enable bit 
This bit sets to detect the receive id le state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0: The receive idle  state detection is disabled. 
If set to 1: The receive idle state detection is enabled. 
Bit Description 
0  Disables the receive FIFO idle detection. 
1  Enables the receive FIFO idle detection. 
 
 
In case of usi n

g Receive FIFO, set this bit to 1. 
 [bit 10] FDRQ: Transmit FIFO data request bit  This bit requ e

sts for the transmit FIFO data. 
If this bit is 1, the transmit data is being requested. If the transmit FIFO inte rrupt is enabled (FTIE=1) 
during this time, a transmit FIFO interrupt request is output. 
The FDRQ bit is set when: 
   The FBYTE (for transmission) is 0 (Transmit FIFO is empty). 
   Transmit FIFO is reset. 
 
The FDRQ bit is reset when: 
   This bit is set to 0. 
   Transmit FIFO is filled with data. 
 
Bit Description 
0  Does not request for the transmit FIFO data. 
1  Requests for the transmit FIFO data. 
 
 
  If th e FB

YTE (for transmission) is 0 , this bit cannot be set
  to 0. 
   If this bit is 0, the FSEL bit state cannot be changed. 
   If this bit is set to 1, it has no effect on the operation. 
   If a read-modify-write instruction is issued, 1 is read. 
 
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5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is  set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO select bit  This bit selects the tr ansmit or receive FIFO. 
If set to 0: Set the transmit FIFO as  FIFO1, and the receive FIFO as FIFO2. 
If set to 1: Set the transmit FIFO as  FIFO2, and the receive FIFO as FIFO1. 
Bit Description 
0 Transmit  FIFO:FIFO1; Receive FIFO:FIFO2 
1 Transmit  FIFO:FIFO2; Receive FIFO:FIFO1 
 
 
  This b it 

is not cleared by FI FO reset (FCL2=1,  FCL1
 =1). 
   To change this bit state, first disable the FIFO operation (FCR:OFE2=0, FE1=0). 
 
 
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