Fujitsu Series 3 Manual
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3. Explanation of Operations
3.2.2. Interrupts in scan conversion
This section explains interrupts in scan conversion.
Figure 3-6 FIFO interrupt settings and FIFO operations
FIFO interrupt
request FIFO stage
count settingValid FIFO
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO
Stage Count Setup Register (SFNS)...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-738.png "Page 739
3. Explanation of Operations
3.2.2. Interrupts in scan conversion
This section explains interrupts in scan conversion.
Figure 3-6 FIFO interrupt settings and FIFO operations
FIFO interrupt
request FIFO stage
count settingValid FIFO
stage count
N=5(6stages)
N=3(4stages)
FIFO readout
A/D conversion
Stop123456Stop123456Stop1 Stop
Flag clear
Flag clear
When conversion data for the number of FIFO stages (N + 1) set in SFS [3:0] in the Scan Conversion FIFO
Stage Count Setup Register (SFNS)...")
![Page 740
3. Explanation of Operations
3. One-shot mode for multiple channels
To generate an interrupt after the completion of conversion of the multiple specified channels, set the
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels
is completed, SCIF is set to 1.
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-739.png "Page 740
3. Explanation of Operations
3. One-shot mode for multiple channels
To generate an interrupt after the completion of conversion of the multiple specified channels, set the
FIFO stage count according to the number of channe ls. If eight channels are selected, set the FIFO
stage count by setting SFS [3:0] = 0x7. When the conv ersion of the last one of the selected channels
is completed, SCIF is set to 1.
An interrupt can be generated at any timing before scan completion by setting SFS [3:0] to a...")
![Page 742
3. Explanation of Operations
3.2.4. Interrupts in priority conversion
This section explains interrupts in priority conversion.
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion
FIFO Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is
generated to the CPU.
The following explains FIFO...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-741.png "Page 742
3. Explanation of Operations
3.2.4. Interrupts in priority conversion
This section explains interrupts in priority conversion.
When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion
FIFO Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D
Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is
generated to the CPU.
The following explains FIFO...")
3. Explanation of Operations 3.2.3. FIFO operations in priority conversion This section explains FIFO operations in priority conversion. Four FIFO stages are incorporated for writing priority conversion data. After reset, they are in empty state and the PEMP bit in the Priority Conversion Contro l Register is set to 1. When one A/D conversion process is completed, the conversion result, start factor (priority level), and conversion channels are written in the first FIFO stage. This resets SEMP to 0. The conversion result and conversion channels for the subsequent conversion processes are written in the corresponding FIFO stages. When such data is written in all of the 4 stages, the PFUL bit is set to 1 to indicate that FIFO is in full state. If conversion is performed and an attempt is made to write data in FIFO when FIFO is in full state, the POVR bit is set to 1 and the data is di scarded (cannot overwrite the existing data). To clear the data in FIFO, set the PFCLR bit in the Pr iority Conversion Control Register to 1. FIFO goes to the empty state and the PEMP bit is set to 1. Data in FIFO can be read sequentially by reading the Priority FIFO Data Register (PCFD). To perform byte access to this register, read the most significant byte (bit 15:8) to shift FIFO (reading the least significant byte (bit 7:0) does not shift FIFO). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 705 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.4. Interrupts in priority conversion This section explains interrupts in priority conversion. When conversion data for the number of FIFO stages (N + 1) set in PFS [1:0] in the Priority Conversion FIFO Stage Count Setup Register (PFNS) is written in FIFO, the interrupt request bit (PCIF) in the A/D Control Register (ADCR) is set to 1. If the interrupt en able bit (PCIE) is set to 1, an interrupt request is generated to the CPU. The following explains FIFO stage count interrupt methods in priority conversion. To generate an interrupt after the completion of one conversion process for the specified channel, set PFS [1:0] = 0x0. When conversion data is written in the first FIFO stage, PCIF is set to 1. If PFS [1 :0 ] is set to 0x1 or more (two stages or more), interrupts are n ot generated until the specified number of times of conversion is completed. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 706 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.5. Restrictions on reading FIFO data registers in empty state This section explains restrictions on reading FIFO data registers. Read SCFD (Scan FIFO Data Register) only when SEMP (scan conversion FIFO empty bit) = 0. Likewise, read the PCFD (Priority FIFO Data Register) only when PEMP (priority conversion FIFO empty bit) = 0. If the SCFD or PCFD is read afte r confirming that the SEMP or PEMP is 1 (FIFO is empty), an A/D conversion result may have been stored immediately before the reading. In other words, whether the value read from the SCFD or PCFD is valid or invalid cannot be judged and valid FIFO data may be discarded. Figure 3-7 Example of FIFO reading after the empty bit is set to 1 (example in scan conversion) SEMP Internal data bus Valid FIFO stage count SCFD read SEMP read SCFD read SEMP read 001 Stores new FIFO interrupt data 1 Possible to judge the data as valid because the last SEMP read value is 0 Impossible to judge the data as valid or invalid because the last SEMP read value is 1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 707 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.6. Bit placement selection for FIFO data registers This section explains bit placement selection for FIFO data registers. The A/D converter can change the bit placement for the conversion results in the Scan Conversion FIFO Data Register (SCFD) and Priority Conversion FIFO Da ta Register (PCFD) with the FDAS bit in the A/D Status Register (ADSR). The bit placement in the Scan Convers ion FIFO Data Register (SCFD) and Priority Conversion FIFO Data Register (PCFD) can be changed by setting the FDAS bit in the A/D Status Register (ADSR)(Figure 3-8 ). Wh en the FDAS b it is set t o 1, the 10-bit A/D conversion result (SD9 to SD0 and PD9 to PD0) are assigned to the LSB side (bit 9:0). This placement should be used when channel information is not required (for example, conversion of only one channel is performed) because the converted channel information (SC4 to SC0 and PC4 to PC0) is lost. In addition, because there is no information on the prio rity A/D start factor (RS) when the FDAS bit is 1, conversion at priority levels 1 and 2 must not be started together. Figure 3-8 FIFO data register bit placement SCFD register When FDAS=0 When FDAS=1 PCFD register When FDAS=0 When FDAS=1 15 SD9 14SD813SD7 12SD611SD510SD4 9SD3 8SD2 7SD16SD0504SC4 3SC32SC21SC1 0SC0 15 0 140130120110100 9SD9 8SD8 7SD76SD65SD54SD43SD32SD21SD1 0SD0 15 PD9 14PD813PD7 12PD611PD510PD4 9PD3 8PD2 7PD16PD05RS4PC4 3PC32PC21PC1 0PC0 15 0 140130120110100 9PD9 8PD8 7PD76PD65PD54PD43PD32PD21PD1 0PD0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 708 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.3. A/D comparison function The A/D comparison function compares A/D conversion results and generates interrupts. To use the comparison function, set the CMPEN bit in the A/D Comparison Control Register (bit 7 in the CMPCR register) to 1. The values set in the A/D Comparison Value Setup Register (CMPD) are compared with the most significant eight bits (AD9 to 2) of the A/D conver sion result. If the comparison result satisfies the conditions set in the A/D Comparison Control Register (CMPCR), the A/D comparison interrupt bit (CMPIF) in the ADCR register is set to 1. If the in terrupt enable bit (CMPIE) is 1, an interrupt is generated to the CPU. Two bits (AD1 to 0) on the LSB side are not compared. Because the result of A/D conversion, regardless of scan or priority, is compared before it is written to FIFO, com parison is possible when FIFO is full. If CMD1 is set to 1 (to generate an interrupt when the result is equal to or more than the CMPD set value), CMPIF is set to 1 when the conversion result is equal to the value in the A/D Comparison Value Setup Register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 709 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.4. Starting DMA The A/D converter can start DMA transfer with a scan conversion FIFO stage count interrupt request. The A/D converter can transfer scan FIFO data by connecting the interrupt signal of scan conversion from the A/D converter to DMA and starting DMA. By settin g the scan FIFO stage count to 0 (an interrupt request is generated when a conversion result is stor ed in the first stage of FIFO), DMA transfer can be performed in conjunction with A/D conversion. The setting in the DMA Transfer Request Selection Re gister as to whether the A/D converter interrupt signal is connected to the interrupt controller or DMAC should be made for DMA transfer of the interrupt controller. Figure 3-9 DMA transfer operation FIFO in terrupt reques t (DMA start req uest) FIFO s ta ge co unt setting Vali d FIFO s tag e cou nt N= 0(1s tage) FIFO readout (DM A t rans fer) A /D conv ersi onStop1 2 3 4 5 6 Stop12 345 6Stop Clea r b y DMA C A/D start 78 Cle ar by DMAC FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 710 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4. Setup procedure examples This section provides examples of setup procedures for the 10-bit A/D converter. 4.1 Scan conversion setup procedure example 4.2 Priority conversion setup procedure example 4.3 Setting the conversion time FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 711 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4.1. Scan conversion setup procedure example This section provides a scan conversion setup procedure example. Figure 4-1 Scan conversion setup procedure example Empty check readoutSCCR:SEMP = 0? Initial settings - A/D conversion channel setting (written in the SCIS register) - Sampling time setting (written in the ADST and ADSS registers) - Comparison time setting (written in the ADCT register) - Setting the FIFO stage count to 16 (setting SFNS:SFS = 0b1111) - FIFO data placement setting (setting the ADSR:FDAS bit) - Comparison function disabled (setting CMPCR:CMPEN = 0) - Interrupt disabled (setting ADCR:SCIE = 0) Start End Yes FIFO data readout (SCFD register readout) No -FIFO clear (setting SCCR:SFCLR = 1) -Conversion mode setting (setting SCCR:RPT = 0) -A/D software startup (setting SCCR:SSTR = 1) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 712 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples 4.2. Priority conversion setup procedure example This section provides a priority conversion setup procedure example. Figure 4-2 Priority conversion setup procedure example Empty check readoutPCCR:PEMP = 0? Initial settings - A/D conversion channel setting (w ritten in the PCIS register) - Sampling time setting (written in the ADST and ADSS registers) - Comparison time setting (written in the ADCT register) - Setting the FIFO stage count to 4 (setting PFNS:PFS = 0b11) - FIFO data placement setting (setting the ADSR:FDAS bit) - Comparison function disabled (setting CMPCR:CMPEN = 0) - Priority conversion interrupt enabled (setting ADCR:PCIE = 1) Start End Yes FIFO data readout (PCFD register readout) No - FIFO clear (setting PCCR:PFCLR = 1) - Conversion mode setting (setting SCCR:RPT = 0) - A/D software startup (s etting PCCR:PSTR = 1) Generation of a priority conversion interrupt request ADCR:PCIF = 1? Yes No Clearing the priority conversion interrupt request (Setting ADCR:PCIF = 0) FIFO data readout completed four times?No Yes FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-2: 10-bit A/D Converter MN706-00002-1v0-E 713 MB9Axxx/MB9Bxxx Series
4. Setup procedure examples
4.3. Setting the conversion time
The conversion time of the A/D converter is sampling time + comparison time. Two
sampling time settings can be applied to each channel. This section explains how to set and
calculate the conversion time.
Example of setting the sampling time
A sampling time is set in each of Sampling Time Setup Registers 0 and 1 (ADST0 and ADST1). Using
Sampling Time Selection Registers (ADSS3 to 0), whether Sampling Time Setup Registers 0 or 1 is used to
provide the value can be selected for each channel. This allows you to set different sampling times for
channels with different external impedances.
Sampling time = Peripheral clock (PCLK) cycle × (ST set value + 1) × STX setting multiplier
When
STXx1 and STXx0 = 00 (STx5 to STx0 set values multiplied b
y 1) are set, set STx5 to STx0 to 3
or more (2 or less must not be set). Furthermore, the sampling time conditions in Electric
Characteristics of the Data Sheet the must be satisfied.
Example of setting the comparison time
The comparison time is set in the Comparison Time Setup Register (ADCT).
Comparison time = {(CT set value (N) + 1) x 10 + 4} x Peripheral clock (PCLK) cycle
If the sam
pling or comparison time fails to meet the electrical characteristics of the A/D c
onverter, the A/D
conversion accuracy may be degraded.
Example of conversion time calculation (when PCLK = 20 MHz (50 ns cycle))
(1) Sampling time
When ST05 to 00 = 7 and STX01 and STX00 = 00 (multiplied by 1)
Sampling time = 50 ns × (7 + 1) × 1 = 400 ns
When ST15 to 10 = 19 and STX11 and STX10 = 01 (multiplied by 4)
Sampling time = 50 ns × (19 + 1) × 4 = 4 s
(2) Comparison time
When CT02 to 00 = 1
Sampling time = {(1 + 1) × 10 + 4)} × 50 ns = 1.2 s
(3) Conversion time By adding (1) and (2) together:
Conversion time for chan nels specified with the ADST0 register = 1.6 s
Conversion time for chan nels specified with the ADST1 register = 5.2 s
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 18-2: 10-bit A/D Converter
MN706-00002-1v0-E
714
MB9Axxx/MB9Bxxx Series