Fujitsu Series 3 Manual
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3. Operations of Standby Modes 3.2. Operations of TIMER modes (high speed CR timer, main timer, PLL timer, low speed CR timer, and sub timer modes) TIMER mode is used to stop supplying a base clock. This causes the CPU clock, AHB bus clock, and all APB bus clocks to be stopped, leading to the further reduction of power consumption. In this case, all functions are stopped, excluding the oscillators, PLL, hardware watchdog timer, watch counter, clock failure detector, and Low Voltage Detection Circuit. Functions of TIMER mode CPU and internal memory Enabling TIMER mode stops CPU clocks and AHB bus clocks supplied to the internal memory or DMA controller. The contents of the internal memory are held. The debug function is stopped. Peripherals In TIMER mode, all APB clocks are stopped, and all resources, excluding the hardware watchdog timer, watch counter, clock failure detector, and Low Voltage Detection Circuit, are stopped in the last state. Watch counter The watch counter has no effect in TIMER mode. It continues operations based on the configuration that is provided before the transition to TIMER mode. Oscillator clocks Ta b l e 3 - 2 (Clock operation states in TIMER modes ) shows the status of each oscillator clock. Reset and interrupt Reset and interrupt are available to return from TIMER mode. External bus The external bus is stopped in TIMER mode. Status of pin The system can control whether to ho ld the state just before the external pin changes to TIMER mode or change to the high impedance state depending on the setting of the SPL bit in the Standby Mode Control Register (STB_CTL). TIMER mode setting procedure Execute the following steps to change to TIMER mode. 1. Write 0x1ACC to the KEY bit and 0b00 to the STM bit of the Standby Mode Control Register (STB_CTL). Use the SPL bit to set the status of each pin in TIMER mode. 2. Set 1 to the SLEEPDEEP bit of the Cortex-M3 System Control Register. 3. Execute the WFI or WFE instruction. The system changes to the appropriate TIMER mode according to the current clock mode indicated in the RCM bit of the System Clock Mode Control Register (SCM_CTL). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 115 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes Return from TIMER mode The CPU returns from TIMER mode in one of the following cases. Return by reset If a reset (INITX pin input reset, low-voltage detection reset, hardware watchdog reset, or clock failure detection reset) occurs, the CPU changes to high speed CR run mode regardless of clock mode. Software watchdog reset and anomalous frequency detectio n reset are not available in this mode; therefore, the CPU cannot return by those resets. Return by interrupt If an effective NMI interrupt, external interrupt, hard ware watchdog timer interrupt, USB wake up interrupt, watch counter interrupt, or low voltage detection in terrupt request is received in TIMER mode, the CPU returns from TIMER mode and changes to RUN mode to fit clock mode indicated in the RCM bit of SCM_CTL. Table 3-6 Operation modes after the CPU returned from TIMER mode by interrupt Status of master clock before transition to TIMER mode RCM=000 (High speed CR oscillator) RCM=001 (Main oscillator) RCM=010 (PLL oscillator) RCM=100 (Low speed CR oscillator) RCM=101 (Sub oscillator) Operation modes after return by interrupt High speed CR run mode Main run mode PLL run mode Low speed CR run mode Sub run mode Waiting for oscillation stabilization at return When the CPU returns by reset, it waits for the stabili zation of high and low speed CR clock oscillations. If the CPU returns by interrupt, it does not need to wait for oscillation to stabilize. Waiting for the stabilization of the built-in regulator voltage at return To return from low speed CR timer mode or sub timer mode by reset or interrupt, the voltage stabilization wait time (a few hundred of s) of the built-in regulator is ensured automatically. After the wait time has lapsed, return operations are performed. When an interrupt priority used for return is not set at a level to return t he CPU, clock will be returned with the interrupt but the CPU remains stop state without returning. In order to do this, be sure to set the interrupt priority at a level which CPU is able to return. If the transition to TIMER mode is made during debu gging, as the clock to the CPU stops, a return to RUN mode cannot be performed by the ICE. Use a return by reset or interrupt. In case of transiting to the Low speed CR timer mode or Sub timer mode, ensure that the flash memory automatic programming algorithm is term inated before executing transition. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 116 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes 3.3. Operations of STOP mode STOP mode is used to stop all oscillating operations. Enabling this mode stops all functions, excluding the Low Voltage Detection Circuit. This therefore allows data to be held with the minimum power consumption. Functions of STOP mode CPU and internal memory Enabling STOP mode stops CPU clocks and AHB bus clocks supplied to the internal memory or DMA controller. The contents of the internal memory are held. The debug function is stopped. Peripherals All APB bus clocks are stopped, and all resources, excluding the Low Voltage Detection Circuit, are stopped in the last state. Oscillator clocks All oscillator clocks are stopped. Reset and interrupt Reset and interrupt are available to return from STOP mode. External bus The external bus is stopped in STOP mode. Status of pin The system controls whether to hold the state just before the external pin changes to STOP mode or change to the high impedance state depending on the setting of the SPL bit in the Standby Mode Control Register (STB_CTL). STOP mode setting procedure Execute the following steps to change to STOP mode. 1. Write 0x1ACC to the KEY bit and 0b10 to the STM bit of the Standby Mode Control Register (STB_CTL). Use the SPL bit to set the status of each pin in STOP mode. 2. Set 1 to the SLEEPDEEP bit of the Cortex-M3 System Control Register. 3. Execute the WFI or WFE instruction. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 117 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes Return from STOP mode The CPU returns from STOP mode in one of the following cases. Return by reset If a reset (INITX pin input reset or low-voltage detec tion reset) occurs, the CPU changes to the high speed CR run mode regardless of clock mode. Software watchdog reset, hardware watch dog reset, clock failure detection reset, and anomalous frequency detection reset are not available in this mode; th erefore, the CPU cannot return by those resets. Return by interrupt If an effective NMI interrupt, external interrupt, USB wake up interrupt, or low voltage detection interrupt request is received in STOP mode, the CPU returns from STOP mode and changes to RUN mode to fit clock mode indicated in the RCM bit of SCM_CTL. Table 3-7 Operation modes after the CPU returned from the STOP mode by interrupt Status of master clock before changing to STOP mode RCM=000 (High speed CR oscillator) RCM=001 (Main oscillator) RCM=010 (PLL oscillator) RCM=100 (Low speed CR oscillator) RCM=101 (Sub oscillator) Operation modes after return by interrupt High speed CR run mode Main run mode PLL run mode Low speed CR run mode Sub run mode Waiting for oscillation stabilization at return When the CPU returns by reset, it waits for the stabili zation of high and low speed CR clock oscillations. If the CPU returns by interrupt, the oscillation stabiliza tion wait state varies depending on the master clock that is output before the CPU changes to STOP mode as shown in Ta b l e 3 - 8. Table 3-8 Waiting for oscillation to stabilize at return from STOP mode by interrupt Status of master clock before changing to STOP mode RCM=000 (High speed CR oscillator) RCM=001 (Main oscillator) RCM=010 (PLL oscillator) RCM=100 (Low speed CR oscillator) RCM=101 (Sub oscillator) High speed CR clock ON ON ON OFF OFF Main clock MOSCE=0: OFF MOSCE=1: ON ON ON OFF OFF PLL clock OFF PLLE=0: OFF PLLE=1: ON ON OFF OFF Low speed CR clock ON ON ON ON ON Oscillation stabilization waiting after return by interrupt Sub clock SOSCE=0: OFF SOSCE=1: ON SOSCE=0: OFF SOSCE=1: ON SOSCE=0: OFF SOSCE=1: ON SOSCE=0: OFF SOSCE=1: ON ON Waiting for the stabilization of the built-in regulator voltage at return When the CPU returns from STOP mode, the voltage stabilization wait time (a few hundred of s) of the built-in regulator is ensured automatically. After the wa it time has lapsed, return operations are performed. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 118 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes When an interrupt priority used for return is not set at a level to return t he CPU, clock will be returned with the interrupt but the CPU remains stop state without returning. In order to do this, be sure to set the interrupt priority at a level which CPU is able to return. If the transition to STOP mode is made during debugging, as the clock to the CPU stops, a return to RUN mode cannot be performed by the ICE. Use a return by reset or interrupt. In case of transiting to the STOP mode, ensure that the flash memory automatic programming algorithm is terminated before executing transition. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 119 MB9Axxx/MB9Bxxx Series
4. Standby Mode Setting Procedure Examples 4. Standby Mode Setting Procedure Examples This section provides standby mode setting procedure examples. Figure 4-1 Main timer mode setting procedure example Write KEY=0x1ACC and STM=0b00 to the STB_CTL Register together. SLEEPDEEP=1 setting End Start Execute the WFI or WFE instruction. NoUSB used? Yes Write SUSPIE=0 to the UDCIE Register.Write USTP=1 to the UDCC Register. Write UCEN=0 to the UCCR Register. writing Change to main timer mode. NoUCEN=0? Yes NoCAN used? Yes Write Init=1 to the CTRLR Register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 120 MB9Axxx/MB9Bxxx Series
4. Standby Mode Setting Procedure Examples Figure 4-2 Stop mode setting procedure example (Main clock is selected as a master clock.) Write KEY=0x1ACC and STM=0b10 to the STB_CTL Register together. SLEEPDEEP=1 setting End Start Execute the WFI or WFE instruction. NoUSB used? Yes Write SUSPIE=0 to the UDCIE Register.Write USTP=1 to the UDCC Register. Write UCEN=0 to the UCCR Register. writing Change to STOP mode. NoUCEN=0? Yes NoCAN used? Yes Write Init=1 to the CTRLR Register. In case of trans iting to t he STOP m ode, ensure th at t he flash memory automatic programming algorithm is terminated before executing transition. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 121 MB9Axxx/MB9Bxxx Series
5. List of Low Power Consumption Registers 5. List of Low Power Consumption Registers This section explains the configuration and functions of the registers used in standby mode. List of Low Power Consumption Registers Abbreviation Register name See STB_CTL Standby Mode Control Register 5.1 For th e Clock Mode Selection Regi ster, refer to Chap ter Clocks. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 122 MB9Axxx/MB9Bxxx Series
5. List of Low Power Consumption Registers 5.1. Standby Mode Control Register (STB_CTL) The Standby Mode Control Register controls TIMER or STOP mode. The value written to the SPL or STM bit is effective only when 0x1ACC is simultaneously written to the KEY bit. Bit 31 30 29 28 27 2625242322212019 18 1716 Field KEY Attribute R/W Initial value 0x0000 Bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field Reserved SPLReserved STM Attribute - R/W- R/WR/W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [bit31:16] KEY: Standby mode control write control bit This bit releases the SPL or STM bit writing control. The value written to the SPL or STM bit is effec tive only when 0x1ACC is written to the KEY bit. If a value other than 0x1ACC is written to the KEY b it, the value written to the SPL or STM bit is not effective. 0x0000 is always read in read mode. [bit15:5] Reserved: Reserved bits 0 is always set in read mode. This bit has no effect in write mode. [bit4] SPL: Standby pin level setting bit This bit sets the status of external pin in TIMER or STOP mode. Bit Description 0 Holds the status of each external pin in TIMER or STOP mode. [Initial value] 1 Sets the status of each external pin to high impedance in TIMER or STOP mode. [bit3:2] Reserved: Reserved bits 0 is always set in read mode. This bit has no effect in write mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 123 MB9Axxx/MB9Bxxx Series
5. List of Low Power Consumption Registers FUJITSU SEMICONDUCTOR LIMITED Chapter: Low Power Consumption Mode FUJITSU SEMICONDUCTOR CONFIDENTIAL 27 [bit1:0] STM: Standby mode selection bit This bit selects whether to change to TIMER or STOP mode. Bit1 Bit0 Description 0 0 TIMER mode [Initial value] 0 1 Setting disabled 1 0 STOP mode 1 1 Setting disabled The value written to the SPL or STM bit in the Stan dby Mode Control Register (STB_CTL) is effective only when 0x1ACC is simultaneously written to the KEY bit. If a value other than 0x1ACC is written to the KEY bit, the value written to the SPL or STM bit becomes invalid. CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 124 MB9Axxx/MB9Bxxx Series