Fujitsu Series 3 Manual
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3. Operations Differences between software watchdog timer and hardware watchdog timer Ta b l e 3 - 6 shows the major differences between software watchdog timer an d hardware watchdog timer. Table 3-6 Differences between software watchdog timer and hardware watchdog timer Software Watchdog Hardware Watchdog Count clock Divided clock of APB CLKLC Read value of the value register Synchronous reading Reading possible Asynchronous reading Only during tool break, a correct value can be read. Except during tool break, an inaccurate value may be read. Initial value of watchdog interrupt setting and reset setting Disable (No watchdog operation) Enable (With a watchdog operation) Register lock function initial state No lock (Software locks af ter activation) Lock (Hardware locks from the activation) Releasing lock Writing 0x1ACCE551 to lock register to release all lock for the registers Writing 0x1ACCE551 to lock register to release all lock for the registers except WDG_CTL Wdog_Control/ WDG_CTL register Releasing separate lock None Writing 0xE5331AAE to lock register to release lock of WDG_CTL register Relock conditions Writing a value other than 0x1ACCE551 to the lock register locks all the registers again. After releasing lock for the registers except WDG_CTL, the lock is resumed under any of the following conditions: Writing a value other than 0x1ACCE551 or 0xE5331AAE to WDG_LCK Writing to WDG_LDR Writing to WDG_CTL Writing to WDG_ICL again After releasing lock for the registers including WDG_CTL, lock is resumed under any of the following conditions: Writing a value other than 0x1ACCE551 to WDG_LCK Writing to WDG_LDR Writing to WDG_ICL Writing to WDG_CTL Initial value of load register 0xFFFFFFFF 0x0000FFFF Bit number of clear register 32 bits 8 bits Clear register access Clear by writing an arbitrary value Clear by writing an arbitrary value, and then writing a reversal value of the arbitrary value FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 325 MB9Axxx/MB9Bxxx Series
4. Setting Procedure Example 4. Setting Procedure Example This section explains a setting procedure example of watchdog timer. Software watchdog timer Figure 4-1 Setting procedure example of software watchdog timer Start setting FUJITSU SEMICONDUCTOR LIMITED Write interval time to load register (WdogLoad) Write 0x1ACCE551 to WdogLock Access to control register (WdogControl) interrupt and reset enable Access WdogIntClr and clear watchdo g counter Write WdogLock with a value other than “0x1ACCE551” Watchdog counter underflow ? Interrupt flag=1 ? Watchdog reset is generated Watchdog interrupt is generated No Set interval time ? No Ye s Ye s END Release lock Ye s No Activate watchdog timer Write WdogLock with a value other than “0x1ACCE551” Set lock process interrupts Set lock again CHAPTER 11: Watchdog timer MN706-00002-1v0-E 326 MB9Axxx/MB9Bxxx Series
4. Setting Procedure Example Hardware watchdog timer Figure 4-2 Setting procedure example of hardware watchdog timer FUJITSU SEMICONDUCTOR LIMITED Activate hardware watchdog timer INTEN=0 Write interval time to load register (WDG_LDR) Write 0x1ACCE551 to WDG_LCK Access to control register (WDG_CTL) set interrupt and reset enable Access WDG_ICL and write arbitrary value Automatically lock registers again Watch ow ? dog counter underfl Interrupt flag=1 ? Watchdog reset is generated Watchdog interrupt is generated Release lock INTEN=1 Ye s Ye s NoNo END Write 0xE5331AAE to WDG_LCK Access WDG_ICL and write reversal value of arbitrary value to clear watchdog counter Set interval time ? No Ye s Change settings of WDG _CTL? No Write 0x1ACCE551 to WDG_LCK Ye s Release lock Automatically lock registers again Write 0x1ACCE551 to WDG_LCK Release lock Automatically lock registers again process interrupts CHAPTER 11: Watchdog timer MN706-00002-1v0-E 327 MB9Axxx/MB9Bxxx Series
5. Operation Example 5. Operation Example This section shows an operation example of the watchdog timers. Software watchdog timer Figure 5-1 Operation example of software watchdog timer Watchdog counter value Initial value 0xFFFFFFFF Operation halts Operation halts Set value example 0x111FFFFF Set value example 0x0000FFFF Time 1. Interval setting 0x111FFFF3. Watchdog counter clear7. Transit to STOP mode FUJITSU SEMICONDUCTOR LIMITED 1. Set SWC_PSR, WDGT_CTL before activation. Write to WdogLoad register to set interval time. The interval time is not reflected because the watchdog is not activated. The count value is the initial value. 2. Access to WdogControl register, and write INTEN=1 to activate the watchdog. At this time, the interval time is reflected and decrementing will be started from the value set in 1. 3. Access to WdogIntClr register, and write an ar bitrary value to clear the watchdog counter. At this time, the set value will be the value set in 2. 4. Access to WdogIntClr register, and write an ar bitrary value to clear the watchdog counter. At this time, the set value will be the value set in 2. 5. Without clearing the counter, an interrupt will be generated underflow. At this time, the set value will be the value set in 2. 6. Access to WdogLoad register to change interval time. At this time, the down count value will be cleared to the set value. 7. Transit to STOP mode. The software watchdog will be stopped by this. 8. Release STOP mode. The down counter is re started. The count value is not cleared. (Note) Decrementing will be restar ted after oscillation wait stabilization is completed, and the base clock starts its operation. 2. INTEN=1 activate watchdog 4. Watchdog counter clea r 5. Un w derflo interrupt is generate 9. t Underflow rese is generated 6. Interval setting change 0x0000FFFF8. Release STOP mode CHAPTER 11: Watchdog timer MN706-00002-1v0-E 328 MB9Axxx/MB9Bxxx Series
5. Operation Example 9. A software watchdog reset will be generated when the second underflow is generated without clearing the interrupt WdogIntClr register. The software watchdog timer stops its operation by generating a reset. Release of the lock re gister is required to access each register. It is omitted in the ope ration example. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 329 MB9Axxx/MB9Bxxx Series
5. Operation Example Hardware watchdog timer Figure 5-2 Operation example of hardware watchdog timer FUJITSU SEMICONDUCTOR LIMITED Watchdog counter value Set value example 0xFFFFFFFF Initial value 0x0000FFFF Time 3. Watchdog counter clea r1. t af Operation star ter power-o5. P Release STO mode n 7. Underflow reset generated 4. Transit to STOP mode2. Interval setting 0xFFFFFFFF 6. Underflow interrupt generated 1. Hardware watchdog timer starts operation after turning on the power. The initial value of the count value is 0x0000FFFF. 2. Access to WDG_LDR register to change interval time. At this time, the decremented value will be cleared to the set value. 3. Access to WDG_ICL register, and write an arbitrary va lue and then write a reversal value of arbitrary value to clear the watchdog counter. At this time, the set value will be the value set in 2. 4. Transit to STOP mode. The hardware watchdog will be stopped by this. 5. Release STOP mode. The down counter is re started. The count value is not cleared. (Note) Decrementing will be restar ted after oscillation wait stabilization is completed, and the base clock starts its operation. 6. Without clearing the counter, an interrupt will be generated underflow. At this time, the set value will be the value set in 2. 7. A hardware watchdog reset will be generated when the second underflow is generated without clearing the interrupt WDG_IC register. The count value returns to the initial value and decrementing is started. Release of the lock re gister is required to access each register. It is not mentione d i n the operation example. CHAPTER 11: Watchdog timer MN706-00002-1v0-E 330 MB9Axxx/MB9Bxxx Series
6. Registers 6. Registers This section explains the registers of clock generation. Table 6-1 List of registers for the watchdog timer Register Name Explanation Reference WdogLoad Software watchdog timer load register 6.1 WdogValue Software watchdog timer value register 6.2 WdogControl Software watchdog timer control register 6.3 WdogIntClr Software watchdog timer clear register 6.4 WdogRIS Software watchdog timer interrupt status register 6.5 WdogLock Software watchdog timer lock register 6.6 WDG_LDR Hardware watchdog timer load register 6.7 WDG_VLR Hardware watchdog timer value register 6.8 WDG_CTL Hardware watchdog timer control register 6.9 WDG_ICL Hardware watchdog timer clear register 6.10 WDG_RIS Hardware watchdog timer interrupt status register 6.11 WDG_LCK Hardware watchdog timer lock register 6.12 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 331 MB9Axxx/MB9Bxxx Series
6. Registers 6.1. Software Watchdog Timer Load Register (WdogLoad) WdogLoad register sets the cycle of the software watchdog timer. Register configuration bit 31 0 Field WdogLoad Attribute R/W Initial value 0xFFFFFFFF Register function [bit31:0] WdogLoad : Interval cycle setting bit bit31:0 Explanation In case of writing Sets the cycle of the software watchdog. The initial value is 0xFFFFFFFF. The minimum value for writing is 1. When 0 is written, an interrupt will be generated. (A reset may be generated by setting.) In case of reading A set value can be read. The initial value 0xFFFFFFFF is read. During watchdo g ti mer operation, if the value of W dogLoad is mod ified, the value of WdogLoad will be reflected to the timer counter, and counting is continued. During the watchdog timer is halting, if the value of WdogLoad is modified, the value of WdogLoad will be reflected to the timer counter at activation. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 332 MB9Axxx/MB9Bxxx Series
6. Registers 6.2. Software Watchdog Timer Value Register (WdogValue) WdogValue register can read the current value of the software watchdog timer. Register configuration bit 31 0 Field WdogValue Attribute R Initial value 0xFFFFFFFF Register function [bit31:0] WdogValue : Counter value bit bit31:0 Explanation In case of writing No effect. In case of reading The count value of the current watchdog counter is read. The initial value 0xFFFFFFFF is re ad if reading before activation. See Debug Break Watchdog Timer Control Register in the chapter of Clock for the setting of watchdog timer at tool break. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 333 MB9Axxx/MB9Bxxx Series
6. Registers 6.3. Software Watchdog Timer Control Register (WdogControl) WdogControl register sets enable/disable of the software watchdog timer. Register configuration bit 7 2 1 0 Field Reserved RESEN INTEN Attribute - R/W R/W Initial value - 1’b0 1’b0 Register function [bit7:2] res : Reserved bits 0b000000 is read from these bits. In case of writing, set 0b000000. [bit1] RESEN : Reset enable bit of the software watchdog bit Explanation In case of reading Register value is read. In case of writing 0 A watchdog reset is disabled. In case of writing 1 A watchdog reset is enabled. [bit0] INTEN : Interrupt and counter enable bit of the software watchdog bit Explanation In case of reading Register value is read. In case of writing 0 A watchdog interrupt is disabled. A watchdog counter is disabled. In case of writing 1 A watchdog interrupt is enabled. A watchdog counter is enabled. Writin g 1 to the watchdog counter loads an interval cycle value from WdgLoad and the software watchdog timer is activ ated. Writing 0 to INTEN stops the watchdog counter. Th e watchdog counter reloads the cycle value from WdgLoad when 1 is written again and reactivated. The watchdog timer can be activated by enabling IN TEN only. The watchdog timer is not activated by enabling RESEN only. To activate the watchd og timer, INTEN should be enabled. See 3. Operations fo r more details. Wr itin g 0 to INTEN clears the interrupt flag in soft ware watchdog interrupt status register (WdogRIS). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 334 MB9Axxx/MB9Bxxx Series