Fujitsu Series 3 Manual
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![Page 688
3. Operations
3. Operations
This section explains the operation of Quad Position & Revolution Counter.
Operation of position counter
The position counter receives an input signal from AIN or BIN external pin as an event of count clock, and
increments or decrements the counter. As listed in Table 3-1, the position counter can select a counting
mode by setting
of the position counter mode bits (QCR:PCM[1:0]) of a control register. The counting
conditions depend on the selected count...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-687.png "Page 688
3. Operations
3. Operations
This section explains the operation of Quad Position & Revolution Counter.
Operation of position counter
The position counter receives an input signal from AIN or BIN external pin as an event of count clock, and
increments or decrements the counter. As listed in Table 3-1, the position counter can select a counting
mode by setting
of the position counter mode bits (QCR:PCM[1:0]) of a control register. The counting
conditions depend on the selected count...")
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3. Operations
PC_Mode1: Up/down count mode
An external signal entered from AIN or BIN external pin is receive d as the counting clock, and the
position counter is counted up or down.
In this mode, the position counter is counted up when an active edge of AIN signal is detected. When an
active edge of BIN signal is detected, the position counter is counted down.
Figure 3-1 Operations in up/down count mode (QCR:AES[1:0]=10, QCR:BES[1:0]=10, QCR:SWAP=0)
23432
+1 +1 +1 -1 -1
AIN...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-688.png "Page 689
3. Operations
PC_Mode1: Up/down count mode
An external signal entered from AIN or BIN external pin is receive d as the counting clock, and the
position counter is counted up or down.
In this mode, the position counter is counted up when an active edge of AIN signal is detected. When an
active edge of BIN signal is detected, the position counter is counted down.
Figure 3-1 Operations in up/down count mode (QCR:AES[1:0]=10, QCR:BES[1:0]=10, QCR:SWAP=0)
23432
+1 +1 +1 -1 -1
AIN...")
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3. Operations
Table 3-4 Counting in 4-time frequency multiplication mode (QCR:AES[1:0]=11, QCR:BES[1:0]=11)
Edge detection pin Detection edge Level Check pinInput level Counting
direction Figure 3-3
Timing
Rising edge High Up (1)
Rising edge Low Down (2)
Falling edge High Down (3)
BIN
Falling edge AIN
Low Up (4)
Rising edge High Down (5)
Rising edge Low Up (6)
Falling edge High Up (7)
AIN
Falling edge BIN
Low Down (8)
Figure 3-3 Operation in 4-time frequency...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-690.png "Page 691
3. Operations
Table 3-4 Counting in 4-time frequency multiplication mode (QCR:AES[1:0]=11, QCR:BES[1:0]=11)
Edge detection pin Detection edge Level Check pinInput level Counting
direction Figure 3-3
Timing
Rising edge High Up (1)
Rising edge Low Down (2)
Falling edge High Down (3)
BIN
Falling edge AIN
Low Up (4)
Rising edge High Down (5)
Rising edge Low Up (6)
Falling edge High Up (7)
AIN
Falling edge BIN
Low Down (8)
Figure 3-3 Operation in 4-time frequency...")
![Page 693
3. Operations
Operation of revolution counter
When the revolution counter receives an input from the ZIN pin (having the counte r clear function) or an
output of position counter (underflow or overflow), it is counted up or down. A rising edge, a falling edge,
or both can be set as the active edge of ZIN signal.
The counting conditions of revolution counter depend on the selected mode as follows.
RC_Mode0 (QCR:RCM[1:0]=00)
The revolution counter is disabled.
When the ZIN signal...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-692.png "Page 693
3. Operations
Operation of revolution counter
When the revolution counter receives an input from the ZIN pin (having the counte r clear function) or an
output of position counter (underflow or overflow), it is counted up or down. A rising edge, a falling edge,
or both can be set as the active edge of ZIN signal.
The counting conditions of revolution counter depend on the selected mode as follows.
RC_Mode0 (QCR:RCM[1:0]=00)
The revolution counter is disabled.
When the ZIN signal...")
3. Operations Table 3-4 Counting in 4-time frequency multiplication mode (QCR:AES[1:0]=11, QCR:BES[1:0]=11) Edge detection pin Detection edge Level Check pinInput level Counting direction Figure 3-3 Timing Rising edge High Up (1) Rising edge Low Down (2) Falling edge High Down (3) BIN Falling edge AIN Low Up (4) Rising edge High Down (5) Rising edge Low Up (6) Falling edge High Up (7) AIN Falling edge BIN Low Down (8) Figure 3-3 Operation in 4-time frequency multiplication mode (QCR:AES[1:0]=11, QCR:BES[1:0]=11, QCR:SWAP=0) AIN BIN QPCR23457 68910 11 108 97643 5 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 (4) (6) (1) (7) (4) (6) (1) (7) (8) (2) (5) (3) (8) (2) (5) (3) (4) (6) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 655 MB9Axxx/MB9Bxxx Series
3. Operations PC_Mode3: Count mode with direction A signal entered from the BIN external pin is receive d as the counting clock, and an input level of the signal entered form the AIN external pin is used for count direction control for counter up/down counting. In this mode, when an active edge of BIN signal is detected, the AIN signal level is checked and the position counter counted up or down. A rising edge, a falling edge, or both can be set as the active edge. Table 3-5 Counting in the direction control counting mode Edge detection pin Detection edge Level Check pinInput level Counting direction Figure 3-4 Timing Active edge High Up (1) BIN Active edge AIN Low Down (2) Figure 3-4 Operation in the direction control counting mode (QCR:AES[1:0]=00, QCR:BES[1:0]=10, QCR:SWAP=0) AIN BIN QPCR +1+1+1-1 -1 (1) (1) (2)(2) (1) 2343 2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 656 MB9Axxx/MB9Bxxx Series
3. Operations Operation of revolution counter When the revolution counter receives an input from the ZIN pin (having the counte r clear function) or an output of position counter (underflow or overflow), it is counted up or down. A rising edge, a falling edge, or both can be set as the active edge of ZIN signal. The counting conditions of revolution counter depend on the selected mode as follows. RC_Mode0 (QCR:RCM[1:0]=00) The revolution counter is disabled. When the ZIN signal is used for counter clear func tion (QCR:CGSC=0), the active edge of ZIN signal is reset. Also, the position counter is reset when this counter overflows. Figure 3-5 RC_Mode0 operation (QPRC Maximum Position Register QMPR=9, QCR:CGSC=0) QPCR23013 2456978 0134 2 ZIN 0 QRCR At an active edge of ZIN signal, the QPCR is reset. The revolution counter is disabled. When PC overflows, the QPCR is reset. The revolution counter is disabled. QPCR: QPRC Position Count Register QRCR: QPRC Revolution Count Register RC_Mode1 (QCR:RCM[1:0]=01) When ZIN signal is used for the counter clear function (QCR:CGSC=0), the revolution counter is operated only an active edge of ZIN signal (but an input from the position counter is ignored). When an active edge of ZIN signal is detected during incrementing of position counter (QICR:DIRPC=0), the revolution counter is counted up. When an active edge of ZIN is detected during decrementing of position counter (QICR:DIRPC=1), it is counted down. When the ZIN signal is used for counter clear func tion (QCR:CGSC=0), the position counter is reset only at an active edge of ZIN signal. The position counter is not reset even when an overflow of position counter is detected. When an overflow of position counter is detected, the position counter is counted up and the overflow flag (QICR:OFDF) is set to logical 1. Figure 3-6 RC_Mode1 operation (QPRC Maximum Position Register QMPR=9, QCR:CGSC=0) QPCR23013 245697 8 10 1113 14 12 ZIN 0 QRCR1 At an active edge of ZIN signal, - QPCR is reset. - QRCR is incremented. An overflow of QMPR value is ignored. - No QPCR is reset. - No QRCR is incremented. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 657 MB9Axxx/MB9Bxxx Series
3. Operations When an active edge of ZIN signal and an active edge which counts down position counter are detected at the same time duri ng incrementing of position counter (QICR:DIRPC=0), the revolution counter is counted down. When an active edge of ZIN signal and an active edge which counts up position counter are detected at the same time during decrementing of position c ounter (QICR:DIRPC=1), the revolution counter is counted up. When an active edge of ZI N signal, an active edge of AIN signal, and an active edge of BIN signal are detected at the same time, the revolution counter is counted up or down in accordance with the last position counter directio n bit (QICR:DIRPC). RC_Mode2 (QCR:RCM[1:0]=10) The revolution counter is counted up or down only by the output value of position counter. The position counter is reset only when an overflow of position counter is detected (but an event of ZIN signal is ignored). If an overflow of position counter is detected in any of 3 position counter modes (PC_Mode1, PC_Mode2 and PC_Mode3), the position counter is counted up. If an underflow of it is detected, the position counter is counted down. Figure 3-7 RC_Mode2 operation (QPRC Maximum Position Register QMPR=9) QPCR23457 6890312 4578 6 ZIN 0 QRCR1 The input is ignored at an active edge of ZIN signal. When PC overflows, - QPCR is reset. - QRCR is incremented. RC_Mode3 (QCR:RCM[1:0]=11) In this mode, the revolution counter is operated with an output of position counter and when the ZIN signal is used for the counter clear function (QCR:CGSC=0), the revolution counter is also counted up or down at an active edge of ZIN signal. When an active edge of ZIN signal is detected during incrementing of position counter (QICR:DIRPC=0) or when an overflow of position counter is detected, the revolution counter is counted up. When an active edge of ZIN signal is detected during decrementing of position counter (QICR:DIRPC=1) or when an un derflow of position counter is detected, the revolution counter is counted down. When the ZIN signal is used for the counter clear function (QCR:CGSC=0), the position counter is reset at an active edge of ZIN signal or at detection of position counter overflow. FUJITSU SEMICON DUCT OR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 658 MB9Axxx/MB9Bxxx Series
3. Operations
Figure 3-8 RC_Mode3 operation (QPRC Maximum Position Register QMPR=9, QCR:CGSC=0)
QPCR23013
2456978 0134
2
ZIN
0
QRCR12
At an active edge of ZIN signal,
- QPCR is reset.
- QRCR is incremented. When PC overflows,
- QPCR is reset.
- QRCR is incremented.
When an acti
ve edge of ZIN signal and an active edge which counts down position counter are detected
at the same time du ri
ng incrementing of position counter (QICR:DIRPC=0), the revolution counter is
counted down.
When an active edge of ZIN signal and an active edge which counts up position counter are detected at
the same time during decrementing of position c ounter (QICR:DIRPC=1), the revolution counter is
counted up.
When an active edge of ZI N signal, an active edge of AIN signal, and an active edge of BIN signal are
detected at the same time, the revolution counter is counted up or down in accordance with the last
position counter directio n bit (QICR:DIRPC).
Absolute value of positions
In RC_Mode2 and 3 mode (when the revolution counter operates with an output of position counter), each
position has the following absolute value.
QPRC Position Count Register (QPCR) + QPRC Revolution Count Register (QRCR) × (QPRC
Maximum Position Register (QMPR) +1)
Example: Time measurement The revolution counter counts the hours, an d the position counter counts the minutes.
If QMPR=59, QPCR=20, and QRCR=5
Time = 20 + 5 × (59 + 1)
= 320 minutes. This is the absolute value in position counter units (minutes).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17: Quad Position & Revolution Counter
MN706-00002-1v0-E
659
MB9Axxx/MB9Bxxx Series
3. Operations Quad Position & Revolution Counter interrupts The following table defines the conditions where an interrupt request of Quad Position & Revolution Counter can generate. Table 3-6 Generation conditions of Quad Position & Revolution Counter interrupt requests Interrupt request Interrupt request flag Interrupt request is enabled if Interrupt request is cleared if Count inversion interrupt request QICR: CDCF=1 QICR: CDCIE=1 QICR:CDCF is set to 0. Zero index interrupt request QICR: ZIIF=1 QICR:ZIIF is set to 0. Overflow interrupt request QICR: OFDF=1 QICR:OFDF is set to 0. Underflow interrupt request QICR: UFDF=1 QICR: OUZIE=1 QICR:UFDF is set to 0. PC and RC match interrupt request QICR: QPRCMF=1 QICR: QPRCMIE=1 QICR.QPRCMF is set to 0. PC match interrupt request QICR: QPCMF=1 QICR: QPCMIE=1 QICR:QPCMF is set to 0. PC match and RC match interrupt request QICR: QPCNRCMF=1 QICR: QPCNRCMIE=1 QICR:QPCNRCMF is set to 0. Outrange interrupt request QECR: ORNGF=1 QICR: ORNGIE=1 QECR:QRNGF is set to 0. QICR: QPRC Interrupt Control Register QECR: QPRC Extension Control Register FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 660 MB9Axxx/MB9Bxxx Series
3. Operations Interrupts of position counter Figure 3-9 Position counter interrupt timing (RC_Mode0, RC_Mode2 or RC_Mode3) Time PC counting 0x0000 QPCCR value QMPR value Z input Count inversion interrupt Comparison match interrupt Overflow interrupt Underflow interrupt Zero index interrupt QPCCR: QPRC Position Counter Compare Register Operation example of QPRC Maximum Position Register (QMPR) interrupt The QPRC Maximum Position Register (QMPR) value is used as the reload data to the position counter when an overflow or underflow of position counter is detected. When the position counter value matches the QPRC Maximum Position Register (QMPR) value, the operation of the revolution counter depends on the selected mode as follows: When the position counter is counted up in RC_Mode0 (QCR:RCM[1:0]=00), RC_Mode2 (QCR:RCM[1:0]=10) or RC_Mode3 (QCR:RCM[1:0]=11), the overflow flag (QICR:OFDF) is set to 1 and the position counter is reset. When the position counter is counted up in RC_Mode1 (QCR:RCM[1:0]=01), the overflow flag (QICR:OFDF) is set to 1. During this time, th e position counter is not reset but is counted up. The following gives an operation ex ample where the QPRC Maximum Position Register (QMPR) is used in RC_Mode2 (QCR:RCM[1:0]=10). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 661 MB9Axxx/MB9Bxxx Series
3. Operations During counting up When the position counter maximum value overflows to 0x0000, the revolution counter is counted up. During this time, the overflow flag (QICRL:OFDF) is set to logical 1. Example: If the QPRC Maximum Position Register (QMPR) is set to 18 Position counter 15 16 17 18 0 1 2 Revolution counter 1 1 1 1 2 2 2 During counting down When an underflow is detected with 0x0000 and when the value of Quad Counter Maximum Position Counter Register (QMPR) is reloaded to the positio n counter, the revolution counter is counted down. During this time, the underflow flag (QICRL:UFDF) is set to logical 1. Example: If the QPRC Maximum Position Register (QMPR) is set to 5 Position counter 4 3 2 1 0 5 4 3 2 1 0 5 Revolution counter 1 1 1 1 1 0 0 0 0 0 0 0xFFFF The count i ng direction of position counter depends on the AIN and BIN external input signals only. Position counter reset mask function The position counter reset mask function can be used only when RC_Mode0 (QCR:RCM[1:0]=00) or RC_Mode3 (QCR:RCM[1:0]=11) is selected. This functi on operates regardless of setting of the position counter mode (PC_Mode1, PC_Mode2 or PC_Mode3). The position counter reset mask function is executed in the following sequence. 1. If an active event of ZIN signal, an overflow of position counter, or an underflow of position counter are detected, a value being set by the position counter re set mask bits (QCR:PCRM[1:0]) is set to the mask counter (*1). 2. When the position counter is counted up or down in the same counting direction, the mask counter (*1) is counted down. The position counter is reset only when the mask counter (*1) is set to 0x0. Also, the revolution counter is not counted up or down. When a count inversion of the position counter is detected, the mask counter (*1) is set to 0x0. 3. If the mask counter (*1) is set to 0x0, the position counter is set to 0x0000 when an active edge of ZIN signal or an overflow of position counter is detected. *1 : The number of times to mask both the rese t of position counter and the counting up/down of revolution counter is counted. The masking con tinues until this counter value reaches 0x0. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 662 MB9Axxx/MB9Bxxx Series
3. Operations The following gives an operation example where the position counter reset mask function is used in RC_Mode3 (QCR:RCM[1:0]=11). Example 1: An active edge of ZIN signal is ignored for four (4) counts of position counter after occurrence of position counter overflow. Figure 3-10 Position counter reset mask operation example 1 (QMPR=99, QCR:PCRM[1:0]=10, QCR:CGSC=0) QPCR97 98 9902 1345201 3467 5 ZIN 1 QRCR3 2 At an active edge of ZIN signal, - QPCR is reset. - QRCR is incremented. The reset events are ignored for 4 counts after PC overflow. Example 2: An active edge of ZIN signal is ignored for four (4 ) counts of position counter after count inversion of position counter. Figure 3-11 Position counter reset mask operation example 2 (QMPR=99, QCR:PCRM[1:0]=10, QCR:CGSC=0) QPCR97 98 9902 11099 9698 97 95 9492 91 93 ZIN 1 QRCR1 2 The reset events are ignored for 4 counts after PC underflow. The reset events are ignored after PC overflow. The Mask function is canceled as PC counting was inverted. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 663 MB9Axxx/MB9Bxxx Series
3. Operations The following gives an operation example where the position counter reset mask function is used in RC_Mode0 (QCR:RCM[1:0]=00). Example 3: An active edge of ZIN signal is ignored for four (4) counts of position counter after occurrence of position counter overflow if the revolution counter is disabled. Figure 3-12 Position counter reset mask operation example 3 (QMPR=99, QCR:PCRM[1:0]=10, QCR:CGSC=0) QPCR97 98 9902 1345201 3467 5 ZIN 0 QRCR At an active edge of ZIN signal, the QPCR is reset. The reset events are ignored for 4 counts after PC overflow. While the p o sition counter reset mask function is operating, the mask function is released and the position cou n ter can be reset in the following conditions. When the position counter mode bit (QCR:PCM[1:0]) is changed When the revolution counter mode bit (QCR:RCM[1:0]) is changed When the direction of the position counter is changed Even if an overflow or underflow of the position counter occurs without inversion of the position counter while the position counter reset mask function is operating in RC_Mode0 (QCR:RCM[1:0]=00) or RC_Mode3 (QCR:RCM[1:0]=11), the revolution counter is not counted up or down. However, if an overflow occurs, the position counter becomes 0. If an underflow occurs, the QMPR is reloaded to the position counter. The overflow interrupt request flag bit (QICR:OFDF) or the underflow interrupt request flag bit (QICR:UFDF) is set to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 664 MB9Axxx/MB9Bxxx Series