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5. Register 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Dual Timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  22  
5.7.  Background Load Register (TimerXBGLoad)   
X=1 or 2 
Background Load Register (TimerXBGLoad) is a  32-bit register having a value which the 
counter starts to decrement.   
 
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXBGLoad[31:16] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field TimerXBGLoad[15:0] 
Attribute  R/W R/W R/W  R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:0] TimerXBGLoad : Background Load bit  This register is used to reload the counter when th e current count reaches zero in Periodic Mode setting. 
This is not used in Free-running Mode or One-shot Mode. 
Writing to this register reloads the counter differently  from the writing to the Load Register (TimerXLoad). 
The difference is as follows. Writing to the Load Regi ster immediately starts the counter with the new 
value; however, writing to this register does not i mmediately restart the counter with the new value. 
After a value is written to either of the Load Register  or the Background Register, the register value written 
last is returned at any reading. In other words, the same value is read from the Load Register and the 
Background register, and the value is always reloaded  after the counter reaches zero in Periodic Mode. 
CHAPTER  12: Dual  Timer 
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CHAPTER: Watch Counter Prescaler 
This chapter explains the functions and operations of the watch counter prescaler. 
 1.
 Overview of the Watch Counter Prescaler 
2. Configuration of the Watch Counter Prescaler 
3. Explanation of Operations an d Setting Procedure Examples of  the Watch Counter Prescaler 
4. Registers of the Watch Counter Prescaler 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFWCPRE-E01.1 
CHAPTER  13-1: Watch  Counter  Prescaler 
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1.  Overview of the Watch Counter Prescaler 
The watch counter prescaler is a prescaler which generates a counter clock used for a watch 
counter. 
 Watch Counter Prescaler 
This is a prescaler which generates  a count clock of the watch counter. 
The watch counter prescaler can select a main  clock or a sub clock as an input clock (F
CL). The watch 
counter prescaler outputs the division clocks (WCCK0 to 3) shown in  Table 1-1 by setting SEL_OUT bit of 
the clock sel e

ction register (CLK_SEL). 
Table 1-1 Division clocks generated by the watch counter prescaler 
SEL_OUT WCCK3 WCCK2 WCCK1 WCCK0 
0 215/FCL 214/FCL 213/FCL 212/FCL 
1 225/FCL 224/FCL 223/FCL 222/FCL 
SEL_OUT  :  Output clock selection bit of clock selection register (CLK_SEL) 
FCL  :  Frequency of input clock   
CHAPTER  13-1: Watch  Counter  Prescaler 
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2.  Configuration of the Watch Counter Prescaler 
This section shows the block diagram of the watch counter prescaler. 
 Block diagram of the  watch counter prescaler 
Figure 2-1 shows the block diagram of the watch counter prescaler. 
Figure 2-1 Block diagram of the watch counter prescaler 
 
Internal bus 
Division counter 
(down counter) 
FCL : Frequency of input clock  SEL_IN 
CLK_EN Count enabled
SEL_OUT 
Main clock 
Sub clock 
FCL  WCCK0 
WCCK1 
WCCK2 
WCCK3 
Input 
clock select Division 
clock setting 
Clock selection register (CLK_SEL upper byte) 
Clock selection register (CLK_SEL lower byte) Division clock enable register (CLK_EN)  Division clock 
(to watch counter) 
CLK_EN_R 
 

 Clock selection register (CLK_SEL) 
This register selects the input clock (FCL) which inputs the division counter, and sets the division clocks 
(WCCK0 to 3) that output. 
  Division clock enable register (CLK_EN) 
This register enables counting down of the division counter. 
There is a delay for 2 cycles of the clock selected by  SEL_IN bit of the clock selection register (CLK_SEL) 
during a period of time from a value is written to this  register until the division counter starts to operate. 
 Division counter 
This is a down counter which generates the division clocks (WCCK0 to 3) of the input clock (FCL). 
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3.  Explanation of Operations and Setting Procedure Examples of the Watch Counter Prescaler 
This section explains the operations of the watch counter prescaler. Also, procedures for 
setting the operating state are shown. 
 Procedures for setting the watch counter prescaler 
The procedures for setting the watch  counter prescaler are shown below. 
 To start output of the division clock 
1.  Select the input clock (FCL) of the division counter with SEL_IN bit of the clock selection register 
(CLK_SEL). Also, set the division clock that outputs with SEL_OUT bit of the clock selection register 
(CLK_SEL). 
At this time, the division clock to be output is fixed to L since the division counter is not operated. 
2.  Set 1 to CLK_EN bit of the division clock enable register (CLK_EN) to enable output of the division 
clock. 
 To stop output of the division clock 
1.  Set 1 to CLK_EN bit of the division clock enable register (CLK_EN) to disable output of the division 
clock. 
 To restart after stopping out put of the division clock 
1. Set 1 to CLK_EN bit of the division clock enable register (CLK_EN) to enable output of the division 
clock. 
2.  Write 0 to WCEN bit of the watch counter contro l register (WCCR) of the watch counter, and clear 
the value of the 6-bit down counter in the watch counter to 0b000000. 
3.  Write 0 to WCEN bit of the watch counter control  register (WCCR) of the watch counter to restart the 
operation of the watch counter. 
  To switch while the di vision clock is operating 
1. Set 0 to CLK_EN bit of the division clock enable register (CLK_EN) to disable output of the division 
clock. 
2.  Read CLK_EN_R bit of the division clock enable register (CLK_EN), and confirm whether output of 
the division clock is stopped (CLK_EN_R=0). 
3.  Select the input clock (F
CL) of the division counter by SEL_IN bit of the clock selection register 
(CLK_SEL). Also, set the division clock to be output with SEL_OUT bit of the clock selection register 
(CLK_SEL). 
4.  Set 1 to CLK_EN bit of the division clock enable register (CLK_EN) to enable output of the division 
clock. 
 
   The peri
pheral cl

ock (PCLK) is used to set each regi ster of the watc
h co
unter prescaler
 . The input clock 
(FCL) of the division clock and the peripheral clock (PCLK) are not synchronized. Since the input clock 
(FCL) of the division counter and peripheral clock (PCLK) are not synchronized, a delay for 3 clocks of 
the input clock (FCL) is occurred to WCCK0 to 3 after a value is set to each register. 
   Regarding 2. of  To switch while the division clock is operating , a glitch may be occurred while the 
di vision
 cl

ock is operating. Confirm whether output of the division counter is stopped. 
   The watch counter uses output of the watch counter prescaler as a count clock. Therefore, the settings of 
the watch counter prescaler should not be changed while the watch counter is operating. 
 
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 Operation of the watch counter prescaler 
Figure 3-1  shows an operation of the watc h counter prescaler when SEL_ OUT is set to 0 as an example. 
Figure 3-1 Operation explanation diagram of the watch counter prescaler 
 
CLK_EN bit
Input clock F
CL 
Division counter
WCCK0
WCCK2
WCCK3
WCCK1
Peripheral clock
 (PCLK)
0 0x1FF FFFF 
(1) 
(2)
(3)0x1FF FFFE  0x1FF 
DFFE 0x1FF F7FE0x1FFEFFE0x1FF BFFE 0x1FF
7FFE
  
 
(1) Set CLK_EN bit at rising of the peripheral clock (PCLK). 
(2) The division counter is operated synchronizing with the input clock (F
CL). 
(3) The clocks are output to WCCK0 to 3 from the  counter according to the settings of SEL_OUT bit. 
 
 
The periphe ral

 clock (PCLK) is used for the settings of each register of the watch counter prescaler. Since 
the input  cl

ock (F
CL) of the division counter and peripheral clock (PCLK) are not synchronized, a delay for 
4 clocks of the input clock (F
CL) is occurred to WCCK0 to 3 after  a value is set to each register. 
 
 Relationship between the frequency of the input clock (FCL) and the cycle of 
the division clock 
Ta b l e  3 - 1  shows the setting example of the frequency of the input clock (FCL) and the cycle of the division 
clock. 
Table 3-1 Setting example of the watch counter prescaler 
Cycle of division clock 
SEL_IN SEL_OUT Input clock 
frequency  (F
CL)  WCCK3WCCK2WCCK1 WCCK0
0 (sub clock) 
0 32.768 kHz  1s 500 ms  250 ms 125 ms 
1 (main clock)  1 33.554 MHz  1s 500 ms  250 ms 125 ms 
 
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4.  Registers of the Watch Counter Prescaler 
This section explains the registers for the watch counter prescaler. 
 List of registers for th e watch counter prescaler 
Table 4-1 List of registers for the watch counter prescaler 
Abbreviated 
Register Name  Register Name Reference 
CLK_SEL Clock selection register 
4.1 
CLK_EN Division clock enable register  4.2 
 
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4.1.  Clock Selection Register (CLK_SEL) 
The clock selection register (CLK_SEL) selects the input clock (FCL) and sets the division 
clocks (WCCK0 to 3) to be output. 
 bit 15 to 11 10 9 8 
Field res res SEL_OUT
Attribute R/W  R/W R/W 
Initial value  0b00000  0b00 0 
  bit 7  to 1 0 
Field res  SEL_IN
Attribute R/W  R/W 
Initial value 0b0000000  0 
 
[bit15:11, bit7:1] res : Reserved bits  0 is always read. 
Writing is ignored. 
 
[bit10: 9] res : Reserved bits  Always write 0 to these bits. 
 
[bit8] SEL_OUT : Output clock selection bit  This bit selects the division clocks (WCCK0 to 3) to be output from the division counter. 
Explanation 
bit 
WCCK3 WCCK2  WCCK1 WCCK0 
0 215/FCL 214/FCL 213/FCL 212/FCL 
1 225/FCL 224/FCL 223/FCL 222/FCL 
 
[bit0] SEL_IN : Input clock selection bit  This bit selects the input clock (F
CL) to be used. 
bit Explanation 
0  Generates a division clock using the sub clock. 
1 Generates a division clock using the main clock. 
 
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4. Registers of the Watch Counter Prescaler 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Watch Counter Prescaler 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  9 
4.2.  Division Clock Enable Register (CLK_EN) 
The division clock enable register (CLK_EN) is a register to enable a count down of the 
division counter. 
  bit 7 to 2 1 0 
Field res CLK_EN_R CLK_EN
Attribute R/W  R/W R/W 
Initial value  0b000000  0 0 
 
[bit7:2] res : Reserved bits  0 is always read. 
Writing is ignored. 
 
[bit1] CLK_EN_R : Division clock enable read bit  This bit can read the value of CLK_EN used for controlling the division. Writing to this bit does not affect 
the operations and the reading value. 
bit Explanation 
0  The counter for the clock division stops counting, and oscillation of the division 
clock is not performed. 
1 The counter for the clock division starts counting, and oscillation of the division 
clock is not performed. 
 
[bit0] CLK_EN : Division clock enable bit  There is a delay for 2 cycles in the clock selected  by CLK_SEL register during a period of time from a 
value is written to CLK_EN bit until the value is reflected. 
bit Explanation 
0  The division counter stops counting, and disables oscillation of the division clock.
Clears the value of the division counter to 0. 
1 
The division counter starts counting, and enables oscillation of the division clock.
 
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