Fujitsu Series 3 Manual
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![Page 96
FUJITSU SEMICONDUCTOR LIMITED
5.1. High-speed CR oscillation Frequency Division Setup Register (MCR_PSR)
The MCR_PSR sets the frequency division ratio of high-speed CR oscillation.
A divided clock can be input into input capture.
Register configuration
bit 7 6 5 4 3 2 1 0
Field Reserved CSR
Initial value - 2b01
Attribute - R/W
Register functions
[bit 7:2] : Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1:0] CSR: High-speed CR oscillati...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-95.png "Page 96
FUJITSU SEMICONDUCTOR LIMITED
5.1. High-speed CR oscillation Frequency Division Setup Register (MCR_PSR)
The MCR_PSR sets the frequency division ratio of high-speed CR oscillation.
A divided clock can be input into input capture.
Register configuration
bit 7 6 5 4 3 2 1 0
Field Reserved CSR
Initial value - 2b01
Attribute - R/W
Register functions
[bit 7:2] : Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1:0] CSR: High-speed CR oscillati...")
![Page 97
FUJITSU SEMICONDUCTOR LIMITED
5.2. High-speed CR oscillation Frequency Trimming Register (MCR_FTRM)
The MCR_FTRM sets the frequency trimming value.
This section explains register configuration and register functions.
Register configuration
bit 31 16
Field Reserved
Initial value -
Attribute -
bit 15 109 8 7 6 5 4 3 2 1 0
Field Reserved TRD[9:0]
Initial value - 10b0110000000
Attribute - R/W
Register functions
[bit 31:10] : Reserved bits
0 is always read...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-96.png "Page 97
FUJITSU SEMICONDUCTOR LIMITED
5.2. High-speed CR oscillation Frequency Trimming Register (MCR_FTRM)
The MCR_FTRM sets the frequency trimming value.
This section explains register configuration and register functions.
Register configuration
bit 31 16
Field Reserved
Initial value -
Attribute -
bit 15 109 8 7 6 5 4 3 2 1 0
Field Reserved TRD[9:0]
Initial value - 10b0110000000
Attribute - R/W
Register functions
[bit 31:10] : Reserved bits
0 is always read...")
![Page 98
FUJITSU SEMICONDUCTOR LIMITED
5.3. High-Speed CR Oscillator Register Write-Protect Register (MCR_RLR)
The MCR_RLR controls the write-protect state of the frequency trimming register
(MCR_FTRM).
Register configuration
bit 31 16
Field TRMLCK[31:16]
Initial value 16h0000
Attribute R/W
bit 15 0
Field TRMLCK[15:0]
Initial value 16h0001
Attribute R/W
Register functions
[bit 31:0] TRMLCK: Register write-protect bits
Bit 31:0 Description
When read When 0x00000000...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-97.png "Page 98
FUJITSU SEMICONDUCTOR LIMITED
5.3. High-Speed CR Oscillator Register Write-Protect Register (MCR_RLR)
The MCR_RLR controls the write-protect state of the frequency trimming register
(MCR_FTRM).
Register configuration
bit 31 16
Field TRMLCK[31:16]
Initial value 16h0000
Attribute R/W
bit 15 0
Field TRMLCK[15:0]
Initial value 16h0001
Attribute R/W
Register functions
[bit 31:0] TRMLCK: Register write-protect bits
Bit 31:0 Description
When read When 0x00000000...")
1. Overview Chapter: Resets This chapter explains the function and operation of the resets. 1. Overview 2. Configuration 3. Explanation of Operations 4. Registers CODE: 9BFRESET-E01.2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 65 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview This product has the following reset causes and issues a reset to initialize a device upon accepting a reset cause. Power-on reset INITX pin input External power supply/low-voltage detection reset Software watchdog reset Hardware watchdog reset Clock failure detection reset Anomalous frequency detection reset Software reset TRSTX pin input FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 66 MB9Axxx/MB9Bxxx Series
2. Configuration 2. Configuration Block Diagram of Resets SW-WDG HW-WDG CSV INITX LVDH PONR TRSTX PORESETn SYSRESETn nTRST SQ-WDG reset HW-WDG reset Clock failure detection reset Anomalous frequency detection reset HRESET SYSRESETREQ SYSRESETREQ SYSRESETn PRESET0 PRESET1 PRESET2 Reg Reg PONR : Power-on reset INITX : INITX pin input reset LVDH : Low-voltage detection reset TRSTX : TRSTX pin input reset HRESET : AHB bus reset (a bus reset issued by all reset causes) PRESET0, 1, 2 : APB0, APB1, APB2 bus resets (bus resets issued by all reset causes) SW-WDG reset : Software watchdog reset HW-WDG reset : Hardware watchdog reset PORESETn : Power-on reset that is input to Cortex-M3 SYSRESETn : System reset that is input to Cortex-M3 SYSRESETREQ : SYSRESETREQ bit signal of Cortex-M3 internal reset control register nTRST : SWJ-DP reset FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 67 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3. Explanation of Operations This section explains the operations of the resets. 3.1 Reset Causes 3.2 Resetting Inside the Device 3.3 Reset Sequence 3.4 Operations After Resets are Cleared FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 68 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.1. Reset Causes This section explains reset causes. Power-On Reset (PONR) A reset that is generated at power-up. Generated by This signal is generated by de tecting a rising edge of the power supply. Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware. Flag Bit 0 (PONR) of reset cause register (RST_STR) = 1 INITX Pin Input Reset (INITX) A reset that is externally input from a device. Generated by This signal is generated by inputting a low level to INITX pin. Cleared by This signal is cleared by inputting a high level to INITX pin. Initialization target Initializes all register settings and hardware except the debug circuit. Note: The reset cause register is not initialized. Flag Bit 1 (INITX) of reset cause register (RST_STR) = 1 * The content of the internal RAM is retained if a reset is asynchronously input from INITX pin. Low-voltage Detection Reset, Extern al Voltage Monitoring (LVDH) A reset that is input from a low-voltage detection circuit when a decrease in the external voltage is detected. Generated by This signal is generated when an external voltage is lowered than a specified level. Cleared by This signal is cleared when an external voltage is more than a specified level. Initialization target Initializes all register settings and hardware. Flag Bit 0 (PONR) of reset cause register (RST_STR) = 1 Software Watchdog Reset (SWDGR) A reset that is input from the software watchdog timer. Generated by This signal is generated when the software watchdog timer underflows. Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware except the debug circuit and hardware watchdog timer (including control registers). Note: The reset cause register is not initialized. Flag Bit 4 (SWDT) of reset cause register (RST_STR) = 1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 69 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations Hardware Watchdog Reset (HWDGR) A reset that is input from the hardware watchdog timer. Generated by This signal is generated when the hardware watchdog timer underflows. Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware except the debug circuit. Note: The reset cause register is not initialized. Flag Bit 5 (HWDT) of reset cause register (RST_STR) = 1 Clock Failure Detection Reset (CSVR) A reset that is input when the main or sub crystal oscillator being monitored fails. Generated by This signal is generated when a clock failure is detected in the main or sub crystal oscillator. Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware except the debug circuit and clock failure detection circuit(some registers). Note: The reset cause register is not initialized. Flag Bit 6 (CSVR) of reset cause register (RST_STR) = 1 Bit 1 (SCMF) or bit 0 (MCMF) of CSV status register (CSV_STR) = 1 Note: For details on the CSV_STR, see Chapter Clock Failure Detection. Anomalous Frequency Detection Reset (FCSR) A reset that is input when an anomalous frequenc y is detected in the main crystal oscillator. Generated by This signal is generated when the frequency of the main crystal oscillator is outside of any given setting. Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware except the debug circuit and the anomalous frequency detection(some registers). Note: The reset cause register is not initialized. Flag Bit 7 (FCSR) of reset cause register (RST_STR) = 1 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 70 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations Software Reset (SRST) A reset that is generated when an access to the reset control register occurs. Generated by This signal is generated by a write to the reset control register (SYSRESETREQ bit). Cleared by This signal is automatically cleared after issuing a reset. Initialization target Initializes all register settings and hardware except the following: Registers that are not initialized by a software reset Debug circuit All registers related to clock control Part of registers that control software and hardware watchdog timers Part of registers in the clock failure detection circuit Part of registers that detect an anomalous frequency Part of registers for CR trimming Reset cause register Flag Bit 8 (SRST) of reset cause register (RST_STR) = 1 For reset control re gister (SYSRESETREQ) that contro ls the soft ware reset, see Chapter 3, System Control, in Cortex-M3 Technical Reference Manual. The reset cause register that can determine the o ccurrence of each reset cause is initialized only by power-on reset. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 71 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2. Resetting Inside the Device This section explains the internal reset signals of this device. Resets that are internally connected to the device are divided into resets that are input to the Cortex-M3 core and resets that are input to peripheral circuits. 3.2.1 Resets to Cortex-M3 3.2.2 Resets to Peripheral Circuit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 72 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.1. Resets to Cortex-M3 The device has three reset inputs to the Cortex-M3: PORESETn, SYSRESETn, and nTRST. The following provides reset causes for these three reset inputs. Power-on reset PORESETn Reset Causes Power-on reset (PONR) Low-voltage detection reset (LVDH) System reset SYSRESETn Reset Causes Power-on reset (PONR) Low-voltage detection reset (LVDH) INITX pin input (INITX) Software watchdog reset (SWDGR) Hardware watchdog reset (HWDGR) Clock Failure Detection reset (CSVR) Anomalous frequency detection reset (FCSR) Software reset (SRST) SWJ-DP Reset nTRST Reset Causes Power-on reset (PONR) Low-voltage detection reset (LVDH) TRSTX pin input (TRSTX) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 73 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.2. Resets to Peripheral Circuit The bus resets (HRESET, PRESET0, PRESET1, and PRESET2) that are input to the peripheral circuit are basically generated by all reset causes. Resetting of PRESET1 and PRESET2 can be controlled by register settings. The following provides reset causes for the bus resets. Resets to Peripheral Circuit HRESET and PRESET0 Reset Causes Power-on reset (PONR) Low-voltage detection reset (LVDH) INITX pin input (INITX) Software watchdog reset (SWDGR) Hardware watchdog reset (HWDGR) Clock Failure Detection reset (CSVR) Anomalous frequency detection reset (FCSR) Software reset (SRST) PRESET1 and PRESET2 Reset Causes Power-on reset (PONR) Low-voltage detection reset (LVDH) INITX pin input (INITX) Software watchdog reset (SWDGR) Hardware watchdog reset (HWDGR) Clock Failure Detection reset (CSVR) Anomalous frequency detection reset (FCSR) Software reset (SRST) APB bus resets (APBC1_PSR and APBC2_PSR) The p eripheral circuit is essentially initialized with a ll reset causes. Depe nding on the specifications of the peripheral circuit, there are registers that are initialized only with specific causes. For the initialization conditions for registers, see the initialization conditions for the registers described in the relevant chapter. For details on APB bus resets (APBC1_PSR and APBC2_PSR), see Chapter Clocks. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 3: Resets MN706-00002-1v0-E 74 MB9Axxx/MB9Bxxx Series