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Fujitsu Series 3 Manual

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5. Registers 
 
5.15.  Comparison Time Setup Register (ADCT) 
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the 
A/D conversion time. 
 bit 7 6 5 4 3 2 1 0 
Field Reserved CT2 CT1 CT0 
Attribute  - - -  - - R/W R/W R/W 
Initial value  X X X  X X 1 1 1 
 
[bit 7:3] Reserved: Reserved bits  When writing, always write 0. Wh en reading, 0 is always read. 
 
[bit 2:0] CT2:CT0: Compare clock  frequency division ratio setting bits 
These bits set the division ratio of the HCLK fo r generating the compare clock of A/D conversion. 
The frequency division ratio setting is common to Sampling Setup Registers 0 and 1. 
Bit 2  Bit 1 Bit 0  Description 
0 0 0 Frequency division ratio 2 
0  0 1 Frequency division ratio 3 
0  1 0 Frequency division ratio 4 
0  1 1 Frequency division ratio 5 
1  0 0 Frequency division ratio 6 
1  0 1 Frequency division ratio 7 
1  1 0 Frequency division ratio 8 
1  1 1 Frequency division ratio 9 
 
Frequency division ratio = CT set value + 2 
Compare clock cycle = Base clock (HCL K) cycle × Frequency division ratio 
Comparison time = Compare clock cycle × 14 
Example:  When the CT set value = 3 and HCLK = 80 MHz (12.5 ns),    Frequency division ratio = 3 + 2 = 5 
Compare clock cycle = 12 .5 ns × 5 = 62.5 ns 
Comparison time = 62.5 ns × 14 = 875 ns 
 
It is not  p

ossible to write to the ADCT register during  the period of 
 operation enable state transitions and 
A/D conversion. 
For setting the compare clock cycle, refer to the Electri cal Characteristics in the data sheet to make sure 
that an appropriate time should be selected in accordance with an analog power supply voltage (AVCC) and 
a base clock (HCLK) cycle. 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
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5. Registers 
 
5.16.  A/D Operation Enable Setup Register (ADCEN) 
The A/D Operation Enable Setup Register (ADCEN) is used to turn the 12-bit A/D converter to 
the operation enable state. 
 bit 7 6 5 4 3 2 1 0 
Field Reserved READY ENBL 
Attribute  - - -  - - - R R/W 
Initial value  X X X  X X X  0 0 
 
[bit 7:2] Reserved: Reserved bits  When writing, always write 0. Wh en reading, 0 is always read. 
 
[bit1] READY : A/D operation enable state bit  This bit indicates whether the A/D converter is in the operation enable state or not. 
A/D conversion can be performed only in the operation enable state. 
An A/D conversion request in the operation stop state is ignored. 
If the A/D converter enters the operation stop st ate during A/D conversion, A/D conversion stops 
immediately.  
Bit Description 
0  Operation stop state 
1 Operation enable state 
 
[bit0] ENBL : A/D operation enable bit  This bit enables the operation of the A/D converter. 
Writing 1 to the ENBL bit turns the A/D converter to the operation enable state after the period of 
operation enable state transitions. On the other hand, writing 0 to this bit turns the A/D converter to the 
operation stop state. 
Bit Description 
0 Stops operation 
1 Enables operation 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-3: 12-bit  A/D Converter 
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5. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: 12-bit A/D Converter 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  52 
The cycle number of the base clock (HCLK) necessary as  the period of operation enable state transitions 
depends on the CT[2:0] set value of the ADCT register . The cycle number for the set value is as follows: 
ADCT.CT[2:0] Description 
0b000 72 cycles 
0b001 108 cycles 
0b010 144 cycles 
0b011 180 cycles 
0b100 216 cycles 
0b101 252 cycles 
0b110 288 cycles 
0b111 324 cycles 
 
Period of operation enable state transitions = Base clock (HCLK) cycle   cycle number 
例)  When the CT set value = 3 and HCLK = 80 MHz (12.5 ns),    Period of operation enable state transitions = 12.5 × 180 = 2250 ns 
 
 
It is not possible to write to the ADCT register during  the period of operation enable state transitions and 
A/D conversion. 
Set the ADCEN after setting the ADCT. Set the ADCT so that it may satisfy the period of operation enable 
state transitions of Electrical Characteristics in the data sheet. 
When setting the CPU to the timer mode or the stop mode, set the ENBL bit to 0 and turn the A/D 
converter to the operation stop state. 
 
 
CHAPTER  18-3: 12-bit  A/D Converter 
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1. Overview 
 
Chapter: A/D Timer Trigger Selection 
This chapter explains the functions and operations to select a timer trigger of the A/D 
converter. 
 
1.
 Overview 
2. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFBATSB-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
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1. Overview 
 
1. Overview 
This section explains the operations to select a timer trigger of the A/D converter. 
 Selecting a timer trigger of the A/D converter 
The 10-bit A/D converter and th e 12-bit A/D converter are started by the factors shown in Ta b l e  1 - 1 . 
Table 1-1 A/D converter start factor 
Conversion type Start factor 
Priority level 1 conversion    Input from an external trigger pin (at falling edge) 
Priority level 2 conversion  
  Software (when the PCCR:PSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
Scan conversion  
  Software (when the SCCR:SSTR bit is set to 1) 
   Trigger input from timer (at rising edge) 
 
The A/D converter can be started with two types of timers: base timer and multifunction timer. 
A timer start factor can be selected using the Scan C onversion Timer Trigger Selection Register (SCTSL) or 
Priority Conversion Timer Trigger Selection Register  (PRTSL). The A/D converter starts A/D conversion if 
a rising edge of the selected timer is detected while timer starting is enabled. 
For details on the operations of the 10-bit A/D converter, see the explanation of operations in the 10-bit 
A/D Converter. 
For details on the operations of the 12-bit A/D converter, see the explanation of operations in the 12-bit 
A/D Converter. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
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2. Registers 
 
2. Registers 
This section explains the configuration and functions of the registers used to select an A/D 
timer trigger. 
 List of timer trigger selecti on registers for A/D converter 
Abbreviation Register  name See 
SCTSL Scan Conversion Timer Trigger Selection Register  2.1 
PRTSL Priority Conversion Timer Trigger Selection Register  2.2 
 
The functions of the timer trigger selection register s for the A/D converter are common to the 10-bit A/D 
converter and the 12-bit A/D converter. For the othe r registers of the A/D converter, see 10-bit A/D 
Converter and 12-bit A/D Converter. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
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2. Registers 
 
2.1.  Scan Conversion Timer Trigger Selection Register (SCTSL) 
The Scan Conversion Timer Trigger Selection Register (SCTSL) is used to select a timer 
trigger when performing scan conversion. 
 
bit 15 14 13 12 11 10 9 8 
Field Reserved SCTSL[3:0] 
Attribute  R R R  R R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 15:12] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 11:8] SCTSL: Scan conversion timer trigger selection bit 
Bit [11:8]  Description 
0b0000 No selected trigger (Input is fixed to 0.) 
0b0001  Starts scan conversion with the multifunction timer. 
0b0010 Base timer ch.0 
0b0011 Base timer ch.1 
0b0100  Base timer ch.2 
0b0101 Base timer ch.3 
0b0110 Base timer ch.4 
0b0111 Base timer ch.5 
0b1000  Base timer ch.6 
0b1001 Base timer ch.7 
0b1010 
to 0b1111  Setting disabled 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
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2. Registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: A/D Timer Trigger  Selection 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  6 
2.2.  Priority Conversion Timer Trigger Selection Register  (PRTSL) 
The Priority Conversion Timer Trigger Selection Register (PRTSL) is used to select a timer 
trigger when performing priority conversion. 
 
bit 7 6 5 4 3 2 1 0 
Field Reserved PRTSL[3:0] 
Attribute  R R R  R R/W  R/W  R/W R/W 
Initial value  X X X  X 0 0  0 0 
 
[bit 7:4] Reserved: Reserved bits 
Write Has no effect on operation. 
Read The value is undefined. 
 
[bit 3:0] PRTSL: Priority conv ersion timer trigger selection bit 
Bit [3:0]  Description 
0b0000 No selected trigger (Input is fixed to 0.) 
0b0001  Starts priority conversion with the multifunction timer. 
0b0010 Base timer ch.0 
0b0011 Base timer ch.1 
0b0100  Base timer ch.2 
0b0101 Base timer ch.3 
0b0110 Base timer ch.4 
0b0111 Base timer ch.5 
0b1000  Base timer ch.6 
0b1001 Base timer ch.7 
0b1010 
to 0b1111  Setting disabled 
 
CHAPTER  18-4: A/D Timer  Trigger  Selection 
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 FUJITSU SEMICONDUCTOR LIMITED 
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