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3. CRC Registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
Chapter: CRC (Cyclic Redundancy Check) 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  16 
3.4. CRC Register (CRCR) 
The CRC Register (CRCR) is used to output the  CRC calculation result. This register must be 
initialized before start calculating. 
 
bit 31       0 
Field D31-D0 
Attribute R 
Initial value  0xFFFFFFFF 
 
[bit 31:0] D31 to D0: CRC bit  This bit is used to read the CRC calculation result.  If 1 is written to the initialization bit (CRCCR.INIT), 
the value of the Initial Value Register (CRCINIT)) is loaded to this register. 
If input data for CRC calculation is written to the Input Data Register (CRCIN), the CRC calculation result 
is set to this register after one machine clock cycle has elapsed. When all input data writing has been 
completed, this register holds the final CRC code. 
In CRC16 mode, when the byte order is set to big endian (CRCLTE=0), the result is output to D15 to D0. 
When the byte order is set to little endian (CRCLTE=1), the result is output to D31 to D16. 
 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
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1. External Bus Interface Features 
 
Chapter: External Bus Interface 
This chapter explains the functions and operations of the external bus interface. 
 
1.
 External Bus Interface Features 
2. Block Diagram 
3. Operation 
4. Example waveforms of external memory access 
5. Endianness and Valid Byte Lanes 
6. Connection Examples 
7. Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFEXTBUS-E01.1_MEMCS-E1.5 
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1. External Bus Interface Features 
 
1.  External Bus Interface Features 
This section explains features of the external bus interface. 
 External bus interface features 
  Supports 8-bit/16-bit wide SRAM/flash memories. 
   Provides eight chip select ar eas for an SRAM/flash memory. 
   Can configure parameters individually for each chip select area for an SRAM/flash memory. 
   Can access the device during NAND flash memory access.  (Exclusive access control is not required.) 
   Supports NOR flash memory page access. 
   Supports little endian. 
 
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2. Block Diagram 
 
2. Block Diagram 
This section explains the block diagram of the external bus interface. 
Figure 2-1 External bus interface block diagram 
 
This LSI
Control block
External bus interface
AHB interface
Register block
AHB bus
APB bus
External memory bus
I/O
  
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3. Operation 
 
3. Operation 
The section explains the operations of the external bus interface. 
The external bus interface can connect with SRAM and flash memories. 
The external bus interface has eight chip select signals. 
 
3.1 Fundamental SRAM and  flash memo
ry accesses 
3.

2   NAND flash memory access 
 
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3. Operation 
 
3.1.  Fundamental SRAM and flash memory accesses 
The following explains fundamental SRAM and flash memory accesses. 
The external bus interface has a 256 MB address space. Each address can be configured without restrictions. 
(The actual maximum address size is 32 MB if the external output address width is taken into 
consideration.) 
A different timing can be specified for each chip se lect signal. NAND and NOR flash memories can be 
connected. The NOR flash memory can be accessed as is the case with usual access to SRAM. 
A dedicated pin is assigned to a NAND flash memory.  With this, an access to the device sharing a data pin 
with a NAND flash memory is enabled. (See  3.2 NAND flash memory access.) 
In SRAM a ccesses, MCSX0-7 is select
ed within a single access. 

If an access uses a bid width larger than 
the target bit width, the access is converted into a serial access in which  only the address is changed while 
MCSX stays LOW. For example, when an 8-bit wide  device receives 16-bit read access from an internal 
bus, the address is changed from 0 to 1 while MCSX stays LOW, and the data is output serially from 
MDATA[7:0] with transition timing. (See waveforms of  access example.) The data matched to endian is 
output to the internal bus. 
When an access is performed with a width smaller than  the target bit width (for example, a byte access to a 
16-bit wide internal bus), the byte access is controlle d by the MDQM signal (byte mask) during the write 
operation. (The SRAM/flash memory controller only outputs required data.) 
For a device without an input mask, the MDQM signal is used as a write enable. 
If the target device has a mask signal, the MDQM control can be used to make the device only output 
required data. Those processes help reduce power consumption during access. 
 
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3. Operation 
 
3.2.  NAND flash memory access 
The following explains NAND flash memory access. 
An access to a NAND flash memory requires different processes from usual SRAM accesses. 
A NAND flash memory has a (512+16) byte internal  register (an 8-bit/16-bit NAND flash memory has a 
(1024+32) byte register). 
Those registers are used to set the basic  data access. For the read operation, several  s to up to several tens 
of  s is required until data is loaded into the internal  register. For the write operation, several hundred  s 
are required for writing data to memory cells. To erase blocks, several ms are required. 
The chip select signal must st ay LOW when data is being loaded to the internal register. 
Therefore, the read/write signal for the NAND flash memory cannot be controlled. 
The external bus interface that has a separated enable signal can gain access to the NAND flash memory 
while the chip select signal connected to the NAND flas h memory is kept LOW. (This chip select signal can 
be reset to HIGH.) This allows the interface to  access another chip that shares data signals. 
A write access to +0x2000 is  converted into the issue of an address for the NAND flash memory (MNALE 
is asserted). 
A write access to +0x1000 is conver ted into the issue of a command for the NAND flash memory (MNCLE 
is asserted). 
A write/read access to +0x0000 is  converted into a data access to the NAND flash memory (MNALE and 
MNCLE are not asserted) based on the base  address within the area set to NAND mode. 
The setting for access timing is the same as that used  for SRAM access. MNCLE is output at the same 
timing as address output during the access. 
MNALE is in the asserted state until a write access to +0 x3000 after the issue of an address, or any other 
write accesses (data or command) than address issues. This is b ecause NAND flash memory cannot 
de-assert ALE within multiple write accesses for the issue of addresses.  Addresses up to +0x3000 only 
assert MNALE and do not allow an access.  Figure 3-1 shows the process of NAND flash memory access. 
(For  details about the comm

ands, see the specificati on of NAND flash memory connected to this LSI) 
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3. Operation 
 
3.2.1.   Read access to NAND flash memory 
Figure 3-1 shows the flowchart of read access to NAND flash memory. 
Figure 3-1 Flowchart of read access to NAND flash memory. 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
End read access
Turn NAND mode ON 
Single page data read  (Base+0x0000) 
Status read   (Base+0x0000) 
Y 
Sta t us  = O K ?N
Issue a read command 0x00   (Base+0x1000) 
Issue a status read command 0x70   (Base+0x1000)
 Issue an address   (Base+0x2000) 
Issue a read command 0x00 
 (Base+0x 1000) 
 The corresponding chip select signal is fixed to L.
MNCLE is asserted/de-asserted. 

MNALE is ass e
 rted
.

MNALEP is de-asserted.

Access to another device (SRAM) is enabled during this 
period (for several  s). 

 
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3. Operation 
 
3.2.2. Write (auto program) access 
Figure 3-2 shows the flowchart of the write (auto program) access. 
Figure 3-2 Write (auto program) access flowchart 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
Issue a status read command 0x70  (Base+0x1000)
Issue a page program command 0x10   (Base+0x1000)
Status read   (Base+0x0000) 
Y 
Sta t us  O K ? = N
End write (Auto Program) 
  Issue a write command 0x80 
 (Base+0x1000)
Issue an address   (Base+0x2000) 
 
Clear MNALE (optional value)   (Base+0x3000)
Single page data write   (Base+0x0000)
Turn NAND mode ON
 
The corresponding chip select signal is fixed to L.
MNCLE is asserted/de-asserted. 
MNALE is asserted.
MNALEP is de-asserted.
Access to another device (SRAM) is enabled during 
this period (for several hundred  s). 
 
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