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6. LIN Interface (ver. 2.1) Registers 
 
6.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and 
BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. Also, an external clock can be selected as the clock source of 
the reload counter. 
 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field EXT (BGR1) (BGR0) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
   The Baud Rate Generator Registers are used to set a frequency division ra tio of serial clocks. 
   The BGR1 register corresponds to the high-order  bits, and the BGR0 register corresponds to the 
low-order bits. The reload value to be counted can  be written, and the BGR1/0 set value can be read. 
   When the reload value is written in Baud Rate  Generator Registers 1 and 0 (BGR1 and BGR0), the 
reload counter starts its counting. 
   The EXT bit (bit 15) specifies to use the clock source of  reload counter as the internal clock or use an 
external clock. If EXT=0 is set, an internal clock is  used. If EXT=1 is set, an external clock is used. 
 
[bit 15] EXT: External clock select bit 
Bit Description 
0  Uses the internal clock. 
1  Uses an external clock. 
 
[bit 14:8] BGR1: Baud Rate Generator Register 1 
Bit 14:8  Description 
Write Write data in reload counter bit 8 to 14. 
Read  Reads the BGR1 set value. 
 
[bit 7:0] BGR0: Baud Rate Generator Register 0 
Bit 7:0  Description 
Write Write data in reload counter bit 0 to 7. 
Read  Reads the BGR0 set value. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
 
  Data must be written in the Baud Rate Generato r Registers (BGR1 and BG
 R0) in 16-bit data access 
mode. 
   If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are 
reloaded only after the counter value has reached 15h00. In order to validate the new set values 
immediately, change the BGR1/0 set values  and execute the programmable clear (UPCL). 
   If the reload value is even, the LOW signal width of  serial clock is longer than the HIGH signal 
width for a single cycle of bus clock. If the valu e is odd, the serial clock has the same HIGH and 
LOW signal width. 
   Set the reload value to 3 or more. Note that data may not be received normally due  to the baud rate error 
and reload value setting. 
   When the baud rate generator is operating and if you  need to switch to the external clock (EXT=1), first 
set the BGR1 and BGR0 bits (baud rate generators 1  and 0) to 0. Then, execute the programmable clear 
instruction (UPCL) and select  the external clock (EXT=1). 
 
 
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6. LIN Interface (ver. 2.1) Registers 
 
6.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select transmit or receive 
FIFO, enable transmit FIFO interrupt, and control the interrupt flag. 
 
bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They must always be set to 0. 
Bit 15:14  Description 
0 Disables the FIFO test. 
1  Enables the FIFO test. 
 
 
If this 

bit is set to 1, the FIFO test is executed. 
 [bit 13] Unused bit  This bit  val

ue is undefined when read. 
This bit has no effect when written. 
 
[bit 12] FLSTE: Re-transmit data lost detect enable bit  This bit enables the FLST bit detection. 
If set to 0: The FLST bit detection is disabled. 
If set to 1: The FLST bit detection is enabled. 
Bit Description 
0  Disables the Data Lost detection. 
1  Enables the Data Lost detection. 
 
 
If you wish

 to set this bit to 1, set the FSET bit to 1 first, and then set this bit to 1. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 11] FRIIE: Receive FIFO idle detect enable bit 
This bit sets to detect the receive id le state if receive FIFO contains valid data for more than 8-bit hours. If 
the receive interrupt is enabled (SCR:RIE=1), a receive interrupt is genera ted when the receive idle state is 
detected. 
If set to 0: The receive idle  state detection is disabled. 
If set to 1: The receive idle state detection is enabled. 
Bit Description 
0  Disables the receive FIFO idle detection. 
1  Enables the receive FIFO idle detection. 
 
 
In case of usi n

g Receive FIFO, set this bit to 1. 
 [bit 10] FDRQ: Transmit FIFO data request bit  This bit requ e

sts for the transmit FIFO data. 
If this bit is 1, the transmit data is being requested. If the Transmit Interrupt is enabled (FTIE=1) during 
this time, a transmit FIFO interrupt request is output. 
The FDRQ bit is set when: 
   The FBYTE (for transmission) is 0 (Transmit FIFO is empty). 
   Transmit FIFO is reset. 
 
The FDRQ bit is  cleared when: 
   This bit is set to 0. 
   Transmit FIFO is filled with data. 
 
Bit Description 
0  Does not request for the transmit FIFO data. 
1  Requests for the transmit FIFO data. 
 
 
  If th e FB

YTE (for transmission) is 0 , this bit cannot be set
  to 0. 
   If this bit is 0, the FSEL bit state cannot be changed. 
   If this bit is set to 1, it has no effect on the operation. 
   If a read-modify-write instruction is issued, 1 is read. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 9] FTIE: Transmit FIFO interrupt enable bit 
This bit enables a transmit FIFO interrupt. If this bit is  set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
[bit 8] FSEL: FIFO select bit  This bit selects the tr ansmit or receive FIFO. 
If set to 0, transmit FIFO is assigned FIFO1, and receive FIFO is assigned FIFO2. 
If set to 1, transmit FIFO is assigned FIFO2, and receive FIFO is assigned FIFO1. 
Bit Description 
0 Transmit  FIFO:FIFO1; Receive FIFO:FIFO2 
1 Transmit  FIFO:FIFO2; Receive FIFO:FIFO1 
 
 
  This b it 

is not cleared by FI FO reset (FCL2=1,  FCL1
 =1). 
   To change this bit state, first disa ble the FIFO operation (FE2=0, FE1=0). 
 
 
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6. LIN Interface (ver. 2.1) Registers 
 
6.8.  FIFO Control Register 0 (FCR0) 
FIFO Control Register 0 (FCR0) is used to enable/disable the FIFO operation, reset FIFO, 
save the read pointer, and set the data re-transmission. 
 
bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (FCR1) - FLSTFLD FSETFCL2FCL1 FE2 FE1 
Attribute      - R R/W  W R/W  R/W  R/W R/W 
Initial 
value     - 0 0 0 0 0 0 0 
 
[bit 7] Unused bit  This bit value is undefined when read. 
This bit has no effect when written. 
 
[bit 6] FLST: FIFO re-transmit data lost flag bit  This bit shows that the re-transmit data of transmit FIFO has been lost. 
The FLST bit is set when: 
  The FLSTE bit of FIFO Control Register 1 (FCR1) is 1, the write pointer of transmit FIFO matches the 
read pointer which has been saved by th e FSET bit, and data is written in FIFO. 
 
The FLST bit is cleared when: 
   FIFO is reset (FCL bit is set to 1). 
   The FSET bit is set to 1. 
 
If this bit is set to 1, the data identified by the  read pointer (saved by the FSET bit) is overwritten. 
Therefore, the FLD bit cannot set the data re-transmission even if an error has occurr ed. If this bit is set to 
1 and if you wish to re-transmit data, first  reset FIFO. Then, write data in FIFO again. 
Bit Description 
0 No Data Lost has occurred. 
1  Data Lost has occurred. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 5] FLD: FIFO pointer reload bit 
This bit reloads the data, being saved in transmit FIFO by  the FSET bit, to the reload pointer. This bit can be 
used to re-transmit data after a communication error or others have occurred. 
When the re-transmission setting has finished, this bit is set to 0. 
Bit Description 
0 Not  reloaded 
1 Reloaded 
 
 
  If th is 

bit is 1, data is being reloaded in the read  poin
 ter. Therefore, data writing except for FIFO reset 
is disabled. 
   When FIFO is enabled or when data is being transmitted, this bit cannot be set to 1. 
   After you have set the TIE and TBIE bits to 0, set  this bit to 1. After you have enabled transmit FIFO, 
set the TIE and TBIE bits to 1. 
 
[bit 4] FSET: FIFO pointer save bit  This bit save s th

e transmit FIFO read pointer. 
If the read pointer is saved before transmission and if  the FLST bit is 0, data can be re-transmitted even 
when a communication error or others occur. 
If set to 1: The current read pointer value is saved. 
If set to 0: No effect. 
Bit Description 
0 Not  saved 
1 Saved 
 
 
This  b

it can be set to 1 only when the transmit byte count (FBYTE) is 0. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 3] FCL2: FIFO2 reset bit 
This bit resets the FIFO2 value. 
If this bit is set to 1, the FIFO2 internal state is initialized. 
Only the FCR1:FLST2 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit  During writing During reading 
0 No  effect. 
1 FIFO2 is reset.  0 is always read. 
 
 
  Disable th e tra

nsmission and receptio n first, and then reset FIFO2. 
   Set th e tran

smit FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE2 register is set to 0. 
 
 
[bit 2] FCL1: FIFO1 reset bit  This b it resets t

he FIFO1 state. 
If this bit is set to 1, the FIFO1 internal state is initialized. 
Only the FCR1:FLST1 bit is initialized, but the other bits of FCR1/0 registers are kept. 
Description Bit  During writing During reading 
0 No  effect. 
1 FIFO1 is reset.  0 is always read. 
 
 
  Disable th e tra

nsmission and receptio n first, and then reset FIFO1. 
   Set th e tran

smit FIFO interrupt enable bit to 0 before the execution. 
   The valid data count of the FBYTE1 register is set to 0. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
[bit 1] FE2: FIFO2 operation enable bit 
This bit enables or disables the FIFO2 operation. 
  To use the FIFO2 operation,  set this bit to 1. 
   If FIFO2 is set as transmit FIFO and if data exists in FIFO2 when this bit is set to 1, the data 
transmission starts immediately when  the LIN interface (ver. 2.1) is enabled to transmit data (TXE=1). 
During this time, set both TIE and TBIE bits to 0. Then, set this bit to 1 and set both TIE and TBIE 
bits to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO2 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(TDRE=1). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO2 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO2 state is held even if the FIFO2 operation is disabled. 
 
Bit Description 
0  Disables the FIFO2 operation. 
1  Enables the FIFO2 operation. 
 
[bit 0] FE1: FIFO1 operation enable bit  This bit enables or disables the FIFO1 operation. 
  To use the FIFO1 operation,  set this bit to 1. 
   If FIFO1 is set as transmit FIFO and if data exists in FIFO1 when this bit is set to 1, the data 
transmission starts immediately when  the LIN interface (ver. 2.1) is enabled to transmit data (TXE=1). 
During this time, set both TIE and TBIE bits to 0. Then, set this bit to 1 and set both TIE and TBIE 
bits to 1. 
   If receive FIFO is selected by the FSEL bit and if a r eceive error has occurred, this bit is cleared to 0. 
This bit cannot be set to 1 un til the receive error is cleared. 
   If FIFO1 is used as transmit FIFO, this bit must be  set to 1 or 0 when the transmit buffer is empty 
(TDRE=1). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 0 when the receive buffer is empty 
(SSR:RDRF=0) and no valid data exists in receive  FIFO (FBYTE2=0) after reception is disabled 
(SCR:RXE=0). 
   If FIFO1 is used as receive FIFO, this bit must  be set to 1 when the receive buffer is empty 
(SSR:RDRF=0) after receptio n is disabled (SCR:RXE=0). 
   The FIFO1 state is held even if the FIFO1 operation is disabled. 
 
Bit Description 
0  Disables the FIFO1 operation. 
1  Enables the FIFO1 operation. 
 
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6. LIN Interface (ver. 2.1) Registers 
 
6.9.  FIFO Byte Register (FBYTE) 
The FIFO Byte Register (FBYTE) indicates the effective data count in the FIFO buffer. Also, 
this register can be used to generate a receive interrupt when a certain number of data sets is 
received in the receive FIFO. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field (FBYTE2) (FBYTE1) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
The FBYTE register indicates the effective data coun t of FIFO. The following shows the settings of the 
FCR1:FSEL bit. 
Table 6-3 Display of data count 
FSEL  FIFO selection  Data count display 
0 FIFO2:Receive FIFO, FI FO1:Transmit FIFO FIFO2:FBYTE2, FIFO1:FBYTE1 
1  FIFO2:Transmit FIFO, FIFO1:Receive  FIFO FIFO2:FBYTE2, FIFO1:FBYTE1 
 
  The initial value of data transfer coun t is 0x08 for the FBYTE register. 
   Set a data count to flag a receive interrupt for the FBYTE register of receive FIFO. If  this transfer data 
count matches the FBYTE register display, th e interrupt flag (RDRF) is set to 1. 
   If both conditions below are satisfied  and if the receive idle state continues for more than 8 baud rate 
clocks, the interrupt flag (RDRF) is set to 1. 
  The receive FIFO idle detect  enable bit (FRIIE) is 1. 
   The number of data sets stored in the recei ve FIFO does not reach the transfer count. 
If the RDR data is read during counting of 8 clocks, this counter is reset to 0, and counting for 8 
clocks is restarted. If receive FIFO is disabled, this counter is reset to 0. If data remains in receive 
FIFO and if receive FIFO is enabled, the data counting is restarted. 
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