Fujitsu Series 3 Manual
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9. Descriptions of base timer functions
Timer Control Register 2 (Low-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the
T32 bit to 1 selects 32-bit timer mode.
Changes must be made...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-505.png "Page 506
9. Descriptions of base timer functions
Timer Control Register 2 (Low-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field T32 FMD2 FM D1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] T32: 32-bit timer selection bit This bit selects the 32-bit timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b011 to select the reload timer function, setting the
T32 bit to 1 selects 32-bit timer mode.
Changes must be made...")
![Page 507
9. Descriptions of base timer functions
[bit 3] OSEL: Output polarity specification bit This bit selects whether to invert the timer output level.
Used in combination with bit 2 MDSE, this bit generates the following output waveforms.
MDSE OSEL Output waveforms
0 0 Toggle output at the LOW level at the start of counting
0 1 Toggle output at the HIGH level at the start of counting
1 0 Rectangular waves at the HIGH level during counting
1 1 Rectangular waves at the LOW level during...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-506.png "Page 507
9. Descriptions of base timer functions
[bit 3] OSEL: Output polarity specification bit This bit selects whether to invert the timer output level.
Used in combination with bit 2 MDSE, this bit generates the following output waveforms.
MDSE OSEL Output waveforms
0 0 Toggle output at the LOW level at the start of counting
0 1 Toggle output at the HIGH level at the start of counting
1 0 Rectangular waves at the HIGH level during counting
1 1 Rectangular waves at the LOW level during...")
![Page 508
9. Descriptions of base timer functions
[bit 0] STRG: Software trigger bit When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering.
The read value of the STRG bit is always 0.
Soft ware triggering
is also enabled when 1 is written to the CTEN and
STRG bits simultaneously.
If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings.
Bit Description
0 Invalid
1 Start triggered by software
FUJITSU...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-507.png "Page 508
9. Descriptions of base timer functions
[bit 0] STRG: Software trigger bit When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering.
The read value of the STRG bit is always 0.
Soft ware triggering
is also enabled when 1 is written to the CTEN and
STRG bits simultaneously.
If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings.
Bit Description
0 Invalid
1 Start triggered by software
FUJITSU...")
![Page 509
9. Descriptions of base timer functions
Timer Control Register 2 (High-order bytes of TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.3.3 Timer Control Register (High-order bytes of TMCR).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2:...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-508.png "Page 509
9. Descriptions of base timer functions
Timer Control Register 2 (High-order bytes of TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.3.3 Timer Control Register (High-order bytes of TMCR).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2:...")
![Page 510
9. Descriptions of base timer functions
Status Control Register (STC)
bit 7 6 5 4 3 2 1 0
Field res TGIE res UDIE res TGIR res UDIR
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Note: The TMCR2 register is placed in the upper bytes of this register.
[bit 7] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit 6] TGIE: Trigger interrupt request enable bit This bit controls interrupt requests of bit 2 TGIR.
When the TGIE bit is enabled,...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-509.png "Page 510
9. Descriptions of base timer functions
Status Control Register (STC)
bit 7 6 5 4 3 2 1 0
Field res TGIE res UDIE res TGIR res UDIR
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Note: The TMCR2 register is placed in the upper bytes of this register.
[bit 7] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit 6] TGIE: Trigger interrupt request enable bit This bit controls interrupt requests of bit 2 TGIR.
When the TGIE bit is enabled,...")
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9. Descriptions of base timer functions
[bit 2] TGIR: Trigger interrupt request bit When a software trigger or trigger input is detected, the TGIR bit is set to 1.
The TGIR bit is cleared by writing 0.
Even if 1 is written to the TGIR bit, the bit value is not affected.
The read value of read-modify-write instructions is 1 regardless of the bit value.
Bit Description
0 Clears an interrupt cause.
1 Detects an interrupt cause.
[bit 1] res: Reserved bit The read value is 0....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-510.png "Page 511
9. Descriptions of base timer functions
[bit 2] TGIR: Trigger interrupt request bit When a software trigger or trigger input is detected, the TGIR bit is set to 1.
The TGIR bit is cleared by writing 0.
Even if 1 is written to the TGIR bit, the bit value is not affected.
The read value of read-modify-write instructions is 1 regardless of the bit value.
Bit Description
0 Clears an interrupt cause.
1 Detects an interrupt cause.
[bit 1] res: Reserved bit The read value is 0....")
![Page 512
9. Descriptions of base timer functions
9.3.4. PWM Cycle Set Register (PCSR)
The PWM Cycle Set Register (PCSR) is a register for storing the initial counter value. In 32-bit
mode and for the even channel, the initial count value of the lower 16 bits is stored. For the
odd channel, the initial count value of the upper 16 bits is stored. The initial value after a reset
is undefined. Be sure to use the 16-bit data transfer instruction to access this register.
bit 15 0
Field PCSR [15:0]...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-511.png "Page 512
9. Descriptions of base timer functions
9.3.4. PWM Cycle Set Register (PCSR)
The PWM Cycle Set Register (PCSR) is a register for storing the initial counter value. In 32-bit
mode and for the even channel, the initial count value of the lower 16 bits is stored. For the
odd channel, the initial count value of the upper 16 bits is stored. The initial value after a reset
is undefined. Be sure to use the 16-bit data transfer instruction to access this register.
bit 15 0
Field PCSR [15:0]...")
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9. Descriptions of base timer functions
9.3.5. Timer Register (TMR)
The Timer Register (TMR) is a register that reads the count value of a timer. In 32-bit mode
and for the even channel, the count value of the lower 16 bits is read. For the odd channel, the
count value of the upper 16 bits is read. The initial value is undefined.
Be sure to use the 16-bit data transfer instruction to read this register.
bit 15 0
Field TMR [15:0]
Attribute R
Initial value 0xXXXX
The value of the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-512.png "Page 513
9. Descriptions of base timer functions
9.3.5. Timer Register (TMR)
The Timer Register (TMR) is a register that reads the count value of a timer. In 32-bit mode
and for the even channel, the count value of the lower 16 bits is read. For the odd channel, the
count value of the upper 16 bits is read. The initial value is undefined.
Be sure to use the 16-bit data transfer instruction to read this register.
bit 15 0
Field TMR [15:0]
Attribute R
Initial value 0xXXXX
The value of the...")
![Page 516
9. Descriptions of base timer functions
Selection of count clock
The count clock of the counter can be selected from eight types by setting bit 8: CKS3 in the TMCR2
register and bit 14 to 12: CKS2, CKS1, and CKS0 in the TMCR register.
The selectable count clocks are as follows:
TMCR2 and TMCR registers
CKS3, CKS2, CKS1, and CKS0 bits Internal count clock to be selected
0b0000
Machine clock [Initial value]
0b0001 1/4 frequency of the machine clock
0b0010 1/16 frequency of the machine...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-515.png "Page 516
9. Descriptions of base timer functions
Selection of count clock
The count clock of the counter can be selected from eight types by setting bit 8: CKS3 in the TMCR2
register and bit 14 to 12: CKS2, CKS1, and CKS0 in the TMCR register.
The selectable count clocks are as follows:
TMCR2 and TMCR registers
CKS3, CKS2, CKS1, and CKS0 bits Internal count clock to be selected
0b0000
Machine clock [Initial value]
0b0001 1/4 frequency of the machine clock
0b0010 1/16 frequency of the machine...")
9. Descriptions of base timer functions [bit 2] TGIR: Trigger interrupt request bit When a software trigger or trigger input is detected, the TGIR bit is set to 1. The TGIR bit is cleared by writing 0. Even if 1 is written to the TGIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. [bit 1] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 0] UDIR: Underflow interrupt request bit When a count value underflow from 0x0000 to 0xFFFF occurs during counting from the value for which the HIGH width is set, the UDIR bit is set to 1. The UDIR bit is cleared by writing 0. Even if 1 is written to the UDIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 475 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.3.4. PWM Cycle Set Register (PCSR) The PWM Cycle Set Register (PCSR) is a register for storing the initial counter value. In 32-bit mode and for the even channel, the initial count value of the lower 16 bits is stored. For the odd channel, the initial count value of the upper 16 bits is stored. The initial value after a reset is undefined. Be sure to use the 16-bit data transfer instruction to access this register. bit 15 0 Field PCSR [15:0] Attribute R/W Initial value 0xXXXX This is a register for setting the cycle. Transfer to the Timer Register is performed at an underflow. Access the PCSR register with 16-bit data. Set the cycle for the PCSR register after setting the reload timer function using the FMD2, FMD1, and FMD0 bits in the TMCR register. When writing data in the PCSR register in 32-bit mode, access the upper 16-bit data (odd channel data) first, and then access the lower 16-bit data (even channel data). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 476 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.3.5. Timer Register (TMR) The Timer Register (TMR) is a register that reads the count value of a timer. In 32-bit mode and for the even channel, the count value of the lower 16 bits is read. For the odd channel, the count value of the upper 16 bits is read. The initial value is undefined. Be sure to use the 16-bit data transfer instruction to read this register. bit 15 0 Field TMR [15:0] Attribute R Initial value 0xXXXX The value of the 16-bit down counter is read. Access the TMR register with 16-bit data. When reading the TMR register in 32-bit mode, read the lower 16-bit data (even channel data) first, and then read the upper 16-bit data (odd channel data). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 477 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.4. PWC timer function The function of the base timer can be set to either the 16-bit PWM timer, 16-bit PPG timer, 16/32-bit reload timer, or 16/32-bit PWC timer using the FMD2, 1, and 0 bits in the Timer Control Register. This section explains the timer functions available when PWC is set. 1. Operations of the PWC timer 2. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWC timer is selected 3. Data Buf f er Register (DTBF) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 478 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.4.1. Operations of the PWC timer The PWC timer has the pulse width measurement function. Five types of count clock are available for measuring the time and cycle between any input pulse events. This section explains the basic functions and operations of the pulse width measurement function. Pulse width measurement function Count operation is not performed until the counter is started and cleared to 0x0000 and the specified measurement start edge is input. U pon detecting a measurement start edge , the counter starts count-up from 0x0001 and stops counting upon detecting a measur ement end edge. The value counted in between is stored as a pulse width in the register. An interrupt request can be generated when the measurement is completed or an overflow occurs. After the completion of measurement, it operates as follows depending on the measurement mode: In one-shot measurement mode: Stops the operation. In continuous measurement mode: Tr ansfers the counter value to the buffer register and stops counting until the measurement start edge is input again. Figure 9-17 Pulse width measurement operation (one-shot measurement mode/HIGH width measurement) Time 0xFFFF 0x0000 Count Start of the startup process Count stop(The solid line indicates the count value.) PWC input pulse to be measured Count clear Count start 0x0001 EDIR flag setting (Completion of measurement) CTEN Figure 9-18 Pulse width measurement operation (continuous measurement mode/HIGH width measurement) Data transfer to the DTBF Overflow OVIR flag setting EDIR flag setting Time 0xFFFF 0x0000 Count Start of the startup process Count stop (The solid line indicates the count value.) PWC input pulse to be measured Count clear Count start 0x0001 EDIR flag setting (Completion of measurement) CTEN Count restart 0x0001 Count continued Count stop Data transfer to the DTBF FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 479 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Selection of count clock The count clock of the counter can be selected from eight types by setting bit 8: CKS3 in the TMCR2 register and bit 14 to 12: CKS2, CKS1, and CKS0 in the TMCR register. The selectable count clocks are as follows: TMCR2 and TMCR registers CKS3, CKS2, CKS1, and CKS0 bits Internal count clock to be selected 0b0000 Machine clock [Initial value] 0b0001 1/4 frequency of the machine clock 0b0010 1/16 frequency of the machine clock 0b0011 1/128 frequency of the machine clock 0b0100 1/256 frequency of the machine clock 0b0101 0b0110 0b0111 Setting disabled 0b1000 1/512 frequency of the machine clock 0b1001 1/1024 frequency of the machine clock 0b1010 1/2048 frequency of the machine clock Others Setting disabled The machine clock is selected as the initial value after a reset. Be sure to select the counter clock before starting the counter. Selection of operation mode Set the TMCR to select the operation/measurement mode. Operation mode setting ... TMCR bit 10 to 8: EGS2, EGS1, and EGS0 (Selection of measurement edge) Measurement mode setting ... TMCR bit 2: MDSE (S election of one-shot/continuous measurement) The following provides a list of operation mode settings. Operation mode MDSEEGS2 EGS1 EGS0 Continuous measurement: Buffer enabled 0 0 0 0 ↑ to ↓ HIGH pulse width measuremen t One-shot measurement: Buffer disabled 1 0 0 0 Continuous measurement: Buffer enabled 0 0 0 1 ↑ to ↑ Cycle measurement between rising edges One-shot measurement: Buffer disabled 1 0 0 1 Continuous measurement: Buffer enabled 0 0 1 0 ↓ to ↓ Cycle measurement between falling edges One-shot measurement: Buffer disabled 1 0 1 0 Continuous measurement: Buffer enabled 0 1 1 1 ↑ or ↓ to ↑ or ↓ Interval measurement between all edges One-shot measurement: Buffer disabled 1 1 1 1 Continuous measurement: Buffer enabled 0 1 0 0 ↓ to ↑ LOW pulse width measurement One-shot measurement: Buffer disabled 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 1 0 0 1 1 1 Setting disabled 1 1 1 1 HIGH pulse width measurement in one-shot measurement mode is selected as the initial value after a reset. Be sure to select an operation mode before starting the counter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 480 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Starting and stopping pulse width measurement Set bit 1: CTEN bit in the TMCR to start, restart, or st op forcibly each operation. The pulse width measurement is started or restarted by writing 1 to the CTEN bit, and it is stopped forcibly by writing 0 to the CTEN bit. CTEN Function 1 Starts or restarts the pulse width measurement. 0 Forcibly stops the pulse width measurement. Operation after a restart After the counter is restarted in pulse measuremen t mode, counting is not performed until a measurement start edge is input. After a measurement start edge is detected, the 16-bit up counter starts counting from 0x0001. Restart An operation to start the counter again after it has been started and while it is in operation (writing 1 again while the CTEN bit is 1) is referred to as a restart. When restarted, the counter performs the following operation: When waiting for a measurement start edge: Has no effect on operation. When performing measurement: Clears the count to 0x0000 and waits for a measurement start edge again. When detection of a measurement end edge and the restart operation occu r simultaneously, a measurement end flag (EDIR) is set and, when in continuous measurement mode, the measurement result is transferred to the DTBF. Stop In one-shot measurement mode, since the count operation is stopped automatically by a counter overflow or completion of measurement, you do not have to be aware of the stop. In continuous measurement mode or when you want to stop the operation before it stops automatically, you have to stop it forcibly. Counter clear and initial value The 16-bit up counter is cleared to 0x0000 in the following cases: When a reset is performed When 1 is written to bit 1: CTEN bit in the TMCR (including the cases for restarting) The 16-bit up counter is initialized to 0x0001 in the following case: When a measurement start edge is detected FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 481 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Details on pulse width measurement operations One-shot measurement and continuous measurement Pulse width measurement can be performed in two modes: one for performing measurement only one time and the other for performing it continuously. Each mode is selected with the MDSE bit in the TMCR (see Selection of operation mode ).Differences between these modes are as follows: One -shot m easurem ent mode: When the first measurement end edge is input, th e counter stops counting, a measurement end flag (EDIR) in the STC is set, and no further measurement is performed. However, when restarted at the same time, it waits to start measurement. Continuous measurement mode: When a measurement end edge is input, the counte r stops counting, a measurement end flag (EDIR) in the STC is set, and the counter stops until the measurement start edge is input again. When the measurement start edge is input again, the counter is initialized to 0x0001 and measurement is started. After the measurement is completed, the result in the counter is transferred to the DTBF. Be sure to select/change measurement modes while the counter is stopped. Measurement result data There are differences between one-shot and continuo us modes in handling of measurement results and counter values and in DTBF functions. Differences between these modes in handling of measurement results are as follows: One-shot measurement mode: Reading the DTBF during operation obtains the count value being measured. Reading the DTBF after the completion of meas urement obtains the measurement result data. Continuous measurement mode: After the measurement is completed, the result in the counter is transferred to the DTBF. Reading the DTBF obtains the last measurement result. The previous measurement result is retained during the measurement operation. It is not possible to read the count value being measured. In continuous measurement mode, if the next m easurement is completed before the measurement result is read, the previous result is overwritten by th e new result. In this case, an error flag (ERR) in the STC is set. The error flag is cleared automatically when the DTBF is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 482 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Measurement modes and count operations The measurement mode can be selected from five types, differing in which part of the input pulse is measured. The following are explanations: Measurement mode EGS2, 1, and 0 Item to be measured (W: Pulse width to be measured) HIGH pulse width measurement 0b000 The width of the HIGH period is measured. Count (measurement) start: At detection of a rising edge Count (measurement) end: At detection of a falling edge Stop ↓ ↑ Sta r t ↓ Count stop ↑ Count start W W Cycle measurement between rising edges 0b001 The cycle between rising edges is measured. Count (measurement) start: At detection of a rising edge Count (measurement) end: At detection of a rising edge Cycle measurement between falling edges 0b010 The cycle between falling edges is measured. Count (measurement) start: At detection of a falling edge Count (measurement) end: At detection of a falling edge Interval measurement between all edges 0b011 The width between continuously input edges is measured. Count (measurement) start: At detection of an edge Count (measurement) end: At detection of an edge LOW pulse width measurement 0b100 The width of the LOW period is measured. Count (measurement) start: At detection of a falling edge Count (measurement) end: At detection of a rising edge WW ↑ Count start ↑ Count stop ↑ Start W WW ↓ Count start ↓ Count stop ↓ Start ↓ Stop ↓ Start W ↑ Stop ↑ Start W W ↑ Count start ↓ Count stop ↓ Start W Stop ↑ ↓ Start ↑Count stop ↑ Count start WW In any measurement mode, the counter is cleared to 0x0000 when started, and it does not perform the count operation until a measurement start edge is input. Once a measurement start edge is input, the counter continues incrementing for every count clock until a measurement end edge is input. In pulse width measurement between all edges or cycle measurement in continuous measurement mode, an end edge is also a start edge for the next measurement. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 483 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Pulse width/cycle calculation method After completion of measurement, the measured pulse width/cycle can be calcu lated as follows from the measurement result data stored in the DTBF: T W = n x t TW : Measured pulse width/cycle n : Measurement result data stored in the DTBF t : Count clock cycle Generation of interrupt requests Two interrupt requests can be generated. Interrupt request due to a counter overflow When count-up causes an overflow during measurement, an overflow flag (OVIR) is set and an interrupt request is generated if overflow interrupt requests are enabled. Interrupt request due to completion of measurement When a measurement end edge is detected, a measur ement end flag (EDIR) in the STC is set and an interrupt request is generated if measurem ent end interrupt requests are enabled. The measurement end flag (EDIR) is cleared automatically when the measurement result DTBF is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 484 MB9Axxx/MB9Bxxx Series