Fujitsu Series 3 Manual
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5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 51
5.6. Transfer Destination Address Register (DMACDA )
This section describes transfer destination address register ( DMACDA).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACDA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACDA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-265.png "Page 266
5. Registers of DMAC FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: DMAC
FUJITSU SEMICONDUCTOR CONFIDENTIAL 51
5.6. Transfer Destination Address Register (DMACDA )
This section describes transfer destination address register ( DMACDA).
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Field DMACDA[31:16]
Attribute R/W
Initial
Va l u e 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Field DMACDA[15:0]
Attribute R/W
Initial
Va l u e 0 0 0 0...")
2. Configuration, Block Diagram, and Operation 2. Configuration, Block Diagram, and Operation This section explains the configuration, block diagram, and operation of the I/O port. Configuration of the I/O Port By setting registers of the I/O port, select Inpu t/Output direction and select GPIO/peripheral. Figure 2-1 shows the details of the I/O port. Figure 2-1 Block Diagram of the I/O Port PFR EPFR FUJITSU SEMICONDUCTOR LIMITED Peripheral output signal 2 If there is no output pin setting, input direction.Pin DDR Peripheral output signal 1 External bus output signal Peripheral direction signal 2 PCR Peripheral direction signal 1 External bus direction signal PFR EPFR If ADE/SPSR=1, input direction ADE/ SPSR 1 0 1 0 0 1 PDOR EPFR PDIR PDIR (GPIO read) can be always read when digital input is selected Special pin judgement USB has no pull-up When ADE/SPSR=1, input value is fixed to 0. When ADE/SPSR=0, digital pin input. ADE/ SPSR Peripheral macro Relocation pin input Special pin ADC When ADE/SPSR=1, USB Special pin is balid oscillation CHAPTER 9: I/O PORT MN706-00002-1v0-E 235 MB9Axxx/MB9Bxxx Series
2. Configuration, Block Diagram, and Operation Ta b l e 2 - 1 describes register function. The PFR, DDR, PD IR, PDOR, and PCR register have 1-bit control register for each I/O port and select a function for the I/O port. The ADE register has 1-bit control register for each I/O port which doub les as an analog input pin and selects a function for the I/O port. The SPSR register selects a function for the I/O port which doubles as a USB pin or an oscillation pin. The EPFR register has control register for each I/O pin of peripheral functions and selects to which I/O port an I/O pin of peripheral functions will be relocated. Table 2-1 Register Function Descriptions Register name Function description ADE A register to set whether the I/O port will be used as a special pin (an analog input pin) or a digital input/output pin. SPSR A register to set whether the I/O port will be used as a special pin (USB or oscillation) or a digital input/output pin. PFR A register to set whether the I/O port will be used as a GPIO function or an input/output pin of peripheral functions. PCR A register to set whether a pull-up resistor of the I/O port will be connected or disconnected if the I/O port is used as a digital input pin or a digital bidirectional pin. DDR A register to set whether the I/O port will be used as an input pin or an output pin if the I/O port is used as a GPIO function pin. Note: If a pin is selected as an I/O pin of peripheral functions, a setting value is invalid. PDIR A register to read the level status of the I/O port. If the I/O port is used as a digital input pin, it reads input level. If the I/O port is used as a digital output pin, it reads output level. If the I/O port is used as an analog input pin, it always reads 0. PDOR A register to set output level if the I/O port is used as an output pin of GPIO function. When 0 is set, it outputs Low level. When 1 is set, it outputs High level. Note: If a pin is selected as GPIO input or intput/output of peripheral functions, a setting value is invalid. EPFR A register to select a function for an input/output of peripheral functions and set relocation function. Setting a peripheral output pin It sets whether to produce output for the I/O port or not. In addition, it can also set to which I/O port a pin of peripheral functio ns will be relocated for each pin. Setting a peripheral input pin It can set to which I/O port a pin of periphe ral functions will be relocated for each pin. Setting a peripheral bidirectional pin It can set to which I/O port a pin of peri pheral functions will be relocated for each pin FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 236 MB9Axxx/MB9Bxxx Series
2. Configuration, Block Diagram, and Operation
Ta b l e 2 - 2 lists pin functions which availability depends on selected I/O port functions and register setting
values.
Table 2-2 I/O Port Functions and Register Setting Values
I/O Port Function
Available main function Available sub function ADE/
SPSR PFR
DDR PCR EPFR
Special pin
Analog input
USB
Oscillation N/A 1 - - Disconnect *0
GPIO function input pin
Peripheral function input pin 0 Valid
GPIO function output pin GPIO function input pin (FB)
Peripheral function input pin (FB) 0
1 Disconnect *1
Peripheral function output pin
GPIO function input pin (FB)
Peripheral function input pin (FB) Disconnect *2
Peripheral function
bidirectional pin GPIO function input pin (FB)
Peripheral function input pin (FB)
Valid *3
Peripheral function input pin
GPIO function input pin 0
1 -
Valid *4
Legends
- : Indicates that a register setting value does not affect pin functions.
Valid : Indicates that a pull-up resistor is disconnected if PCR register value is 0. Indicates that a pull-up resistor is co nnected if PCR register value is 1.
Disconnect : Indicates that a pull- up resistor is disconnected regardless of PCR register value.
(FB) : Indicates that an output signal of the I/O port provides feedback and the level of the I/O port can be read from PDIR. The signal can be also used as input for peripheral functions.
*0 : If the input pin of peripheral functions is selected for the I/O port, the setting is invalid. If the output pin of peripheral functions is selected for the I/O port, the setting is invalid.
If the bidirectional pin of peripheral functions is selected for the I/O port, the setting is invalid.
*1 : If the input pin of peripheral functions is selected for the I/O port, the setting is valid. If the output pin of peripheral functions is selected for the I/O port, the setting is invalid.
If the bidirectional pin of peripheral functions is selected for the I/O port, the setting is invalid.
*2 : Indicates that the output pin of peripheral functions is selected for the I/O port.
*3 : Indicates that the bidirectional pin of peripheral functions is selected for the I/O port.
*4 : Indicates that neither the output pin nor the bidirectional pin of peripheral functions is selected for the I/O port.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 9: I/O PORT
MN706-00002-1v0-E
237
MB9Axxx/MB9Bxxx Series
2. Configuration, Block Diagram, and Operation Initially Selected Functi ons for the I/O Port Ta b l e 2 - 3 describes initially selected functions fo r each I/O port after reset is released. Table 2-3 Initially Selected Functions for Each I/O Port after Reset Is Released No Pin Initially selected function 1 TRSTX, TCK, TDI, TMS, TDO JTAG pin is selected. Pull-up is enabled. 2 ANxx Can be used as an analog input pin. Digital input is cut off and 0 is input. 3 X0A, X1A Can be used as an oscillation pin. Digital input is cut off and 0 is input. 4 All GPIO pins other than the above pins Digital input. Output is Hi-Z. Note: For the status of pins other than GPIO (a MD pin, a reset pin), see Data Sheet. All the output selection values of EPFR during reset are no output. About Relocation Function Some input/output of peripheral functions have more than one pin (relocation pin). One of the pins can be selected by setting EPFR. Figure 2-2 show the schematic view of relocation function. Figure 2-2 Schematic View of Relocation Function Relocation select Relocation output pin _0 Peripheral macroOutput selectRelocation output pin _1 Relocation output pin _2 Relocation input pin A_0 Peripheral macroRelocation input pin A_1 Relocation input pin A_2 Input select Note: Which peripheral function is allocated to which pin depends on products. See the pin function list of Data Sheet. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 238 MB9Axxx/MB9Bxxx Series
2. Configuration, Block Diagram, and Operation Even if the input of one I/O port is connected to two or more peripheral functions, all peripheral inputs can be used by setting EPFR. For example, in Figure 2-3, by selecting input for both Relocation input pin A_2 a n d Relocation input pin B_1, simultaneous usage is possible. In this way, it is possible to use external interrupt and a multi-function serial input pin shared by one I/O port simultaneously. Figure 2-3 Multiple Peripheral Inputs Relocation input pin A_0 Peripheral macro ARelocation input pin A_1 Relocation input pin A_2/relocation input pin B_1 Input select Relocation input pin B_0 Relocation input pin B_2 Input selectPeripheral macro B Even if an I/O cell pin is set as output, it can work as an input pin because input is not masked. For example, timer output can be used as external interrupt input which shared. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 239 MB9Axxx/MB9Bxxx Series
2. Configuration, Block Diagram, and Operation About Fixed Priority of EPFR Outputs Only one output pin function among two or more outputs is allocated to one I/O port. By setting the EPFR register, if more than one output is set, fixed priority is applied and output pins are selected. Figure 2-4 shows output pins and fixed priority. Figure 2-4 Output Pins and Fixed Priority Fixed priority functionPeripheral A output pin _0/ peripheral B output pin _1/ peripheral C output pin _0 Peripheral macro C Peripheral macro B Peripheral macro A Ta b l e 2 - 4 describes fixed priority of EPFR. Table 2-4 Fixed Priority of EPFR Higher Peripheral function Applied pin ↓ JTAG, trace Output pin, I/O pin ↓ USB I/O pin ↓ CAN Output pin ↓ Multi-function serial Output pin, I/O pin ↓ Base timer output I/O pin ↓ Multi-function timer Output pin ↓ External bus Output pin, I/O pin ↓ Internal CR waveform output Output pin Lower Note: Fixed priority is only applicable when function is set to output. In case of input, there is no fixed priority. Due to output setting on the lower part of the priority, the EPFR register always includes no output setting. If you are going to use a pin as an input pin of peripheral functions, disable all shared output settings. If every output of a pin is not selected, th e pin works as an external input pin. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 240 MB9Axxx/MB9Bxxx Series
3. Setup Procedure Example 3. Setup Procedure Example This section explains a procedure example of setting up the I/O port. Setup of the I/O Port By setting registers of the I/O port, select I/O direction and select GPIO/peripheral. Figure 3-1 shows a setup procedure example. Figure 3-1 Setup Procedure Example of the I/O Port Set peripherals EPFR peripheral output enabled Note: Output follows fixed priority EPFR peripheral input enabled Special pin selected Ye s Ye s No No No Set GPIO The pin doubles as a special pin? Ye s PFR=1? Set peripheral output? ADE/SPSR=1? No special pin No Ye s DDR=0? Set GPIO input PDIR readable Set GPIO output Setting PDOR output possible No Ye s Set EPFR Set peripheral pins Sta r t FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 241 MB9Axxx/MB9Bxxx Series
4. Register List 4. Register List This section provides the register list of the I/O port. Ta b l e 4 - 1 provides the register list. Table 4-1 Register List of the I/O Port Abbreviation Register name See PFR0 Port function setting register 0 PFR1 Port function setting register 1 PFR2 Port function setting register 2 PFR3 Port function setting register 3 PFR4 Port function setting register 4 PFR5 Port function setting register 5 PFR6 Port function setting register 6 PFR7 Port function setting register 7 PFR8 Port function setting register 8 4.1 PCR0 Pull-up setting register 0 PCR1 Pull-up setting register 1 PCR2 Pull-up setting register 2 PCR3 Pull-up setting register 3 PCR4 Pull-up setting register 4 PCR5 Pull-up setting register 5 PCR6 Pull-up setting register 6 PCR7 Pull-up setting register 7 4.2 DDR0 Port input/output direction setting register 0 DDR1 Port input/output direction setting register 1 DDR2 Port input/output direction setting register 2 DDR3 Port input/output direction setting register 3 DDR4 Port input/output direction setting register 4 DDR5 Port input/output direction setting register 5 DDR6 Port input/output direction setting register 6 DDR7 Port input/output direction setting register 7 DDR8 Port input/output direction setting register 8 4.3 PDIR0 Port input data register 0 PDIR1 Port input data register 1 PDIR2 Port input data register 2 4.4 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 242 MB9Axxx/MB9Bxxx Series
4. Register List Abbreviation Register name See PDIR3 Port input data register 3 PDIR4 Port input data register 4 PDIR5 Port input data register 5 PDIR6 Port input data register 6 PDIR7 Port input data register 7 PDIR8 Port input data register 8 4.4 PDOR0 Port output data register 0 PDOR1 Port output data register 1 PDOR2 Port output data register 2 PDOR3 Port output data register 3 PDOR4 Port output data register 4 PDOR5 Port output data register 5 PDOR6 Port output data register 6 PDOR7 Port output data register 7 PDOR8 Port output data register 8 4.5 ADE Analog input setting register 4.6 SPSR Special Port Setting Register 4.18 EPFR00 Extended pin function setting register 00 4.8 EPFR01 Extended pin function setting register 01 4.9 EPFR02 Extended pin function setting register 02 4.10 - Reserved - EPFR04 Extended pin function setting register 04 4.11 EPFR05 Extended pin function setting register 05 4.12 EPFR06 Extended pin function setting register 06 4.13 EPFR07 Extended pin function setting register 07 4.14 EPFR08 Extended pin function setting register 08 4.15 EPFR09 Extended pin function setting register 09 4.16 EPFR10 Extended pin function setting register 10 4.17 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 243 MB9Axxx/MB9Bxxx Series
4. Register List 4.1. Port Function Setting Register (PFRx) The PFRx register selects usage of a pin. List of PFR Register Configuration 31 16 15 0 Initial value Attribute Support reserved PFR0 0x001FR/W P0F to P00 reserved PFR1 0x0000 R/W P1F to P10 reserved PFR2 0x0000 R/W P2F to P20 reserved PFR3 0x0000 R/W P3F to P30 reserved PFR4 0x0000 R/W P4F to P40 reserved PFR5 0x0000 R/W P5F to P50 reserved PFR6 0x0000 R/W P6F to P60 reserved PFR7 0x0000 R/W P7F to P70 reserved PFR8 0x0000 R/W P8F to P80 Detailed Register Configuration bit 31 16 15 0 Field reserved PFRx Register Function [bit31:16] res : Reserved Bit 0x0000 is read out from these bits. When writing these bits, set them to 0x0000. [bit15:0] PFRx : Port Function Setting Register x Selects usage of a pin. bit15:0 Description Reading Can read out the setting value of the register. Writing 0 Uses a pin as a GPIO pin. Writing 1 Uses a pin as an input/output pin of peripheral functions. The x of PFRx is a wildcard. PFRx indicates PFR0, PFR1, PFR2, etc. Th e x of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, et c. PxF indicates P0F, P1F, P2F, etc. Functions can be set for 16 ports from PxF to Px0. Each bit in the register sets each pin individua lly. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of PFR0 sets P0F, the 14th bit of PFR0 sets P0E, and the 0th bit of PFR0 sets P00. As a JTAG pin is selected for P04 to P00, the initial value is 1. For a pin which is not available in your product, writing a value to the bit is invalid, and the read value is undefined. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 244 MB9Axxx/MB9Bxxx Series