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Fujitsu Series 3 Manual

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2. CRC Operations 
 
2.2.  CRC use examples 
Figure 2-2 to Figure 2-5  show CRC use examples. 
 Use example 1    CRC16, Byte input fixed 
Figure 2-2 Use example 1 (CRC16, byte input fixed, core byte order : Big endian) 
//***********************************************************
//  CRC16 (CRC ITU-T)
//     polynomial: 0x1021
//     initial value: 0xFFFF
//     CRCCR.CRC32: 0 //CRC16
//     CRCCR.LTLEND: 0 //big endian
//     CRCCR.LSBFST: 0 //MSB First
//     CRCCR.CRCLTE: 0 //CRC big endian
//     CRCCR.CRCLSF: 0 //CRC MSB First
//     CRCCR.FXOR: 0 //CRC Final XOR off
//***********************************************************
//
// Example 1-1 (Byte-base writing)
//
// Initialization
B_WRITE (CRCCR, 0x01);
// data write “123456789”
B_WRITE (CRCIN, 0x31);
B_WRITE (CRCIN, 0x32); 
B_WRITE (CRCIN, 0x33); 
B_WRITE (CRCIN, 0x34); 
B_WRITE (CRCIN, 0x35); 
B_WRITE (CRCIN, 0x36); 
B_WRITE (CRCIN, 0x37); 
B_WRITE (CRCIN, 0x38); 
B_WRITE (CRCIN, 0x39);
// read result 
H_READ (CRCR+2, data); 
// check result 
assert (data == 0x29B1); 
//
// Example 1-2 (CRC check) 
//
// Initialization
B_WRITE (CRCCR, 0x01); 
// data write 123456789 + CRC 
B_WRITE (CRCIN, 0x31); 
B_WRITE (CRCIN, 0x32); 
B_WRITE (CRCIN, 0x33); 
B_WRITE (CRCIN, 0x34); 
B_WRITE (CRCIN, 0x35); 
B_WRITE (CRCIN, 0x36); 
B_WRITE (CRCIN, 0x37); 
B_WRITE (CRCIN, 0x38);
B_WRITE (CRCIN, 0x39); 
B_WRITE (CRCIN, 0x29); //
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2. CRC Operations 
 
  Use example 2    CRC16, differe nt input bit widths mixed 
Figure 2-3 Use example 2 (CRC16, different input  bit widths mixed, core byte order: Big endian) 
//************************************************************
//  CRC16 (CRC ITU-T)
//     polynomial: 0x1021
//     initial value: 0xFFFF
//     CRCCR.CRC32: 0 //CRC16
//     CRCCR.LTLEND: 0 //big endian
//     CRCCR.LSBFST: 0 //MSB First
//     CRCCR.CRCLTE: 0 //CRC big endian
//     CRCCR.CRCLSF: 0 //CRC MSB First
//     CRCCR.FXOR: 0 //CRC Final XOR off
//************************************************************
//
// Example 2-1 (Writing widths mixed)
//
// Initialization
B_WRITE (CRCCR, 0x01); 
// data write 123456789 
W_WRITE (CRCIN, 0x31323334); 
H_WRITE (CRCIN, 0x3556); 
H_WRITE (CRCIN+2, 0x3738); 
B_WRITE (CRCIN+3, 0x39); 
// read result 
H_READ (CRCR+2, data); 
// check result 
assert  (data == 0x29B1); 
//
// Example 2-2 (CRC check) 
//
// Initialization
B_WRITE (CRCCR, 0x01); 
// data write 123456789 + CRC 
W_WRITE (CRCIN, 0x31313334); 
W_WRITE (CRCIN, 0x35363738); 
H_WRITE (CRCIN, 0x3929); //
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2. CRC Operations 
 
  Use example 3    CRC32, byte order: Big endian 
Figure 2-4 Use example 3 (CRC32, byte order: Big endian) 
//************************************************************
// CRC32 (IEEE-802.3)
// polynomial: 0x04C11DB7
// initial value: 0xFFFF_FFFF
// CRCCR.CRC32 1 // CRC32 
// CRCCR.LTLEND: 0 // big endian 
// CRCCR.LSBFST: 1 // LSB First
// CRCCR.CRCLTE: 0 // CRC big endian
// CRCCR.CRCLSF: 1 // CRC LSB First
// CRCCR.FXOR: 1 // CRC Final XOR on
//************************************************************
//
// Example 3-1 (CRC32)
//
// Initialization
B_WRITE (CRCCR, 0x6B); 
// data write 123456789
W_WRITE (CRCIN, 0x31323334); 
W_WRITE (CRCIN, 0x35363738); 
B_WRITE (CRCIN, 0x39); 
// read result 
W_READ (CRCR, data); 
// check CRC result 
assert (data == 0x2639F4CB); //
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2. CRC Operations 
 
  Use example 4    CRC32, byte  order: Little endian 
Figure 2-5 Use example 4 (CRC32, byte order: Little endian) 
//************************************************************
// CRC32 (IEEE-802.3)
// polynomial: 0x04C11DB7 
// initial value: 0xFFFF_FFFF
// CRCCR.CRC32  1 // CRC32
// CRCCR.LTLEND: 1 // big endian 
// CRCCR.LSBFST: 1 // LSB First
// CRCCR.CRCLTE: 1 // CRC big endian
// CRCCR.CRCLSF: 1 // CRC LSB First 
// CRCCR.FXOR: 1 // CRC Final XOR on
//************************************************************
//
// Example 4-1 (CRC32)
//
// Initialization
B_WRITE (CRCCR, 0x7F); 
// data write 123456789 
W_WRITE (CRCIN, 0x34333231); 
W_WRITE (CRCIN, 0x38373635);
B_WRITE (CRCIN, 0x39); 
// read result
W_READ (CRCR, data); 
// check result 
assert (data == 0xCBF43926); //
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3. CRC Registers 
 
3. CRC Registers 
This section provides a list of CRC registers. 
  CRC registers 
Table 3-1 CRC register list 
Abbreviation Register name See 
CRCCR CRC Control Register  3.1 
CRCINIT Initial Value Register 3.2 
CRCIN Input Data Register  3.3 
CRCR CRC Register  3.4 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
1269 
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3. CRC Registers 
 
3.1.  CRC Control Register (CRCCR) 
The CRC Control Register (CRCCR) is used to control CRC calculation. 
 
bit 7 6 5 4 3 2 1 0 
Field res FXOR CRCLSFCRCLTE LSBFSTLTLEND CRC32 INIT 
Attribute R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial value 0 0 0  0 0 0 0 0 
 
[bit 7] RES: Reserved bit  The read value is 0. 
Be sure to write 0 to this bit. 
 
[bit 6] FXOR: Final XOR control bit  This bit is used to output the CRC result as the XOR value or XOR. 
The OR value is set to ALLH. This bit is inverted at FXOR=1. 
This processing is performed in the latter part of the CRC Register processing. The CRC result is therefore 
reflected on the read value imme diately after this bit was set. 
Bit Description 
0 None 
1 Yes 
 
[bit 5] CRCLSF: CRC result bit-order setting bit  This is a bit-order setting bit for CRC result. 
This bit is used to rearrange bits  within each byte. Set 0 to specify  MSB First and set 1 to specify LSB 
First. 
This processing is performed in the latter part of the CRC Register processing. The CRC result is therefore 
reflected on the read value imme diately after this bit was set. 
Bit Description 
0 MSB First 
1 LSB First 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
1270 
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3. CRC Registers 
 
[bit 4] CRCLTE: CRC result byte-order setting bit 
This is a byte-order setting bit for CRC result. 
This bit is used to rearrange the by te order in each word. Set 0 to speci fy big endian and set 1 to specify 
little endian. 
This processing is performed in the latter part of the CRC Register processing. The CRC result is therefore 
reflected on the read value imme diately after this bit was set. 
If this bit is set to 1 in CRC16 mode, data is output to bit 31 to bit 16. 
Bit Description 
0 Big endian 
1 Little endian 
 
[bit 3] LSBFST: Bit-order setting bit  This is a bit-order setting bit. 
This bit is used to specify the head bit of a byte (8 bits). Set 0 to specify MSB First and set 1 to specify 
LSB First. 
Four types of processing orders can be specified when this bit is combined with the LTLEND setting. 
Bit Description 
0 MSB First 
1 LSB First 
 
[bit 2] LTLEND: Byte-order setting bit  This is a byte-order setting bit. 
This bit is used to specify the byte order with the wr ite width. Set 0 to specify big endian and set 1 to 
specify little endian. 
Bit Description 
0 Big endian 
1 Little endian 
 
[bit 1] CRC32: CRC mode selection bit  This bit is used to select the CRC16 or CRC32 mode. 
Bit Description 
0 CRC16 
1 CRC32 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
1271 
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3. CRC Registers 
 
[bit 0] INIT: Initialization bit 
This is an initialization bit. Writing 1 initializes data.  This bit does not have a value, and always returns 
0 at reading. 
At initialization, the value of the Initial Value Register is loaded to the CRC Register. 
Initialization must be performed once  at the start of CRC calculation. 
Description Bit 
Write Read 
0 Invalid 
1 Initialization  Always reads 0. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
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3. CRC Registers 
 
3.2.  Initial Value Register (CRCINIT) 
The Initial Value Register (CRCINIT) is used to save the initial values for CRC calculation. 
 
bit 31       0 
Field D31-D0 
Attribute R/W 
Initial value  0xFFFFFFFF 
 
[bit 31:0] D31 to D0: Initial value bit  This bit is used to save the initial values for CRC calculation. 
Write the initial values for CRC calculation to this register. 
(0xFFFFFFFF at resetting) 
In CRC16 mode, D15 to D0 are used while D31 to D16 are ignored. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
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3. CRC Registers 
 
3.3.  Input Data Register (CRCIN) 
The Input Data Register (CRCIN) is used to set input data for CRC calculation. 
 
bit 31       0 
Field D31-D0 
Attribute R/W 
Initial value  0x00000000 
 
[bit 31:0] D31 to D0: Input data bit  This bit is used to set input data for CRC calculation. 
Write input data for CRC calculation to this register.  There are three types of bit widths: 8, 16, and 32, 
which can be specified together.   
The byte and half-word writing positio ns are arbitrary. The available address positions are as follows. 
   Byte writing  :  +0, +1, +2, +3 
   Half-word writing  :  +0, +2 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  22: CRC  \050Cyclic  Redundancy  Check\051 
MN706-00002-1v0-E 
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