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Fujitsu Series 3 Manual

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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   12 
5.4.  USB-PLL Control Register 3 (UPCR3) 
The UPCR3 sets the frequency division ratio (K) of PLL macro for USB.  
 Register configuration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPLLK 
Attribute - R/W 
Initial value - 5'b00000 
 
  Register functions  
[bit  7:5] res: Reserved bits  
"0b000" is read from these bits.  
Set these bits to "0b000" when writing.  
[ bit  4:0] UPLLK: Frequency division ratio (K) setting bit of the USB -PLL clock  
Bit 4:0 Description 
00000 
Divides the frequency by (UPLLK+1)  
(Example) UPLLK = "00000" => 1/1 frequency [Initial value]  
00001 
• 
• 
11111 
 
< Note > 
This register is not initialized by software reset.  
 
 
CHAPTER  20-1: USB Clock  Generation 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   13 
5.5.  USB-PLL Control Register 4 (UPCR4) 
The UPCR4 Register sets the frequency division ratio (N) of PLL macro for USB.  
 Register configuration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPLLN 
Attribute - R/W 
Initial value - 5'b10111 
 
  Register functions  
[bit  7:5] res: Reserved bits  
"0b000" is read from these bits.  
Set these bits to "0b000" wh en writing. 
[ bit  4:0] UPLLN: Frequency division ratio (N) setting bit of the USB -PLL clock  
Bit 4:0 Description 
00000 This setting is disabled. 
00001 
Divides the frequency by (UPLLN+1)  
(Example) UPLLN = "10111" => 1/24 frequency [Initial value]  • 
• 
11111 
 
< Note > 
This register is not initialized by software reset.  
 
 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   14 
5.6.  USB-PLL Macro Status Register (UP_STR) 
The UP_STR indicates the macro status of USB -PLL.  
 Register configuration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPRDY 
Attribute - R 
Initial value - 1'b0 
 
  Register functions  
[bit  7:1] res: Reserved bits  
"0b0000000" is read from these bits.  
Set these bits to "0b0000000" when writing.  
[bit 0] UPRDY: USB -PLL macro oscillation stable bit  
Bit Description 
0 In a stabilization wait or an oscillation stop state [Initial value] 
1 In a stabilized state 
 
This register is not initialized by software reset.  
 
 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   15 
5.7.  USB- PLL Interrupt Enable Register (UPINT_ENR)  
The UPINT_ENR enables/disables the USB-PLL oscillation stabilization complete interrupt.  
 Register conf iguration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPCSE 
Attribute - R/W 
Initial value - 1'b0 
 
 Register functions  
[bit  7:1] res: Reserved bits  
"0b0000000" is read from these bits.  
Set these bits to "0b0000000" when writing.  
[bit 0] UPCSE: USB -PLL macro oscillation stabilization complete interrupt enable bit  
Bit Description 
0 Disables the interrupt [Initial value] 
1 Enables the interrupt 
 
CHAPTER  20-1: USB Clock  Generation 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   16 
5.8.  USB- PLL Interrupt Status Register (UPINT_STR)  
The UPINT_STR indicates the status of USB-PLL oscillation stabilization wait interrupts.  
 Register configuration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPCSI 
Attribute - R 
Initial value - 1'b0 
 
  Register functions  
[bit  7:1] res: Reserved bits  
"0b0000000" is read from these bits.  
Set these bits to "0b0000000" when writing.  
[bit 0]  UPCSI: USB- PLL interrupt cause status bit  
Bit Description 
0 No interrupt has occurred [Initial value] 
1 An interrupt has occurred 
 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   17 
5.9.  USB-PLL Interrupt Clear Register (UPINT_CLR) 
The UPINT_CLR is used to clear the USB -PLL interrupt cause.  
 Register config uration 
bit 7 6 5 4 3 2 1 0 
Field Reserved UPCSC 
Attribute - W 
Initial value - 1'b0 
 
 Register functions  
[bit  7:1] res: Reserved bits  
"0b0000000" is read from these bits.  
Set these bits to "0b0000000" when writing.  
[bit 0] UPCSC: USB -PLL macro oscillation stabilization interrupt cause clear bit  
Bit Description 
0 Disabled [Initial value] 
1 Clears the PLL macro oscillation stabilization wait interrupt. 
 
< Note > 
Writing to this register and clearing the interrupt clears the UPINT_STR Register.  
 
 
CHAPTER  20-1: USB Clock  Generation 
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    							   5. Register List  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   18 
5.10.  USB Enable Request Register (USBEN) 
The USBEN enables/disables USB controller operation.  
 Register configuration 
bit 7 6 5 4 3 2 1 0 
Field Reserved USBEN 
Attribute - R/W 
Initial value - 1'b0 
 
  Register functions  
[bit  7:1] res: Reserved bits  
"0b0000010" is read f rom these bits. 
Set these bits to "0b0000010" when writing.  
[bit 0] USBEN: USB enable bit  
Bit Description 
0 Disables USB operation (Resets the USB controller) [Initial value] 
1 Enables the USB operation 
 
< Notes > 
⋅  When using USB, set this bit to "1" previ o u s l y. 
⋅   Supply at least five cycles of USB clocks to the USB controller before setting this bit to "1".  
 
 
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    							   6. Usage Precautions  FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB  Clock Generation  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   19 
6.  Usage Precautions 
This section explains the precautions for using clock generation unit.  
⋅  Setting clock output and stopping PLL macro  
Do not disable the  USB clock output (UCEN = 0) and select the USB clock (UCSEL) at the same time.  
Be sure to disable the USB clock output before selecting the USB clock.  
⋅   Setting the frequency division ratio of PLL oscillation  
When the PLL frequency division ratio is changed  after stabilization of PLL oscillation, stop the PLL 
oscillation once, change the frequency division ratio, and then enable the PLL oscillation again.  
⋅   Selecting the main clock  
By writing "0" to the UCSEL bit, the main clock is selected as the USB clock.  
T he main clock should be selected when the main clock oscillates at 48 MHz.  
⋅   Setting the PLL oscillation stabilization wait time  
Set the oscillation stabilization wait time with the PLL Oscillation Stabilization Wait Time Setup 
Register, and then enable PLL.  Do not change the oscillation stabilization wait time while waiting for 
oscillation to stabilize.  
⋅   Selecting the PLL macro input clock  
By writing "1" to the UCSEL bit, the PLL macro oscillation clock is selected as the USB clock.  
Write "0" to the UPINC bit  of the USB-PLL Control Register 1 (UPCR1), and be sure to select the main 
clock as the PLL macro input clock.  
The following  Table 6-1 shows relationship between the USB clock and UPDS/UPLLEN/UPINC.  
Table 6-1 USB clock and register settings  
  UCSEL UPLLEN  UPINC 
When using the 48 MHz main clock  
  0  0  - 
When using the PLL macro   
oscillation clock  Main clock oscillation input
 
1  1  0 
Setting disabled  
1  1  1 
 
⋅  Standby mode and the PLL oscil lation stabilization wait counter 
If the mode changes to TIMER/STOP mode while waiting for the PLL oscillation to stabilize, PLL stops 
and the stabilization wait counter is cleared.  
⋅   Setting the USB enable bit and USB controller  
To use the USB controller, e nable the USB enable bit. Supply the USB operating clock to the USB 
controller before enabling the USB enable bit. For details on USB controller settings, see Chapters 
"USB Function" and "USB Host".  
 
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1. Overview of USB Function 
 
Chapter: USB Function 
This chapter explains the USB function. 
 
1.
 Overview of USB Function 
2. Configuration of USB Function 
3. Operations of USB Function 
4. Examples of USB Function Setting Procedures 
5. USB Function Registers 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FW03F-E18.1 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
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1. Overview of USB Function 
 
1.  Overview of USB Function 
The USB function is an interface supporting the USB (Universal Serial Bus) communication 
protocol.It supports full-speed transfer mode (12 Mbps), and has the following features. 
1.1.  Features of USB function 
  Full-speed (12 Mbps) transfer supported. 
   Auto answered device status. 
   Automatic generation and check of bit stripping, bit stuffing, CRC5, and CRC16. 
   Toggle check by data synchronization bit. 
   Auto-answer to standard all commands other than the Get/SetDescriptor and SynchFrame   
(these three commands can be processed similarly as class vendor commands). 
   The class vendor commands can be received as data and responded by firmware. 
   Up to 6 Endpoints supported. (Endpoint 0 is fixed to control transfer) 
   Each Endpoint includes 2 buffers for data transfer.   
(Endpoint 0 includes each buffer exclus ively for IN and OUT directions) 
   Automatic data transfer via DMA supported (except Endpoint 0 buffers). 
 
 
Set th

e base clock (HCLK) to 13 MHz or higher when using the USB function. 
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  20-2: USB Function 
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