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Fujitsu Series 3 Manual

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6. Registers 
 
6.4.  Software Watchdog Timer Clear Register (WdogIntClr) 
WdogIntClr register clears the software watchdog timer. 
 Register configuration 
bit  31         0 
Field WdogIntClr 
Attribute R/W 
Initial value  0xxxxxxxxx 
 
  Register function 
[bit31:0] WdogIntClr : clear bit 
bit31:0 Explanation 
In case of reading  An undefined bit is read. 
In case of writing Writing an arbitrary value 

  Clears an interrupt of the watchdog timer, if an interrupt of the watchdog 
timer is generated. 
   Reloads the set value from WdogLoad register to the watchdog timer 
counter. 
 
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6. Registers 
 
6.5.  Software Watchdog Timer Interrupt Status Register (WdogRIS) 
WdogRIS register shows the status of the software watchdog timer. 
 Register configuration 
bit  7       1 0 
Field Reserved  RIS 
Attribute -  R 
Initial value - 1’b0 
 
  Register function 
[bit7:1] res : Reserved bits 
0b0000000 is read from these registers. 
In case of writing, set 0b0000000. 
[bit0] RIS : Software watchdog interrupt status bit 
bit Explanation 
In case of writing  No effect. 
In case of reading 0  A watchdog interrupt is not generated. 
In case of reading 1 A watchdog interrupt is generated. 
 
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6. Registers 
 
6.6.  Software Watchdog Timer Lock Register (WdogLock) 
WdogLock register controls accesses of all the registers of software watchdog timer. 
 Register configuration 
bit  31         0 
Field WdogLock 
Attribute R/W 
Initial value  0x00000000 
 
  Register function 
[bit31:0] WdogLock : Software watchdog lock register 
bit31:0 Explanation 
In case of writing  Writing 0x1ACCE551: 
    Releases locks of all the registers of software watchdog timer. 
Writing other than 0x1ACCE551: 
    Lock function for all of the software watchdog timer registers will be   
  enabled. 
In case of reading 
0x00000000 : The lo
cks are released. 
0x00000001 : The locks are not released. 
 
 
  Lock for in itial v

alues are not enabled. Enable lock fu nction after the soft
 ware watchdog timer is started. 
   After lock is released, the clear regi ster (WdogIntClr) will become accessible. 
   After accessed the clear register (WdogI ntClr), lock will not be automatically enabled. Incorporate lock 
release -> clear -> lock enable for any clear sequence. 
   If locks are not released, reading is enabled and the va lues in each register can be read by accessing each 
register of the software wa tchdog. Writing is disabled. 
 
 
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6. Registers 
 
6.7.  Hardware Watchdog Timer Load Register (WDG_LDR) 
WDG_LDR register sets the cycle of hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_LDR 
Attribute R/W 
Initial value  0x0000FFFF 
 
  Register function 
[bit31:0] WDG_LDR : Interval cycle setting bit 
bit31:0 Explanation 
In case of writing  Sets cycle of the hardware watchdog. 
The initial value is 0x0000FFFF. 
The minimum value of writing is 1. 
An interrupt is generated after 0 is written. 
In case of reading 
A set value can be read. The initial value 0x0000FFFF is read. 
 
 
  During watchdo g ti

mer operation, if the value of WDG_LDR is modified, the value of WDG_LDR will 
be reflected to  th

e timer counter and counting is continued. 
   During the watchdog timer is halting, if the valu e of WDG_LDR is modified, the value of WDG_LDR 
will be reflected to the timer counter at activation of the watchdog timer. 
   The case of modifying the WDG_LDR register when  the watchdog timer interrupt was occurred, the 
watchdog timer interrupt is cleared. 
   This register can not be cleared by a software reset or a software watchdog reset. 
 
 
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6. Registers 
 
6.8.  Hardware Watchdog Timer Value Register (WDG_VLR) 
WDG_VLR register can read the current counter value of the hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_VLR 
Attribute R 
Initial value  0xxxxxxxx 
 
  Register function 
[bit31:0] WDG_VLR : Counter value bit 
bit31:0 Explanation 
In case of reading  The current count value of the watchdog counter can be read. 
By turning on the power, the hardware watchdog automatically activates, 
therefore decrementing is 
already started at the time of reading. The value 
after power on or the value decremented from the initial value 
0x0000FFFF is read. 
In case of writing  No effect. 
 
 
  This regi st

er can not be cleared by soft ware reset or s
 oftware watchdog reset. 
   Reading a correct value of this regi ster is possible only if the watchdog timer stops at tool break. See 
Debug Break Watchdog Timer Control Register in the chapter of Clock for the setting of watchdog 
timer at tool break. Except during  tool break, an inaccurate value may be read due to asynchronous 
reading for the bus clock. In this case, a countermeasur e is necessary such as comparing read values after 
reading it twice. 
 
 
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6. Registers 
 
6.9.  Hardware Watchdog Timer Control Register (WDG_CTL) 
WDG_CTL register sets enable/disable of the hardware watchdog timer. 
 Register configuration 
bit  7      2 1  0 
Field Reserved  RESEN INTEN
Attribute -  R/W R/W 
Initial value  - 1’b1 1’b1 
 
  Register function 
[bit7:2] res : Reserved bits 
0b000000 is read from these bits. 
In case of writing, set these bits to 0b000000. 
[bit1] RESEN : Hardware wa tchdog timer reset enable bit 
bit Explanation 
In case of reading  A value of register is read. 
In case of writing 0  A watchdog reset is disabled. 
In case of writing 1  A watchdog reset is enabled. 
 
[bit0] INTEN : Hardware watchdog interrupt and counter enable bit 
bit Explanation 
In case of reading  The value of the register is read. 
In case of writing 0  A watchdog interrupt is disabled. 
A watchdog counter is disabled. 
In case of writing 1 A watchdog interrupt is enabled. 
A watchdog counter is enabled. 
 
 
  Writin g 0

 to INTEN stops the watchdog counter.  When writing 1 again
 , the watchdog counter 
reloads the cycle value from WDG_LDR, and continues counting. 
   The watchdog timer can be activated by enabling IN TEN only. The watchdog timer is not activated by 
enabling RESEN only. To activate the watc hdog timer, INTEN should be enabled. 
   To access this register, it is required to write 0x1ACCE551 to the lock regi ster, and also write the 
reversal value 0xE5331A AE to release lock. 
   This register cannot be cleared by a software reset or a software watchdog reset 
   Writing 0 to INTEN clears the interrupt flag in  hardware watchdog interrupt status register 
(WDG_RIS). 
 
 
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6. Registers 
 
6.10.  Hardware Watchdog Timer Clear Register (WDG_ICL) 
WDG_ICL register clears the hardware watchdog timer. 
 Register configuration 
bit  7         0 
Field WDG_ICL 
Attribute R/W 
Initial value  0xxx 
 
  Register function 
[bit7:0] WDG_ICL : clear bit 
bit7:0 Explanation 
In case of reading  Undefined value is read. 
In case of writing Writing an arbitrary 8-bit value, and then write a reversal value of the 
arbitrary value, 

  Clears an interrupt, if an interrupt of watchdog timer is generated. 
   Reloads the set value from WDG_LDR register to the watchdog timer 
counter. 
 
 
This r e

gister cannot be cleared by a software reset or a software watchdog reset. 
  
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6. Registers 
 
6.11.  Hardware Watchdog Timer Interrupt Status Register (WDG_RIS) 
WDG_RIS register shows the status of the hardware watchdog timer. 
 Register configuration 
bit  7       1 0 
Field Reserved  RIS 
Attribute -  R 
Initial value - 1’b0 
 
  Register function 
[bit7:1] res : Reserved bits 
0b0000000 is read from these bits. 
In case of writing, set 0b0000000. 
[bit0] RIS : Hardware watchdog interrupt status bit 
bit Explanation 
In case of writing  No effect 
In case of reading 0    Hardware watchdog interrupt is not generated. 
In case of reading 1  Hardware watchdog interrupt is generated. 
 
 
This r e

gister cannot be cleared by a software reset or a software watchdog reset. 
  
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6. Registers 
 
6.12.  Hardware Watchdog Timer Lock Register (WDG_LCK) 
WDG_LCK register controls all the registers of the hardware watchdog timer. 
 Register configuration 
bit  31         0 
Field WDG_LCK 
Attribute    R/W    
Initial value     0x00000001    
 
  Register function 
[bit31:0] WDG_LCK : Hardware watchdog lock register 
bit31:0 Explanation 
In case of writing  In case of writing 0x1ACCE551: 
    The locks of all the registers other than the control register are released.
Later, in case of writing the re
versal value, 0xE5331AAE: 
    The locks of all the registers are released. 
In case of other procedure is performed or writing any value other than 
above: 
  No effect. 
In case of reading  0x00000000 : The lo
cks are released. 
0x00000001 : The locks are not released. 
 
 
  This r e

gister cannot be cleared by a software reset or a software watchdog reset. 
   In case of accessing to each register  of the 

hardware watchdog when the locks are not released, reading is 
enabled and the values of each register can be read. Writing is ignored. 
 
 
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7. Notes 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Watchdog timer 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  30  
7. Notes 
The section explains the notes when using the watchdog timer. 
  Hardware watchdog timer clear register 
To clear the hardware watchdog, write an arbitrary 8- bit value, and then write a reversal value of the 
arbitrary value. Clearing cannot be performed unles s the correct reversal value is written. Even if 
clearing is not performed, the  register is locked again. 
   Cooperation with a debug tool 
When a tool break is applied by a debug tool, to continue or stop of the counter of the watchdog timer 
can be set by setting of the register. See the chapter, Clock for details about the behavior of the 
watchdog timers during debugging. 
   Operation at standby mode 
Writing to a key register is required at setting of the standby mode to not to stop the watchdog timer for 
the case of the mode is transited to the standby mode because of an unintended program operation. 
See the chapter, Low-power Consumption Mode for more details. 
   Generation of a watchdog reset can be confirmed by the reset source register. See the section for Reset 
Source Register in the chapter, Reset for more details. 
 
   See the section for Interrupt Sour ce Register in the chapter Interrupt for an interrupt source. 
 
   Use a divided clock of APB clock for the count clock of the software watchdog. 
See the chapter, Clock for divided clock setting of the count clock. 
   Hardware watchdog and interrupt handler 
Before releasing the Lock for WDG_CTL (after re leasing the Lock for the register other than 
WDG_CTL), if an another interrupt becomes effective by the hardware watchdog and the interrupt 
handler begins its processing, the Lock releasing count could not be detected by hardware.   
So, at the beginning of the interrupt handler, write values in the WDG_LCK register to lock the register. 
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