Fujitsu Series 3 Manual
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3. Operations Explanation of operation modes 8-bit PPG operation mode One channel can operate as 8-bit PPG independently. 16-bit PPG operation mode Two channels are combined, and the comb ined channel operates as 16-bit PPG. 8+8-bit PPG operation mode In this mode, it needs two PPGs. One channel operates as an 8-bit prescaler. Another channel operates as 8-bit PPG timer. The borrow output of prescaler is counted, and allows 8-bit PPG pulse in any cycle. 16+16-bit PPG operation mode In this mode, it needs totally four PPGs. Two channels are combined, and combined channel operates as 16-bit prescaler. The other two channels are combined, and combined channel operates as 16-bit PPG timer. In this mode, the borrow output of the prescal er is counted, and allows 16-bit PPG pulse in any cycle. Relation between PPG channels and operation modes The PPG has an 8-bit Counter for each channel. In 16 -bit operation mode, two channels are combined and a 16-bit PPG is operated. The combination of 16-bit operation modes and PPG channel concatenation is defined on Ta b l e 3 - 1. Table 3-1 Combination of operation modes and PPG channel concatenation PPG channel 8-bit mode 8+8-bit mode 16-bit mode 16+16-bit mode PPG0 PPG0 PPG0 PPG1 PPG1 PPG0 prescaler PPG0 PPG0 PPG2 PPG2 PPG2 PPG3 PPG3 PPG2 prescaler PPG2 PPG0 prescaler PPG4 PPG4 PPG4 PPG5 PPG5 PPG4 prescaler PPG4 PPG4 PPG6 PPG6 PPG6 PPG7 PPG7 PPG6 prescaler PPG6 PPG4 prescaler PPG8 PPG8 PPG8 PPG9 PPG9 PPG8 prescaler PPG8 PPG8 PPG10 PPG10 PPG10 PPG11 PPG11 PPG10 prescaler PPG10 PPG8 prescaler PPG12 PPG12 PPG12 PPG13 PPG13 PPG12 prescaler PPG12 PPG12 PPG14 PPG14 PPG14 PPG15 PPG15 PPG14 prescaler PPG14 PPG12 prescaler FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 625 MB9Axxx/MB9Bxxx Series
3. Operations Selecting the count clock The count clocks to be used are PCLK clocks, and can be selected from one of the following four types of count clock inputs. The count clock operates as shown on Ta b l e 3 - 2. Table 3-2 Count clock selection PCS1 PCS0 Count clock operation 0 0 The Count Clock is counted for PCLK cycle. 0 1 The Count Clock is counted for 4 cycles of PCLK. 1 0 The Count Clock is counted for 16 cycles of PCLK. 1 1 The Count Clock is counted for 64 cycles of PCLK. Note: The period of the initial count may vary if the PPG is started when the prescaler is running and the PPG is halted in 8+8-bit PPG operation mode and 16+16-bit PPG operation mode. Control of pulse output When the PPG is halted, the LOW level pulse is output at default setting. The signal level inverting, including the initial signal level, can be specified by the REVC register. PPG startup conditions The following three PPG start tr igger modes can be selected. Start triggered by the Timing Generator Circuit Start triggered by GATE signal from the multifunction timer Start triggered by register writing Ta b l e 3 - 3 below defines the register settings and PPG start/stop conditions. Table 3-3 PPG start condition settings PPGC Register TTGR bit GATEC Register STGR bit PPG start/stop conditions 1 - Start triggered by the Timing Generator Circuit 0 1 Start triggered by GATE signal from the multifunction timer 0 0 Start triggered by TRG Register writing Start triggered by the Timing Generator Circuit The Timing Generator Circuit compares its built-in, 8-bit UP counter value with the 8-bit Compare register value, and generates/outputs a start trigger signal of PPG Timer when they match. The details are given in 3.2 Timing generator circuit operations . Start triggered b y GATE signal from the multifunction timer The PPG can be started and stopped by the GATE signal from the multifunction timer. Also, an effective startup period of PPG can be set by combination of EDGE bit of GATEC register and the GATE signal from the multifunction timer. Figure 3-2 shows an example of PPG startup by the GA TE signal from th e multifunction timer. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 626 MB9Axxx/MB9Bxxx Series
3. Operations Figure 3-2 An example of PPG operation by GATE signal from the multifunction timer GATE signal of multifunction timer PPG Count cycle StartStop PPG Count cycle Start Stop EDGE=0 (Start at rising edge, and stop at falling edge) PPG output GATE signal of multifunction timer PPG Count cycle Start Stop PPG Count cycle StartStop EDGE=1 (Start at falling edge, and stop at rising edge) PPG output 1. PPG continues output operation during the GATE signal is active. 2. After LOW level pulses for T x (L+1) count are output, HIGH level pulses for T x (H+1) count are output. 3. After HIGH level pulses are counted, LOW level pulses are counted again and output. The pulse output is continued when the GATE signal is active. 4. When the GATE signal is made inactive, PPG pulse output is stopped. Note: PPG startup at a rising e dge or a falling edge of GATE signal can be set by the EDGE bit. Start triggered by TRG register writing When the PEN bit TRG register (PPG start register) is set to 1 at each channel, the PPG is started and it starts pulse counting. The PPG stops counting when the PEN bit of each channel is set to 0. The details are shown in Figure 3-1. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 627 MB9Axxx/MB9Bxxx Series
3. Operations 3.2. Timing generator circuit operations The Timing generator circuit compares its built-in, 8-bit UP counter value with the 8-bit compare register value, and generates/outputs a start trigger signal of PPG Timer when they match. If a compare register is set for each PPG timer, multiple PPG timers can be synchronized and they can be started with a delay of each PPG start timing. A delay period can be set by the four compare registers relating to each PPG channel. The 8-bit UP counter value is entered in each comparator and wh en it matches the compare register value, each PPG start trigger signal is generated. Four channels of PPGs can be synchronized for a single timing generator, and those PPGs can be started with a delay. Four counter operation clocks (PCLK/2, PCLK/8, PCLK/32, and PCLK/64) can be selected. When the 8-bit UP counter is running, the MONI bit is read as 1. When stopped, the MONI bit is read as 0. The PPG starts when the STR bit of TTCR register (PPG start trigger cont rol register) is set to 1. The PPG stops when TRGnO=0 is set. Also, the counting stops if the UP counter overflows. Figure 3-3 gives an example of Timing Generator counting operation. Figure 3-3 An example of timing generator counting operation 8-bit up counter Count cycle MONI=1 Count starts if STR=1.Count stops if overflowed.Count starts if STR=1.Count stops if overflowed. Count cycle MONI=1 Counter overflow value 1. When TTCR.STR=1 is set, the 8-bit UP counter starts counting. 2. During counting, TTCR.MONI=1 is read. When counting is stopped, TTCR.MONI=0 is read. 3. If the 8-bit UP counter overflows, TTCR.STR=0 is set and the counting is stopped. 4. When TTCR.STR=1 is set again, the 8-bit UP counter starts counting. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 628 MB9Axxx/MB9Bxxx Series
3. Operations Figure 3-4 gives an example of Timing Generator compare startup. Figure 3-4 An example of timing generator compare startup 8-bit up counter Count cycle MONI=1 Count starts if STR=1. F0H A0H 80H 40H F0H A0H 80H 40H COMP6 COMP4 COMP2 COMP0 PPG6TG PPG4TG PPG2TG PPG0TG TRG0O=0, TRG2O=0 COMP0 matching COMP2 matching COMP4 matching COMP6 matching TRG4O=0, TRG6O=0 PPG0 output PPG2 output PPG4 output PPG6 output 1. When TTCR.STR=1 is set, the 8-bit UP counter starts counting. During counting, TTCR.MONI=1 is read. 2. If the 8-bit UP counter value matches the COMP0 value, the PPG0 trigger signal (PPG0TG) is made active. 3. If the 8-bit UP counter value matches the COMP2 value, the PPG2 trigger signal (PPG2TG) is made active. 4. If the 8-bit UP counter value matches the COMP4 value, the PPG4 trigger signal (PPG4TG) is made active. 5. If the 8-bit UP counter value matches the COMP6 value, the PPG6 trigger signal (PPG6TG) is made active. 6. If TTCR.TRG0O=0 and TTCR.TRG2O=0 are set, the PPG0 and PPG2 trigger signals are made inactive. 7. If TTCR.TRG4O=0 and TTCR.TRG6O=0 are set, the PPG4 and PPG6 trigger signals are made inactive. Notes: Figure 3-4 shows the operation for Timing Generator 0. Th e COMP Reg i ster value must be written before TTCR.STR=1 is set. In Figure 3-4 , when the counter value matches the COMP register value, PPG output starts the LOW pul ses. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 629 MB9Axxx/MB9Bxxx Series
4. Setup Procedure Example 4. Setup Procedure Example This section explains a setting procedure example of PPG. PPG function setup procedure (example) FUJITSU SEMICONDUCTOR LIMITED Sta r t Access to the PPGC register. Set an operation mode, interrupt, and clocks. Do you stop the PPG? GATEC.STRG=0 GATEC.STRG=1 End Timing Generator Circuit: Go to the Start Trigger Setting section (below). PPGC.TTRG=0 Register: Set a start trigger. PPGC.TTRG=1 Access to the GATEC register. Set a trigger and an effective level. Access to the PRLH/PRLL register. Set a PPG LOW/HIGH width. Access to the REVC register. Set an output level. Multifunction timer: Set a GA TE si gnal. Access to the TRG register. Enable PPG operation. (PENx=1) The PPG starts. (Operation) Ye s No Access to the TRG register. PPG operation stops. (PENx=0) Do you stop the multifunction timer? Start the multifunction timer. Activate the GATE signal. The PPG starts. (Operation) Ye s No An interrupt occurs (by settings). PPG operation stops. (System wait s for a GATE sign al.) End CHAPTER 16-2: PPG MN706-00002-1v0-E 630 MB9Axxx/MB9Bxxx Series
4. Setup Procedure Example Timing generator circuit setup procedure (example) FUJITSU SEMICONDUCTOR LIMITED Do you stop the PPG? Timing Generator Circuit: Set a start tri gger. Access to the TTCR register. Set a Compare clock. End Access to the COMP register. Set a Compare Register value. Ye s TTCR.MONI=0? No Access to the TTCR register. Enable PPG operation. (STR=1) The PPG starts. (Operation) Ye s No Access to the TTCR register. Stop the PPG start trigger. (TRGnO=0) Access to the TTCR register. Read the MONI bit. Ye s TTCR.MONI=0? No Access to the TTCR register. Read the MONI bit. Ye sDo you start the PPG again? No CHAPTER 16-2: PPG MN706-00002-1v0-E 631 MB9Axxx/MB9Bxxx Series
5. Registers 5. Registers This section explain the registers of PPG. Ta b l e 5 - 1 lists and explains PPG Registers. Table 5-1 PPG Register list Abbreviation Register name See TTCR0 PPG Start Trigger Control Register 0 5.1 TTCR1 PPG Start Trigger Control Register 1 5.2 COMP0 PPG Compare Register 0 COMP1 PPG Compare Register 1 COMP2 PPG Compare Register 2 COMP3 PPG Compare Register 3 COMP4 PPG Compare Register 4 COMP5 PPG Compare Register 5 COMP6 PPG Compare Register 6 COMP7 PPG Compare Register 7 5.3 TRG PPG Start Register 5.4 REVC Output Reverse Register 5.5 PPGC0 PPG Operation Mode Control Register 0 PPGC1 PPG Operation Mode Control Register 1 PPGC2 PPG Operation Mode Control Register 2 PPGC3 PPG Operation Mode Control Register 3 PPGC4 PPG Operation Mode Control Register 4 PPGC5 PPG Operation Mode Control Register 5 PPGC6 PPG Operation Mode Control Register 6 PPGC7 PPG Operation Mode Control Register 7 PPGC8 PPG Operation Mode Control Register 8 PPGC9 PPG Operation Mode Control Register 9 PPGC10 PPG Operation Mode Control Register 10 PPGC11 PPG Operation Mode Control Register 11 PPGC12 PPG Operation Mode Control Register 12 PPGC13 PPG Operation Mode Control Register 13 PPGC14 PPG Operation Mode Control Register 14 PPGC15 PPG Operation Mode Control Register 15 5.6 PRLH0 PPG Reload Register H0 PRLL0 PPG Reload Register L0 PRLH1 PPG Reload Register H1 PRLL1 PPG Reload Register L1 PRLH2 PPG Reload Register H2 PRLL2 PPG Reload Register L2 5.7 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 632 MB9Axxx/MB9Bxxx Series
5. Registers Abbreviation Register name See PRLH3 PPG Reload Register H3 PRLL3 PPG Reload Register L3 PRLH4 PPG Reload Register H4 PRLL4 PPG Reload Register L4 PRLH5 PPG Reload Register H5 PRLL5 PPG Reload Register L5 PRLH6 PPG Reload Register H6 PRLL6 PPG Reload Register L6 PRLH7 PPG Reload Register H7 PRLL7 PPG Reload Register L7 PRLH8 PPG Reload Register H8 PRLL8 PPG Reload Register L8 PRLH9 PPG Reload Register H9 PRLL9 PPG Reload Register L9 PRLH10 PPG Reload Register H10 PRLL10 PPG Reload Register L10 PRLH11 PPG Reload Register H11 PRLL11 PPG Reload Register L11 PRLH12 PPG Reload Register H12 PRLL12 PPG Reload Register L12 PRLH13 PPG Reload Register H13 PRLL13 PPG Reload Register L13 PRLH14 PPG Reload Register H14 PRLL14 PPG Reload Register L14 PRLH15 PPG Reload Register H15 PRLL15 PPG Reload Register L15 5.7 GATEC0 Gate Function Control Register 0 GATEC4 Gate Function Control Register 4 GATEC8 Gate Function Control Register 8 GATEC12 Gate Function Control Register 12 5.8 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 633 MB9Axxx/MB9Bxxx Series
5. Registers
5.1. PPG Start Trigger Control Register 0 (TTCR0)
The TTCR0 Register controls a start of PPG0/PPG2/PPG4/PPG6 Register.
Register configuration
Bit 15 14 13 12 11 10 9 8
Field TRG6O TRG4O TRG2O TRG0O CS01 CS00 MONI0 STR0
Attribute R/W R/W R/W R/W R/W R/W R R/W
Initial value 1b1 1b1 1b1 1b1 1b0 1b0 1b0 1b0
Bit 7 6 5 4 3 2 1 0
Field Reserved
Attribute -
Initial value -
Register functions
[Bits 15:12] TRG6O, TRG4O, TRG2O, TRG0O: PPG trigger stop bits
These bits control the PPG start trigger signal.
Bits 15:12 Function
Read 1 is always read.
Writing by 0 Disables the PPG start trigger signal. (LOW output)
Writing by 1 No effect
[Bit 11:10] CS01, CS00: Count clo ck select bits of UP counter comparing built-in compare register.
These bits set an operation clock of UP counter.
Bit 11 Bit 10 Function
0 0 PCLK/2 [Initial value]
0 1 PCLK/8
1 0 PCLK/32
1 1 PCLK/64
[Bit 9] MONI0: 8-bit UP counter operation state monitor bit This bit indicates the PPGs 8-bit UP counter operation state.
Bit Function
Reading as 0 The PPG UP counter is stopped. [Initial value]
Reading as 1 The PPG UP counter is operating.
During writing No effect
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 16-2: PPG
MN706-00002-1v0-E
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MB9Axxx/MB9Bxxx Series