Fujitsu Series 3 Manual
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![Page 1322
3. Operation
3.2.4. Error reply
The following explains the error reply.
When an access to an invalid address occurs, the external bus interface outputs an error reply (by setting
HRESP[1:0] to 01). When this erro r occurs during a burst transfer, operation of the external bus interface
is not guaranteed.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 23: External Bus Interface
MN706-00002-1v0-E
1286
MB9Axxx/MB9Bxxx Series](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1321.png "Page 1322
3. Operation
3.2.4. Error reply
The following explains the error reply.
When an access to an invalid address occurs, the external bus interface outputs an error reply (by setting
HRESP[1:0] to 01). When this erro r occurs during a burst transfer, operation of the external bus interface
is not guaranteed.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 23: External Bus Interface
MN706-00002-1v0-E
1286
MB9Axxx/MB9Bxxx Series")
![Page 1324
4. Example waveforms of external memory access
4.1. Word read access to 8-bit wide SRAM
Figure 4-1 shows waveforms of a word read access to 8-bit wide SRAM.
Figure 4-1 Waveforms of a word read access to 8-bit wide SRAM
DAT00DAT01DAT02 DAT03
00
01 02 03
MCSX [0]MWEX
MDQM [0] MOEX
MDATA [7:0] MAD [24:0] 0
Read address setup
*
Read access cycle
1 2 3 4 5 6 7 8 9 10111213141516171819
***
* On or Off possible
Read address cycle
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 23: External Bus...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1323.png "Page 1324
4. Example waveforms of external memory access
4.1. Word read access to 8-bit wide SRAM
Figure 4-1 shows waveforms of a word read access to 8-bit wide SRAM.
Figure 4-1 Waveforms of a word read access to 8-bit wide SRAM
DAT00DAT01DAT02 DAT03
00
01 02 03
MCSX [0]MWEX
MDQM [0] MOEX
MDATA [7:0] MAD [24:0] 0
Read address setup
*
Read access cycle
1 2 3 4 5 6 7 8 9 10111213141516171819
***
* On or Off possible
Read address cycle
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 23: External Bus...")
![Page 1325
4. Example waveforms of external memory access
4.2. Serial word write/read access to 16-bit wide SRAM
Figure 4-2 shows waveforms of a serial word write/read access to 16-bit wide SRAM.
Figure 4-2 Waveforms of a serial word write/read access to 16-bit wide SRAM
MAD [25:0] 0002
DAT00 DAT02 00
02
DAT00 DAT02
Write address
setup cycleWrite enable cycle*
Write idle cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
MCSX [0]
MDQM [0]
MWEX
MOEX
MDATA [15:0]
Write access cycle
* ON or OFF...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1324.png "Page 1325
4. Example waveforms of external memory access
4.2. Serial word write/read access to 16-bit wide SRAM
Figure 4-2 shows waveforms of a serial word write/read access to 16-bit wide SRAM.
Figure 4-2 Waveforms of a serial word write/read access to 16-bit wide SRAM
MAD [25:0] 0002
DAT00 DAT02 00
02
DAT00 DAT02
Write address
setup cycleWrite enable cycle*
Write idle cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
MCSX [0]
MDQM [0]
MWEX
MOEX
MDATA [15:0]
Write access cycle
* ON or OFF...")
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4. Example waveforms of external memory access
4.3. Issue of an 8-bit NAND flash memory read/write command
Figure 4-3 shows waveforms of the issue of an 8-bit wide NAND flash memory read/write
command (byte access).
Figure 4-3 Waveforms of the issue of an 8-bit NAND flash memory read/write command
RD or WT
Base+0x1000
Base+0x2000
Base+0x2000 Base+0x2000 Base+0x2000
ROW2
ROW0
COL
MNCLE
MNALE
MNWEX
R/B (NAND
FLASH pin)
ROW1
0
MNREX
MDATA [7:0]
MAD [23:0] MCSX [0]
NAND mode ON...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1325.png "Page 1326
4. Example waveforms of external memory access
4.3. Issue of an 8-bit NAND flash memory read/write command
Figure 4-3 shows waveforms of the issue of an 8-bit wide NAND flash memory read/write
command (byte access).
Figure 4-3 Waveforms of the issue of an 8-bit NAND flash memory read/write command
RD or WT
Base+0x1000
Base+0x2000
Base+0x2000 Base+0x2000 Base+0x2000
ROW2
ROW0
COL
MNCLE
MNALE
MNWEX
R/B (NAND
FLASH pin)
ROW1
0
MNREX
MDATA [7:0]
MAD [23:0] MCSX [0]
NAND mode ON...")
3. Operation 3.2.3. Auto block erase access Figure 3-3 shows the flowchart of the auto block erase access. Figure 3-3 Auto block erase access FUJITSU SEMICONDUCTOR LIMITED Y End auto block erase Issue a status read command 0x70 (Base+0x1000) Status read (Base+0x0000) Status = OK? N Turn NAND mode ON Issue an erase start command 0xd0 (Base+0x1000) Issue an address (Base+0x2000) Issue an auto block erase setting command 0x60 (Base+0x1000) The corresponding chip select signal is fixed to L. MNCLE is asserted/de-asserted. MNALE is asserted. MNALE is de-asserted. Access to another device (SRAM) is enabled during this period (for several ms). As shown in the above fl owchart, access to another me mory device is possible even in the stage where the process of accessing NAND flash memory has not finish ed. Because DMA can also be used for reading and writing data, the processor can access the NAND flash memory with minimum instructions. CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1285 MB9Axxx/MB9Bxxx Series
3. Operation 3.2.4. Error reply The following explains the error reply. When an access to an invalid address occurs, the external bus interface outputs an error reply (by setting HRESP[1:0] to 01). When this erro r occurs during a burst transfer, operation of the external bus interface is not guaranteed. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1286 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4. Example waveforms of external memory access This section provides waveforms of external memory access by the external bus interface. 4.1 Word read access to 8-bit wide SRAM 4.2 Serial word write/read acce ss to 16-bit wide SRAM 4.3 Issue of a n 8-bit NAND flash memory read/write command 4.4 8-bit NAND flash memory status read 4.5 8-bit NAND flash memory data write 4.6 16-bit NOR flash memory page read FUJITSU SEMICON DUCT OR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1287 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4.1. Word read access to 8-bit wide SRAM Figure 4-1 shows waveforms of a word read access to 8-bit wide SRAM. Figure 4-1 Waveforms of a word read access to 8-bit wide SRAM DAT00DAT01DAT02 DAT03 00 01 02 03 MCSX [0]MWEX MDQM [0] MOEX MDATA [7:0] MAD [24:0] 0 Read address setup * Read access cycle 1 2 3 4 5 6 7 8 9 10111213141516171819 *** * On or Off possible Read address cycle FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1288 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4.2. Serial word write/read access to 16-bit wide SRAM Figure 4-2 shows waveforms of a serial word write/read access to 16-bit wide SRAM. Figure 4-2 Waveforms of a serial word write/read access to 16-bit wide SRAM MAD [25:0] 0002 DAT00 DAT02 00 02 DAT00 DAT02 Write address setup cycleWrite enable cycle* Write idle cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MCSX [0] MDQM [0] MWEX MOEX MDATA [15:0] Write access cycle * ON or OFF possible FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1289 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4.3. Issue of an 8-bit NAND flash memory read/write command Figure 4-3 shows waveforms of the issue of an 8-bit wide NAND flash memory read/write command (byte access). Figure 4-3 Waveforms of the issue of an 8-bit NAND flash memory read/write command RD or WT Base+0x1000 Base+0x2000 Base+0x2000 Base+0x2000 Base+0x2000 ROW2 ROW0 COL MNCLE MNALE MNWEX R/B (NAND FLASH pin) ROW1 0 MNREX MDATA [7:0] MAD [23:0] MCSX [0] NAND mode ON 12345678910111213141516171819 Issue of a read or write command Address write (Write access cycle) Write enable cycle (Write access cycle) (Write access cycle) (W rite access cycle) (Write access cycle) Write access setup cycle FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1290 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4.4. 8-bit NAND flash memory status read Figure 4-4 shows waveforms of an 8-bit NAND flash memory status read (byte access). Figure 4-4 Waveforms of an 8-bit NAND flash memory status read R/B (NAND FLASH pin) Ready MNREX MNWEX MDATA [7:0] StatusRD BusyBusy Base+1000 Base+0x0000 MNCLE MNALE MAD [23:0] MCSX [0] 0123456789 10 111213141516171819 Issue a status read command Status read Status read Status read Write access cycle Read access cycle Read address cycleRead address setup cycle (0) Write access setup cycle Write enable cycle FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1291 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access 4.5. 8-bit NAND flash memory data write Figure 4-5 shows waveforms of an 8-bit NAND flash memory data write. Figure 4-5 8-bit NAND flash memory data write 012345678910111213141516171819 Dat1 Base+0x0000 ROW1 Dat0 ROW2 Base+0x2000 Dat3 Dat2 MNREX MNWEX R/B (NAND FLASH pin) MDATA [7:0] MAD [23:0] MCSX [0] MNCLE MNALE Address write (write address)Data write Data write Data write Data write Write access cycle Write access cycle Write enable cycle Write address setup cycleWrite address setup cycle Write enable cycle FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1292 MB9Axxx/MB9Bxxx Series
4. Example waveforms of external memory access
4.6. 16-bit NOR flash memory page read
Figure 4-6 shows waveforms of a 16-bit NOR flash memory page read.
Figure 4-6 Waveforms of a 16-bit NOR flash memory page read
MCSX [0]
DAT00 DAT02 DAT04 DAT06
00 02 12 DAT08 DAT10 DAT12
04 06 08 10
MOEX MDATA [15:0]
MAD [25:0] 14
1st Read address cycle
Read access cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
FUJITSU SEMICONDUCT
OR LIMITED
CHAPTER 23: External Bus Interface
MN706-00002-1v0-E
1293
MB9Axxx/MB9Bxxx Series
5. Endianness and Valid Byte Lanes 5. Endianness and Valid Byte Lanes The external bus interface supports little endian. Ta b l e 5 - 1 shows correspondence between endian and valid byte lanes. Table 5-1 Endianness and valid byte lanes Endianness Access size Target width Internal bus address Valid byte lane Correspondent internal bus data MDQM [1:0] MAD [1:0] 1st: H*DATA[7:0] 0b00 2nd: H*DATA[15:8] 0b01 3rd: H*DATA[23:16] 0b10 8 bits 0 MDATA[7:0] 4 th: H*DATA[31:24] 0b10 0b11 MDATA[15:0] 1st: H*DATA[15:0] 0b00 Wo r d 16 bits 0 MDATA[15:0] 2 nd: H*DATA[31:16] 0b00 0b10 1st: H*DATA[7:0] 0b000 MDATA[7:0] 2 nd: H*DATA[15:8] 0b10 0b01 1st: H*DATA[23:16] 0b10 8 bits 2 MDATA[7:0] 2 nd: H*DATA[31:24] 0b10 0b11 0 MDATA[15:0] H*DATA[15:0] 0b00 0b00 Half word 16 bits 2 MDATA[15:0] H*DATA[31:16] 0b00 0b10 0 MDATA[7:0] H*DATA[7:0] 0b10 0b00 1 MDATA[7:0] H*DATA[15:8] 0b10 0b01 2 MDATA[7:0] H*DATA[23:16] 0b10 0b10 8 bits 3 MDATA[7:0] H*DATA[31:24] 0b10 0b11 0 MDATA[7:0] H*DATA[7:0] 0b10 0b00 1 MDATA[15:8] H*DATA[15:8] 0b01 0b00 2 MDATA[7:0] H*DATA[23:16] 0b10 0b10 Little endian Byte 16 bits 3 MDATA[15:8] H*DATA[31:24] 0b01 0b10 H*DATA: AHB I/O data FUJITSU SEMICONDUCTOR LIMITED CHAPTER 23: External Bus Interface MN706-00002-1v0-E 1294 MB9Axxx/MB9Bxxx Series