Fujitsu Series 3 Manual
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![Page 706
4. Registers
4.4. QPRC Position and Revolution Counter Compare Register (QPRCR)
The QPRC Position and Revolution Counter Compare Register (QPRCR) is used to compare
with the selected count value of the position or revolution counter.
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field QPRCR[15:0]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial
value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[bit 15:0] QPRCR: Select whether to compare with the count value of the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-705.png "Page 706
4. Registers
4.4. QPRC Position and Revolution Counter Compare Register (QPRCR)
The QPRC Position and Revolution Counter Compare Register (QPRCR) is used to compare
with the selected count value of the position or revolution counter.
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field QPRCR[15:0]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial
value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[bit 15:0] QPRCR: Select whether to compare with the count value of the...")
![Page 707
4. Registers
4.5. QPRC Control Register (QCR)
The QPRC Control Register (QCR) is used to specify the operation mode of the position
counter or 16-bit revolution counter. It is also used to start or stop each counter.
Low-Order Bytes of QPRC Control Register (QCRL)
bit 7 6 5 4 3 2 1 0
Field SWAP RSEL CGSC PSTP RCM1 RCM0 PCM1 PCM0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] SWAP: Swap bit This bit is used to swap the connections of th e AIN input...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-706.png "Page 707
4. Registers
4.5. QPRC Control Register (QCR)
The QPRC Control Register (QCR) is used to specify the operation mode of the position
counter or 16-bit revolution counter. It is also used to start or stop each counter.
Low-Order Bytes of QPRC Control Register (QCRL)
bit 7 6 5 4 3 2 1 0
Field SWAP RSEL CGSC PSTP RCM1 RCM0 PCM1 PCM0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] SWAP: Swap bit This bit is used to swap the connections of th e AIN input...")
![Page 708
4. Registers
[bit 5] CGSC: Count clear or gate selection bit This bit is used to select the function of the ZIN external pin.
When the counter clear function is enabled (QGSC=0), the ZIN pin clears the position counter if the
revolution count mode is set to RC_Mode0 (RCM[1:0]=00), RC_Mode1 (RCM[1:0]=01), or
RC_Mode3 (RCM[1:0]=11). The CGE1 and CGE0 bits of the QCR register clear the position counter by
selecting a valid edge of the ZIN pin and detecting the selected edge.
When the gate...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-707.png "Page 708
4. Registers
[bit 5] CGSC: Count clear or gate selection bit This bit is used to select the function of the ZIN external pin.
When the counter clear function is enabled (QGSC=0), the ZIN pin clears the position counter if the
revolution count mode is set to RC_Mode0 (RCM[1:0]=00), RC_Mode1 (RCM[1:0]=01), or
RC_Mode3 (RCM[1:0]=11). The CGE1 and CGE0 bits of the QCR register clear the position counter by
selecting a valid edge of the ZIN pin and detecting the selected edge.
When the gate...")
![Page 709
4. Registers
[bit 1:0] PCM1, PCM0: Position counter mode bits These bits are used to select the count mode of the position counter.
bit1 bit0 Description
0 0 Disables the position counter (PC_Mode0) to stop it.
0 1 Up-down count mode (PC_Mode1)
Increments the value with an AIN active edge and decrements it with a BIN
active edge.
1
0 Phase difference count mode (PC_Mode2)
Counts up if AIN is leading BIN and down if BIN is leading AIN.
1 1 Directional count mode (PC_Mode3)
Counts up or...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-708.png "Page 709
4. Registers
[bit 1:0] PCM1, PCM0: Position counter mode bits These bits are used to select the count mode of the position counter.
bit1 bit0 Description
0 0 Disables the position counter (PC_Mode0) to stop it.
0 1 Up-down count mode (PC_Mode1)
Increments the value with an AIN active edge and decrements it with a BIN
active edge.
1
0 Phase difference count mode (PC_Mode2)
Counts up if AIN is leading BIN and down if BIN is leading AIN.
1 1 Directional count mode (PC_Mode3)
Counts up or...")
![Page 710
4. Registers
High-Order Bytes of QPRC Control Register (QCRH)
bit 15 14 13 12 11 10 9 8
Field CGE1 CGE0 BES1 BES0 AES1 AES0 PCRM1 PCRM0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 15:14] CGE1, CGE0: Detection edge selection bits These bits are used to select the detection edge when the ZIN external pin is used for the counter clear
function (CGSC=0). They are also used to select the detection level when the ZIN external pin is used for
the gate...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-709.png "Page 710
4. Registers
High-Order Bytes of QPRC Control Register (QCRH)
bit 15 14 13 12 11 10 9 8
Field CGE1 CGE0 BES1 BES0 AES1 AES0 PCRM1 PCRM0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 15:14] CGE1, CGE0: Detection edge selection bits These bits are used to select the detection edge when the ZIN external pin is used for the counter clear
function (CGSC=0). They are also used to select the detection level when the ZIN external pin is used for
the gate...")
![Page 711
4. Registers
[bit 9:8] PCRM1, PCRM0: Position counter reset mask bits These bits are used to specify the period (mask time) to ignore the events shown below after detecting a
position counter overflow or underflow or detecting a ZIN active edge.
Position counter resetting
Revolution counter increment or decrement
This mask function is released when the count direc tion of the position counter is changed, and restarts
when a position counter overflow or underflow is detected or a ZIN...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-710.png "Page 711
4. Registers
[bit 9:8] PCRM1, PCRM0: Position counter reset mask bits These bits are used to specify the period (mask time) to ignore the events shown below after detecting a
position counter overflow or underflow or detecting a ZIN active edge.
Position counter resetting
Revolution counter increment or decrement
This mask function is released when the count direc tion of the position counter is changed, and restarts
when a position counter overflow or underflow is detected or a ZIN...")
![Page 713
4. Registers
[bit 0] ORNGMD: Outrange mode selection bit This bit defines the outrange mode of the revolution counter.
Bit Description
0 Selects a positive number (in the range from 0x0000 to 0xFFFF).
1 Selects the 8K value (in the range from 0x0000 to 0x7FFFF).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17: Quad Position & Revolution Counter
MN706-00002-1v0-E
677
MB9Axxx/MB9Bxxx Series](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-712.png "Page 713
4. Registers
[bit 0] ORNGMD: Outrange mode selection bit This bit defines the outrange mode of the revolution counter.
Bit Description
0 Selects a positive number (in the range from 0x0000 to 0xFFFF).
1 Selects the 8K value (in the range from 0x0000 to 0x7FFFF).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 17: Quad Position & Revolution Counter
MN706-00002-1v0-E
677
MB9Axxx/MB9Bxxx Series")
![Page 714
4. Registers
4.7. Low-Order Bytes of QPRC Interrupt Control Register
(QICRL)
The Low-Order Bytes of QPRC Interrupt Contro l Register (QICRL) are used to control a
position counter overflow or underflow interrupt, zero index interrupt, QPRC positio\
n counter
comparison match interrupt, or QPRC position and revolution counter comparison match
interrupt.
bit 7 6 5 4 3 2 1 0
Field ZIIF OFDF UFDF OUZIEQPRCMFQPRCMIE QPCMF QPCMIE
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-713.png "Page 714
4. Registers
4.7. Low-Order Bytes of QPRC Interrupt Control Register
(QICRL)
The Low-Order Bytes of QPRC Interrupt Contro l Register (QICRL) are used to control a
position counter overflow or underflow interrupt, zero index interrupt, QPRC positio\
n counter
comparison match interrupt, or QPRC position and revolution counter comparison match
interrupt.
bit 7 6 5 4 3 2 1 0
Field ZIIF OFDF UFDF OUZIEQPRCMFQPRCMIE QPCMF QPCMIE
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0...")
![Page 715
4. Registers
[bit 5] UFDF: Underflow interrupt request flag bit This flag indicates that a position counter underflow occurs. When the position counter is counted down,
this bit is set to 1 if the position counter is 0x0000.
This flag can only clear to 0 in write mode. Setting 1 has no effect.
1 is read by the read-modify-write access operation.
Description Bit Read Write
0 Detects no underflow. Clears this bit.
1 Detects underflow. No effect.
[bit 4] OUZIE: Overflow, underflow, or zero...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-714.png "Page 715
4. Registers
[bit 5] UFDF: Underflow interrupt request flag bit This flag indicates that a position counter underflow occurs. When the position counter is counted down,
this bit is set to 1 if the position counter is 0x0000.
This flag can only clear to 0 in write mode. Setting 1 has no effect.
1 is read by the read-modify-write access operation.
Description Bit Read Write
0 Detects no underflow. Clears this bit.
1 Detects underflow. No effect.
[bit 4] OUZIE: Overflow, underflow, or zero...")
![Page 716
4. Registers
If the register function selection bit (QCR:RSEL) is set to 0, the PC and
RC match interrupt request
flag bit (QPRCMF) is set to 1 immediately when the following one of conditions is satisfied.
The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or
PC_Mode3 (QCR:PCM[1:0]=11) when the pos ition counter is disabled (QCR:PCM[1:0]=00)
and the value of the position counter matches that of the QPRC Position and Revolution Counter
Compare Register...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-715.png "Page 716
4. Registers
If the register function selection bit (QCR:RSEL) is set to 0, the PC and
RC match interrupt request
flag bit (QPRCMF) is set to 1 immediately when the following one of conditions is satisfied.
The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or
PC_Mode3 (QCR:PCM[1:0]=11) when the pos ition counter is disabled (QCR:PCM[1:0]=00)
and the value of the position counter matches that of the QPRC Position and Revolution Counter
Compare Register...")
4. Registers [bit 9:8] PCRM1, PCRM0: Position counter reset mask bits These bits are used to specify the period (mask time) to ignore the events shown below after detecting a position counter overflow or underflow or detecting a ZIN active edge. Position counter resetting Revolution counter increment or decrement This mask function is released when the count direc tion of the position counter is changed, and restarts when a position counter overflow or underflow is detected or a ZIN active edge is detected. bit9 bit8 Description 0 0 No reset mask 0 1 The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes twice. 1 0 The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes four times. 1 1 The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes eight times. The posi t ion counter reset mask function is available only in RC_Mode0 (RCM[1:0]=00) and RC_Mo de3 (RCM[1:0]=11). This function operates regardless of the setting of the position counter mode (PC_Mode1, PC_Mode2, or PC_Mode3). While the position counter reset mask function is operating, the mask function is released and the position counter can be reset in the following conditions. When the position counter mode bit (PCM[1:0]) is changed When the revolution counter mode bit (RCM[1:0]) is changed When the direction of the position counter is changed FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 675 MB9Axxx/MB9Bxxx Series
4. Registers 4.6. QPRC Extension Control Register (QECR) The QPRC Extension Control Register (QECR) is used to select that the revolution counter is inside the count range, indicate that the revolution counter is outside the count range, or control whether or not to generate an interrupt when the revolution counter gets out of the range. bit 15 14 1312 11 10 98765432 1 0 Field Reserved ORNGIE ORNGF ORNGMD Attribute - - - - - - ------- R/W R/W R/W Initial value 0 0 0 0 0 0 00000000 0 0 [bit 15:3] Reserved bit Always write 0 to these bits. The read value is 0. [bit 2] ORNGIE: Outrange interrupt enable bit This bit is used to control whether or not to issue an interrupt notification to the CPU when the outrange interrupt request flag (ORNGF) is set to 1. When this b it is set to 1, an interrupt is generated if the value of the revolution counter gets out of the range (ORNGF=1). Bit Description 0 Interrupt disabled 1 Interrupt enabled [bit 1] ORNGF: Outrange interrupt request flag bit This flag indicates that the revolution counter is outside the count range. If a positive number is selected as the outrange mode of the revolution counter (ORNGMD=0), this flag is set to 1 when the revolution counter changes from 0x0001 to 0x0000 after counting down or when it changes from 0xFFFE to 0xFFFF after counting up. If the 8K value is selected as the outrange mode of the revolution counter (ORNGMD=1), this flag is set to 1 when the revolution counter changes from 0x8001 to 0x8000 after counting down or when it changes from 0x7FFE to 0x7FFF after counting up. This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Out of range is not detected. Clears this bit. 1 Out of range is detected. No effect. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 676 MB9Axxx/MB9Bxxx Series
4. Registers [bit 0] ORNGMD: Outrange mode selection bit This bit defines the outrange mode of the revolution counter. Bit Description 0 Selects a positive number (in the range from 0x0000 to 0xFFFF). 1 Selects the 8K value (in the range from 0x0000 to 0x7FFFF). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 677 MB9Axxx/MB9Bxxx Series
4. Registers 4.7. Low-Order Bytes of QPRC Interrupt Control Register (QICRL) The Low-Order Bytes of QPRC Interrupt Contro l Register (QICRL) are used to control a position counter overflow or underflow interrupt, zero index interrupt, QPRC positio\ n counter comparison match interrupt, or QPRC position and revolution counter comparison match interrupt. bit 7 6 5 4 3 2 1 0 Field ZIIF OFDF UFDF OUZIEQPRCMFQPRCMIE QPCMF QPCMIE Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 7] ZIIF: Zero index interrupt request flag bit This flag is set to 1 when the pos ition counter is reset by the ZIN input. This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no zero index. Clears this bit. 1 Detects zero index. No effect. The zero inde x in terrupt request flag bit (ZIIF) is not set to 1 even if ZIN is used as the gate function (QCR:CGSC=1) or the position counter is reset in RC_Mode2 (QCR:RCM[1:0]=10). [bit 6] OFDF: Overflow interrupt request flag bit This flag ind i cates that a position counter overflow occu rs. When the position counter is counted up, this bit is set to 1 if the value of the position counter matches that of the QPRC Maximum Position Register (QMPR). This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no overflow. Clears this bit. 1 Detects overflow. No effect. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 678 MB9Axxx/MB9Bxxx Series
4. Registers [bit 5] UFDF: Underflow interrupt request flag bit This flag indicates that a position counter underflow occurs. When the position counter is counted down, this bit is set to 1 if the position counter is 0x0000. This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no underflow. Clears this bit. 1 Detects underflow. No effect. [bit 4] OUZIE: Overflow, underflow, or zero index interrupt enable bit This bit is used to control whether or not to issue an interrupt notification to the CPU when the overflow interrupt request flag bit (OFDF), underflow interrupt request flag bit (UFDF), or zero index interrupt request flag bit (ZIIF) is set to 1. When this bit is set to 1, an interrupt is generated if overflow is detected (OFDF=1), underflow is detected (UFDF=1), or zero index is detected (ZIIF=1). Bit Description 0 Interrupt disabled 1 Interrupt enabled [bit 3] QPRCMF: PC and RC match interrupt request flag bit This flag indicates whether the value of the position counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) or the value of the revolution counter (QRCR) matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR). When the comparison between the position counter and QPRC Position and Revolution Counter Compare Register (QPRCR) is selected (QCR:RS EL=0), this flag is set to 1 if the value of the position counter matches that of the QPRC Position and Revol ution Counter Compare Register (QPRCR). When the comparison between the revolution counter and QPRC Position and Revolution Counter Compare Register (QPRCR) is selected (QCR:RS EL=1), this flag is set to 1 if the value of the revolution counter matches that of the QPRC Position and Revol ution Counter Compare Register (QPRCR). This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no comparison match with the QPRCR value. Clears this bit. 1 Detects a comparison match with the QPRCR value. No effect. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 679 MB9Axxx/MB9Bxxx Series
4. Registers If the register function selection bit (QCR:RSEL) is set to 0, the PC and RC match interrupt request flag bit (QPRCMF) is set to 1 immediately when the following one of conditions is satisfied. The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11) when the pos ition counter is disabled (QCR:PCM[1:0]=00) and the value of the position counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR). The value of the position counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) when data is writte n to the Quad Position & Revolution Counter Position Count Register (QPCR) or QPRC Pos ition and Revolution Counter Compare Register (QPRCR) in PC_Mode1 (QCR:PCM[1:0]=01 ), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11). If the register function selection bit (QCR:RSEL) is set to 1, the PC and RC match interrupt request flag bit (QPRCMF) is set to 1 immediately when the following condition is satisfied. The value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) by writing data to the QPRC Position and Revolution Counter Compare Register (QPRCR) when the mode is RC_Mode1 (QCR:RCM[1:0]=01), RC_Mode2 (QCR:RCM[1:0]=10), or RC_Mode3 (QCR:RCM[1:0]=11). The value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) by changing the mode from RC_Mode0 (QCR:RCM[1:0]=00) to another mode. If the register function selection bit (QCR:RSEL) is ch anged, the PC and RC match interrupt request flag bit (QPRCMF) is set to 1 immediately if the following one of conditions is satisfied. The value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) when the register function selection bit (QCR:RSEL) is changed from 0 to 1 in the mode other than RC_Mode0 (QCR.RCM[1:0]=00). The value of the position counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) when the register function selection bit (QCR:RSEL) is changed from 1 to 0 in the mode other than RC_Mode0 (QCR.RCM[1:0]=00). [bit 2] QPRCMIE: PC and RC match interrupt enable bit This bit is used to co ntrol whether or not to issue an interrupt notification to the CPU when the PC and RC match interrupt request flag (QPRCMF) is set to 1. When this bit is set to 1, an interrupt is generated if the value of the position or revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) (QPRCMF=1). Bit Description 0 Interrupt disabled 1 Interrupt enabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 680 MB9Axxx/MB9Bxxx Series
4. Registers [bit 1] QPCMF: PC match interrupt request flag bit This flag indicates whether or not the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR). This flag is set to 1 if the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR). This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no comparison match with the QPCCR value. Clears this bit. 1 Detects a comparison match with the QPCCR value. No effect. The PC m a tch interrupt request flag bit (QPCMF) is set to 1 immediately when the following one of conditions is satisfied. The mode i s changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11) when the positio n counter is disabled (QCR:PCM[1:0]=00) and the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR). The value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) by writing to the Quad Position & Revo lution Counter Position Count Register (QPCR) when the position counter stop bit (QCR:PSTP) is 1 and when the mode is PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11). The value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) by writing to the QPRC Position Counter Compare Register (QPCCR) when the mode is PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11). [bit 0] QPCMIE: PC match interrupt enable bit This bit is used to co ntrol whether or not to issue an interrupt notification to the CPU when the PC match interrupt request flag (QPCMF) is set to 1. When this bit is set to 1, an interrupt is generated if the value of the position counter matches that of the QPRC Position Counter Compare Re gister (QPCCR) (QPCMF=1). Bit Description 0 Interrupt disabled 1 Interrupt enabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 681 MB9Axxx/MB9Bxxx Series
4. Registers 4.8. High-Order Bytes of QPRC Interrupt Control Register (QICRH) The High-Order Bytes of QPRC Interrupt Control Register (QICRH) are used to control a match between the position counter and QPCCR, a match between the revolution counter and QPRCR, and a count inversion interrupt. They are also used to indicate the direction of the position counter when the last underflow or overflow interrupt was detected or the last value of the position counter was changed. bit 15 14 13 12 11 10 9 8 Field Reserved QPCNRCMFQPCN RCMIEDIROUDIRPC CDCF CDCIE Attribute - - R/W R/W R R R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 15:14] Reserved Always write 0 to these bits. The read value is 0. [bit 13] QPCNRCMF: PC match and RC match interrupt request flag bit This flag indicates whether or not the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) and the value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR). This flag is set to 1 when the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) (QPCMF= 1) and the value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR). This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Detects no match. Clears this bit. 1 Detects a match. No effect. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 682 MB9Axxx/MB9Bxxx Series
4. Registers The PC match and RC match interrupt request flag bit (QPCNRCMF) is set to 1 immediately when the following one of conditions is satisfied. The mode is changed to PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11) when the positio n counter is disabled (QCR:PCM[1:0]=00) and the revolution counter is in the mode other than RC_Mode0(QCR:RCM[1:0]=00) while the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) and the value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR). The value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) when data is written to the Quad Pos ition & Revolution Counter Position Count Register (QPCR) or QPRC Position Counter Compare Regist er (QPCCR) where the value of the revolution counter matches that of the QPRC Position & Revolution Counter Compare Register (QPRCR) when the mode is PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11) and the revolution counter is in the mode other than RC_Mode0 (QCR:RCM[1:0]=00). The value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) when the data is wr itten to the QPRC Position and Revolution Counter Compare Register (QPRCR) in the mode othe r than RC_Mode0 (QCR:RCM[1:0]=00) where the specified value matches that of the QPRC Pos ition Count Register (QPCR) or QPRC Position Counter Compare Register (QPCCR) in PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11). The value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) when the mode is changed from RC_Mode0 (QCR:RCM[1:0]=00) to another mode where the specified value matches th at of the QPRC Position Count Register (QPCR) or QPRC Position Counter Compare Register (QPCCR) in PC_Mode1 (QCR:PCM[1:0]=01), PC_Mode2 (QCR:PCM[1:0]=10), or PC_Mode3 (QCR:PCM[1:0]=11). This bit is set to 1 when the value of the position counter matches that of the QPRC Position Counter Compare Register (QPCCR) and the value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Regist er (QPRCR) regardless of the setting of the register function selection bit (QCR:RSEL). [bit 12] QPCNRCMIE: PC match and RC match interrupt enable bit This bit is used to co ntrol whether or not to issue an interrupt notification to the CPU when the PC match and RC match interrupt request flag (QPCNRCMF) is set to 1. When this bit is set to 1, an interrupt is generated if the value of the position counter matches that of the QPRC Position Counter Compare Regist er (QPCCR) and the value of the revolution counter matches that of the QPRC Position and Revolution Counter Compare Register (QPRCR) (QPCNRCMF=1). Bit Description 0 Interrupt disabled 1 Interrupt enabled [bit 11] DIROU: Last position counter flow direction bit This bit indicates the direction of the position counter when the last position counter overflow or underflow was detected. Bit Description 0 The position counter was incremented. 1 The position counter was decremented. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 683 MB9Axxx/MB9Bxxx Series
4. Registers [bit 10] DIRPC: Last position counter direction bit This bit indicates the count direction when the position counter was last changed. Bit Description 0 The position counter was incremented. 1 The position counter was decremented. As the di rection of the position counter is not detected in PC_Mode0 (QCR:PCM[1:0]=00), the last position coun ter direction bit (QICR:DI RPC) becomes indefinite. Therefore, if the mode is changed from PC_Mode0 (QCR:PCM[1:0]=00) to another mode, when a ZIN active edge is detected before an AIN/BIN active edge is detected, the following operations apply. The position counter is reset if the mode is RC_Mode0 (QCR:RCM[1:0]=00), RC_Mode1 (QCR:RCM[1:0]=01), or RC_Mode3 (QCR:RCM[1:0]=11) The revolution counter is not counted up or down [bit 9] CDCF: Count inversion interrupt request flag bit This bit indicat es wh ether or not the position counter inverted the count direction. This bit is set to 1 when the position counter inverts the count direction. Inverting the count direction means that the counter counts down at the next counting after counting up, or the counter counts up at the next counting after counting down. This flag can only clear to 0 in write mode. Setting 1 has no effect. 1 is read by the read-modify-write access operation. Description Bit Read Write 0 Does not invert the count direction of the position counter. Clears this bit. 1 Inverts the count direction of the position counter at least once. No effect. As the di rection of the position counter is not detected in PC_Mode0 (QCR:PCM[1:0]=00), the last position coun ter direction bit (QICR:DI RPC) becomes indefinite. Therefore, after the mode is changed from PC_Mode0 (QCR:PCM[1:0]=00) to another mode, even if an AIN/BIN active edge is detected and the direction of the position counter is inverted, the coun t inversion interrupt request flag bit (QICR:CDCF) is not set to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 17: Quad Position & Revolution Counter MN706-00002-1v0-E 684 MB9Axxx/MB9Bxxx Series