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 When transmit/receive FIFO is enabled: 
1.
 Sets the number of bytes to be received to the FBYTE register. 
2.
 Writes an address for Slave Address (including the data direction bit) and dummy data in the number  of bytes to be received  to the TDR register.   
3.
 Writes 1 to the IBCR:MSS bit. 
4.
 An ACK response is returned and data reception co ntinues as long as the SSR:TDRE bit stays 0. 
During that reception operation, SSR:RDRF is set to 1 when the number of bytes set up in FBYTE 
have been received. When SSR:RDRF is set to  1, starts reading from the RDR register. 
5.
 When SSR:TDRE bit is 1, sets the interrupt flag to 1 to set the I2C bus in the wait state after 
outputting NACK if IBCR:WSEL=0,  and directly after one-byte reception if IBCR:WSEL=1. 
6.
 In case of IBCR:WSEL=1, sets the IBCR:ACKE b it to 0. In case of IBCR:WSEL=0, no setting 
is needed for the IBCR:ACKE bit, Setting the I BCR:MSS bit to 0 or setting the IBCR:SCC bit to 
1 generates the stop condition or iteration start condition. 
 When DMA mode is enabled (SSR:DMA=1) 
When the data direction bit (R/W) is set to 1, the master receives data transmitted from a slave.   
When FIFO is disabled, the master operates as follows. 

 If the SSR:TDRE bit is set to 1, wait is generated (SSR:TBI=1, SSR:RDRF=1) each time one byte 
is received. At this time, an ACK or NACK response is returned, according to the setting of the ACKE 
bit in the IBCR register, before wait if the IBCR:WSEL  bit is 1, and after wait if the IBCR:WSEL bit is 
0. 

 If the SSR:TDRE bit is set to 0, wait is generated  (SSR:RDRF=1) each time one byte is received. At 
this time, an ACK or NACK response is returned, according to the setting of th e ACKE bit in the IBCR 
register, before wait if the IBCR:WSEL bit is 1, and after wait if the IBCR:WSEL bit is 0. 
 
When FIFO is enabled, the SSR:RDRF bit is set upon reception of data in the same number of bytes set for 
the number of bytes to be received. The transmit bus  idle flag (SSR:TBI) is set when the SSR:TDRE bit is 
1, which puts the I
2C bus in the wait state. At this time, acknowledgement operates as follows. Even if 
NACK is output, it is stored in receive FIFO as receive data. 

 In case of IBCR:WSEL=0, an NACK response is re turned when the SSR:TDRE bit is set to 1 if 
NACK is set for the ACKE bit. 

 In case of IBCR:WSEL=1, wait is generated (SSR:TBI =1) after receiving the last byte. During that 
wait, the master sets the IBCR :ACKE bit and returns ACK or NA CK response, according to the 
IBCR:ACKE setting, after clearing the  transmit bus idle flag (SSR:TBI). 
 
For interrupt-generated wait, refer to the following. 
Table 2-7 IBCR:WSEL bit status for master data reception when DMA mode is enabled  (SSR:DMA=1) 
WSEL bit Operation 
0  After the second byte, after 
acknowledgement with 1 set for the SSR:TDRE bit, the 
transmit bus idle flag (SSR:TBI) is set to  1 and SCL to LOW for the wait state. 
After the second byte, after  acknowledgement when receive  FIFO is not used, if the 
receive data full flag (SSR:RDRF) is set to  1, SCL is set to LOW for the wait state. 
After the second byte, after the m
 aster has 
received one-byte data with 1 set for the 
SSR:TDRE bit, the interrupt flag (SSR:TBI) is set to 1 and SCL to LOW for the wait 
state. 
1 
After the second byte, after the receive data  full flag (SSR:RDRF) is set to 1 when 
receive FIFO is not used, SCL is set to LOW for the wait state. 
 
The following shows an ex ample procedure for receiving data from a slave. 
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 When receive FIFO is disabled: 
1.
 Sets Slave Address (including the data direction  bit) to the TDR register and writes 1 to the 
IBCR:MSS bit.   
2.
 ACK is received after the Slave Ad dress setting is transmitted, and then the transmit bus idle flag 
(SSR:TBI) is set to 1. 
3.
 Writes data to be transmitted to the TDR re gister to release the wait state of the I2C bus. 
4.
 After one byte is received, sets the transmit bus id le flag (SSR:TBI) and the receive data full flag 
(SSR:RDRF)*2 to 1 under the following conditions to put the I2C bus in the wait state. 

 In case of IBCR:WSEL=0, after transmitting acknowledgement 

 In case of IBCR:WSEL=1, after receiving one byte 
5.
 Updates the IBCR:WSEL bit, reads from the RD R register and writes dummy data to the TDR 
register. 
6.
 After one byte is received, sets the transmit bus id le flag (SSR:TBI) and the receive data full flag 
(SSR:RDRF)*2 to 1 under the following conditions to put the I2C bus in the wait state.   

 In case of IBCR:WSEL=0, after transmitting acknowledgement 

 In case of IBCR:WSEL=1, after receiving one byte 
Repeats steps 5 to 6 until all the specified number of data sets have been received. 
7.
 After receiving the last data, outputs NACK and  sets the IBCR:MSS bit to 0 or sets the 
IBCR:SCC*1 bit to 1 to generate the stop condition or iteration start condition. 
 

 When transmit/receive FIFO is enabled: 
1.
 Sets the number of bytes to be received to the FBYTE register. 
2.
 Writes an address for Slave Address (including the data direction bit) and dummy data in the number  of bytes to be received  to the TDR register.   
3.
 In case of IBCR:WSEL=0, sets NACK for the  ACKE bit, and writes 1 to the IBCR:MSS bit. 
4.
 An ACK response is returned and data reception co ntinues as long as the SSR:TDRE bit stays 0. 
During that reception operation, SSR:RDRF is set to 1 when the number of bytes set up in FBYTE 
have been received. When SSR:RDRF is set to  1, starts reading from the RDR register. 
5.
 When the SSR:TDRE bit is set to 1, sets the interrupt flag to 1 to set the I2C bus in the wait state 
after outputting NACK if IBCR:WSEL=0. In case of IBCR:WSEL=1, directly after one byte is 
received, sets the transmit bus idle flag (SSR:TBI) to 1 to put the I
2C bus in the wait state. 
6.
 In case of IBCR:WSEL=1, sets the IBCR:ACKE b it to 0. In case of IBCR:WSEL=0, no setting 
is needed for the IBCR:ACKE bit, Set the IBCR:MSS  bit to 0 or set the IBCR:SCC*1 bit to 1 to 
generate the stop condition or iteration start condition. 
  *1 :  When DMA is enabled (SSR:DMA=1), the SSR :TBI bit is 1 and the IBCR:INT bit is 0, 
follow the steps below to issue the iteration start condition. 
1.
 Set the IBCR:INT bit to 1. 
2.
 Check that the IBCR:INT bit is set to 1. 
3.
 Write the slave address in the TDR. 
4.
 Set the IBCR:SCC bit to 1. 
 
*2 :  Directly after receiving one byt e, the receive data full flag (SSR:RDRF) is set to 1 regardless 
of the setting for IBCR:WSEL. When the receive data full flag (SSR:RDRF) is set to 1, put 
the I
2C bus in the wait state after transmitting  acknowledgment in case of IBCR:WSEL=0, 
and directly after receiving one  byte in case of IBCR:WSEL=1. 
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 
 When seven-bit slave address detection is enabled (ISBA:SAEN=1), it is prohibited to specify a 
seven-bit slave address in master mode. 

 When SSR:TDRE is 0, even if an overrun error occurs, acknowledgement is output according to the 
setting for the IBCR:ACKE bit, and then the next process should follow.   

 To change the IBCR register during transmission/reception, do so when the interrupt flag (IBCR:INT) is 
1 or when the transmit bus idle flag (SSR:TBI) is 1 during DMA mode being enabled 
(SSR:DMA=1). 

 In the master mode reception with  DMA disabled (SSR:DMA=0), write  dummy data to the TDR register, 
and then, if the SSR:TDRE bit is 0 when the interrupt flag (IBCR:INT) is turn ed to 1, receive the 
next data with the interrupt flag (IBCR:INT) kept at 0.   

 In the master mode reception with DMA enabled (SSR :DMA=1), write dummy data to the TDR register, 
and then, if the SSR:TDRE bit is 0 when the transmit bus idle flag (SSR:TBI) is turned to 1, receive 
the next data with the transmit bus idle flag (SSR:TBI) kept at 0.   

 To receive data when receive FIFO is enabled and IBCR:WSEL=0, the SSR:RDRF bit is set to 1 
after receiving the last bit and th e interrupt flag (IBCR:INT) is se t to 1 after transmitting ACK. 
 
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Figure 2-30 Master mode receive interrupt 1 by disabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBSR:RSA=0) 
 
 
S R ACK Data DataACKDataACK P or SrSlave AddressNACK 
 


 

 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.  - If the INT bit is set to 0, the interrupt flag is cleared to 0. 
 An interrupt occurs when a single byte is received and an ACK is sent. 
- After the received data has been read, the INT bit is set to 0. 
 An interrupt occurs when a single byte is received and an ACK is sent. 
- After the received data has been read both ACKE and INT bits are set to 0. , 
, 
 An interrupt occurs when a single byte is received and an ACK is sent. 
- MSS bit is set to 0, or both MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1
. 
 
 
Figure 2-31 Master mode receive interrupt 2 by disabling FIFO    (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S ACK Data Slave Address RDataACKDataACK P or SrNACK 
   
  

 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.  - If the INT bit is set to 0, the interrupt flag is cleared to 0. 
 An interrupt occurs when a single byte is received. 
- After the received data has been read, the INT bit is set to 0. 
 An interrupt occurs when a single byte is received. 
- After the received data has been read, ACKE bit are set to 0. MSS bit is set to 0, 
or both MSS and SCC bits are set to 1.
 
*) If an interrupt flag (INT) is set, the TDRE bit is set to 1. 
 
 
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Figure 2-32 Master mode receive interrupt 3 by enabling FIFO   (SSR:DMA=0, IBCR:WSEL=0, IBCR:ACKE=0, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 

 
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if TDRE bit is set to 1. 
- The entire data is read from the Receive FIFO buffer
, and MSS bit is set to 0 or both MSS   
and SCC bits are set to 1.
 
 
Figure 2-33 Master mode receive interrupt 4 by enabling FIFO    (SSR:DMA=0, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
  
 
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if TDRE bit is set to 1. 
- After the entire data has been read from the Receive FIFO buffer
, ACKE bit is set to 0 
and MSS bit is set to 0 or both MSS and SCC bits are set to 1.
 
 
Figure 2-34 Master mode receive interrupt 5 by disabling FIFO    (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 
 

   


 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received.
- Dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received and an ACK is sent. 
- After the received data has been read, the dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received and an ACK is sent. 
- After the received data has been read, the ACKE bit are set to 0  and the dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received and an ACK is sent. - MSS bit is set to 0, or both MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT or TBI) is set, the TDRE bit is set to 1
. 
 
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Figure 2-35 Master mode receive interrupt 6 by disabling FIFO   (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 
  

  
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 : Interrupt by TBIE=1 
 An interrupt occurs when the slave address is sent, the direction bit is sent, and an ACK is received. 
- Dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received. 
- After the received data has been read, the dummy data is written in the TDR register. 
 An interrupt occurs when a single byte is received. 
- After the received data has been read, ACKE bit are set to 0 MSS bit is set to 0,    or both MSS and SCC bits are set to 1. 
*) If an interrupt flag (INT or TBI) is set, the TDRE bit is set to 1
. 
 
Figure 2-36 Master mode receive interrupt 7 by enabling FIFO    (SSR:DMA=1, IBCR:WSEL=0, IBCR:ACKE=0, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
 
 

 
 
 : Interrupt by INTE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if TDRE bit is set to 1. 
- The entire data is read from the Receive FIFO buffer
, and MSS bit is set to 0 or both MSS   
and SCC bits are set to 1.
 
 
Figure 2-37 Master mode receive interrupt 8 by enabling FIFO    (SSR:DMA=1, IBCR:WSEL=1, IBSR:RSA=0) 
 
 
S R ACK Data Slave Address DataACKDataACK P or SrNACK 
  
 
 
 : Interrupt by TBIE=1 
 : Interrupt by CNDE=1 
 An interrupt occurs if TDRE bit is set to 1. 
- After the entire data has been read from the Receive FIFO buffer
, ACKE bit is set to 0 
and MSS bit is set to 0 or both MSS and SCC bits are set to 1.
 
 
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 Arbitration lost 
If the master receives the data different from sent data, due to concurrent transmission of data from another 
master, the master judges the situation as arbitration lost. At this time, the IBCR:MSS bit is set to 0 and 
the IBSR:AL bit to 1, enabling operation in slave mode.   
The IBSR:AL bit can be cleared to 0 under the following conditions: 

 The IBCR:MSS bit is set to 1. 

 The IBCR:INT bit is set to 0. 

 The IBSR:SPC bit is set to 0 when the IBSR:AL bit and IBSR:SPC bit are 1. 

 The I2C interface operation is disabled (ISMK:EN bit=0). 
 
Upon an occurrence of arb itration lost, the interrupt fl ag (IBCR:INT) is set to 1 according to the setting of 
the IBCR:WSEL bit, and sets SCL of the I
2C bus to LOW. 
 Wait state for master mode 
When both conditions below are satisfied, master mode is put in the wait state while the IBSR:BB bit stays 
1. After the IBSR:BB bit attains  0, start condition is transmitted. 

 When the IBCR:MSS is set to 1 while the IBSR:BB bit is 1 

 When the interface is not operating as a slave 
 
Refer to the IBCR:MSS bit and IBCR:ACT bit to check if master mode is in the wait state or not (in the 
wait state if the IBCR:MSS=1 and IBCR:ACT=0). Af ter setting the IBCR:MSS bit to 1 and to operate 
in slave mode, set the IBSR:AL bit to 1, the IBCR:MSS bit to 0, and the IBCR:ACT bit to 1. 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
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 Issuing iteration start condition when DMA mode  is enabled (SSM:DMA=1) 
When writing a slave address to the TDR register wh ile the transmit bus is idle (SSR:TBI=1) and the 
interrupt flag (IBCR:INT) is 0, transmission star ts and the iteration start condition cannot be issued. 
Therefore, to issue the iteration start condition while  the transmit bus is idle (SSR:TBI=1) and the 
interrupt flag (IBCR:INT) is 0, follow the steps below. 
1.
 Set the IBCR:INT bit to 1. At this  time, no SIRQ interrupt is generated. 
2.
 Check that the IBCR:INT bit is set to 1. 
3.
 Write the slave address in the TDR. 
4.
 Issue the iteration start  condition (IBCR:SCC=1). 
 
Figure 2-38 Issuing iteration condition when DMA mode is enabled    (SSR:DMA=1, IBCR:WSEL=0, IBSR:RSA=0, ACK response) 
ACK
D0
TBI bit
TDRE bit
INT bit
D7
The SCC bit 
is set to 1.
The INT bit is 
set to 1. Data writing in 
the TDR
An iteration start 
condition is generated.
SIRQ
No interrupt 
is generated.
ACK
D7 D6 D5 D4 D3 D2 D1 D0SDA SCL
The INT bit is 
read.Logical 1 state 
is checked.
 
 
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2.3. Slave mode 
If the (iteration) start condition is detected and a combination of the ISBA and ISMK registers 
matches the received address, the interface outputs an ACK response and acts in slave 
mode. 
 Slave address match detection 
After the (iteration) start condition is detected, subsequent seven bits are received as the address. For each 
of the bits that are set to 1 in the ISMK register, the ISBA register is compared with the received address. 
If they match, ACK is output. 
Table 2-8 Operation immediately after outputting acknowledgement to a slave address 
Operation immediately after receiving acknowledgement 
Data 
direction  bit 
(R/W)
Tr
ansmit  
FIFO 
status Receive 
FIFO 
status 
Transmit 
FIFO  Receive 
FIFO  Acknowledgement: 
NACK 
Acknowledgement: ACK 
0 If the SSR:TDRE bit is set to 1
,
  the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state.  Holds the IBCR:INT bit 
to 0 without the wait 
state. 
Disable Disable 
- - 
1 
Without data  Holds the IBCR:INT bit to 0 without the 
wait state. 
0 
Sets the IBCR:INT bit to 1 with the wait 
stat e.
 
With 
data 
Holds the IBCR :INT
 bit 
to 0 withou t th
e wai t

 
state. 
Disable Enable 
- 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state. 
0 Sets the IBCR:INT bit to 1 with the wait 
state if
 the
  SSR:TDRE bit is 1, and holds 
the IBCR:INT bit to 0 without the wait 
state if the SSR:TDRE bit is 0.  Holds the IBCR:INT bit 
to 0 without the wait 
state. 
Enable Disable 
- - 
1 
Without data  Holds the IBCR:INT bit to 0 without the 
wait state. 
0 
Sets the IBCR:INT bit to 1 with the wait 
stat e.
 
With 
data 
Holds the IBCR :INT
 bit 
to 0 withou t th
e wai t

 
state. 
Enable Enable 
- 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state. 
 

 Detection of reserved address If the first byte matches the reserved address (0000x xxx or 1111xxxx), the value of bit 8 is received 
regardless of whether or not tran smit/receive FIFO is enabled, and  the IBCR:INT bit is set to 1, 
causing the I
2C bus to be placed into the wait state. After  the receive data has been read, configure the 
following settings. 

 To run the interface as a slave device, set the IBCR: ACKE bit to 1 and check the value of the data 
direction bit (IBSR:TRX). If the tr ansmitting direction is set, write the transmit data to TDR, and 
clear the IBCR:INT bit. The interface  then acts as a slave device. 

 When not running the interface as a slave device,  set the IBCR:ACKE bit to 0, and clear the 
IBCR:INT bit. After acknowledgement has been output, the interface does not act as a slave device. 
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 Data direction bit 
After receiving the address, the interface receives the data direction bit to determine whether to transmit or 
receive data. If this bit is 0, it  means that data is transmitted from  the master device, and the interface 
receives data as a slave device. 
 Reception in slave mode 
If the received data matches the slave address and the data  direction bit is 0, it means that data is received 
in slave mode. The following  shows a procedure example to receive data in slave mode. 
 When DMA mode is disabled (SSR:DMA=0) 
 When receive FIFO is disabled: 
1.
 After transmitting ACK, set the interrupt  flag (IBCR:INT) to 1, and place the I2C bus into the wait 
state. Based on the IBCR:MSS, IBCR:ACT, and IBSR:FBT bits, judge that the event is an interrupt 
by a slave address match. Then write 1 to th e IBCR:ACKE bit and 0 to the interrupt flag 
(IBCR:INT), and release the wait state of the I
2C bus (see Ta b l e  2 - 8 ). 
2.
 After receiving 1-byte data, set the interrupt fl ag (IBCR:INT) to 1 according to setting of the 
IBCR:WSEL bit, and place the I2C bus into the wait state. 
3.
 Read the data received from the RDR register, set th e IBCR:ACKE bit, write 0 to the interrupt flag 
(IBCR:INT), and release the wait state of the I2C bus. 
4.
 Repeat steps 2 and 3 to detect th e stop or iteration start condition. 
 

 When receive FIFO is enabled: 
1.
 If NACK is detected or receive FIFO becomes full, the interrupt flag  (IBCR:INT) is set to 1, and the 
I2C bus is placed into the wait state. If the stop  or iteration start condition is detected, the interrupt 
flag (IBCR:INT) is not set to 1 (the I2C bus is not placed into th e wait state) by setting the 
IBSR:SPC and IBSR:RSC bits to 1. Receive FIFO  sets the SSR:RDRF bit to 1 when the set value 
of the FBYTE register matches the number of data  sets received. If the SMR:RIE bit is then 1, a 
receive interrupt is generated. 
2.
 When the interrupt flag (IBCR:INT) is set to 1,  read the received data from the RDR register. After 
all data has been read, write 0 to the interrupt flag to release the wait state of the I2C bus. If the stop 
or iteration start condition is detect ed, read all the received data from the RDR register, and clear the 
IBSR:SPC or IBSR:RSC bit to 0. 
 
 When DMA mode is enabled (SSR:DMA=1) 
 When receive FIFO is disabled: 
1.
 After transmitting ACK, set the interrupt  flag (IBCR:INT) to 1, and place the I2C bus into the wait 
state. Based on the IBCR:MSS, IBCR:ACT, and IBSR:FBT bits, judge that the event is an interrupt 
by a slave address match. Then write 1 to th e IBCR:ACKE bit and 0 to the interrupt flag 
(IBCR:INT), and release the wait state of the I
2C bus (see Ta b l e  2 - 8 ). 
2.
 Set 1 to the receive data full flag (SSR:RDRF) immediately after receiving 1-byte data. When the  receive data full flag (SSR:RDRF) is set to 1, if IBCR:WSEL=0, place the I2C bus into the wait 
state after transmitting acknowledg ement. If IBCR:WSEL=1, place the I2C bus into the wait state 
immediately after receiving the 1-byte data. 
3.
 After setting the IBCR:ACKE bit, r ead the data received from the RDR register, and clear the receive 
data full flag (SSR:RDRF) to 0 to release the wait state of the I2C bus. 
4.
 Repeat steps 2 and 3 to detect th e stop or iteration start condition. 
 
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