Fujitsu Series 3 Manual
Have a look at the manual Fujitsu Series 3 Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 86 Fujitsu manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
2. Configuration of CPU Operation Modes 2. Configuration of CPU Operation Modes This section explains the configuration of CPU operation modes. CPU operation mode transition diagram Figure 2-1 shows the CPU operation mode transition diagram. Figure 2-1 CPU operation mode transition diagram Power-on Initialization power-on reset High speed CR oscillation stabilization waiting Low speed CR oscillation stabilization waiting High speed CR mode Main mode PLL mode Low speed CR mode Sub mode (1) (2)(3) (4) (5) (1) Power-on reset (2) Release power-on reset. (3) End oscillation st abilization waiting. (4) Transition to main mode (MOSCE=1, RCS=001) (5) Transition to high speed CR mode (RCS=000) (6) (6) Transition to low speed CR mode (RCS=100) (5) (7) Transition to sub mode (SOSCE=1, RCS=101) (4)(6) (7) (5) (8) Transition to PLL mode (MOSCE=1, PLLE=1, RCS=010) (8) (4) (9) (9) (9) Reset (Excluding software reset) (4) (7) (6) (7) (8) (7) (8) (8) (5) (6) High speed CR mode In this mode, the high speed CR oscillator clock is used as a master clock. Main mode In this mode, the main oscillator clock is used as a master clock. Low speed CR mode In this mode, the low speed CR oscillator clock is used as a master clock. Sub mode In this mode, the sub oscillator clock is used as a master clock. PLL mode In this mode, the PLL oscillator clock is used as a master clock. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 105 MB9Axxx/MB9Bxxx Series
2. Configuration of CPU Operation Modes
High speed CR mode transition diagram
In high speed CR mode, the high speed CR oscillator clock is used as a master clock.
Figure 2-2 High speed CR mode transition diagram
High speed CR run mode
High speed CR sleep mode
STOP mode
Program reset
High speed CR timer mode
High speed CR oscillation
stabilization waiting
Other modeA-1 Transition to RUN mode
(Oscillation stabilization)
A-2 Start high speed CR oscillation .
A-1A-2
A-4 Software reset
A-4A-5
A-3
A-5 Release software reset . A-3 Complete oscillation stabilization waiting .
A-6
A-7
A-6 SLEEP mode (WFI or WFE instruction at SLEEPDEEP =0)
A-7 Interrupt
A-8
A-8 TIMER mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=00)
A-7
A-9
A-9 STOP mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=10)
A-7
A-10A-10 Transition to other mode
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 5: Low Power Consumption Mode
MN706-00002-1v0-E
106
MB9Axxx/MB9Bxxx Series
2. Configuration of CPU Operation Modes
Main mode transition diagram
In main mode, the main oscillator clock is used as a master clock.
Figure 2-3 Main mode transition diagram
Main run mode
Main sleep mode
STOP mode
Program reset
Main timer mode
Main oscillation stabilization
waiting
Other mode
B-1B-2
B-4B-5
B-3
B-6
B-7
B-8
B-7
B-9
B-7
B-10
B-1 Transition to RUN mode (MORDY=1)
B-2 Start main oscillation. (MORDY=0)
B-4 Software reset
B-5 Release software reset. B-3 Complete oscillation stabilization waiting.
(MORDY=1) B-6 SLEEP mode (WFI or WFE instruction at SLEEPDEEP=0)
B-7 Interrupt
B-8 TIMER mode
(WFI or WFE instruction at SLEEPDEEP=1 and STM=00)
B-9 STOP mode (WFI or WFE instruction at SLEEPDEEP=1 and STM=10)
B-10 Transition to other mode
Low speed CR mode transition diagram
In low speed CR mode, the low speed CR oscillator clock is used as a master clock.
Figure 2-4 Low speed CR mode transition diagram
Low speed CR run mode
Low speed CR sleep mode
STOP mode
Program reset
Low speed CR timer mode
Low speed CR oscillation
stabilization waiting
Other mode
C-1C-2
C-4C-5
C-3
C-6
C-7
C-8
C-7
C-9
C-7
C-10
C-1 Transition to RUN mode
(Oscillation stabilization)
C-2 Start low speed CR oscillation .
C-4 Software reset
C-5 Release software reset. C-3 Complete oscillation stabilization waiting . C-6 SLEEP mode (WFI or WFE instruction at SLEEPDEEP =0)
C-7 Interrupt
C-8 TIMER mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=00)
C-9 STOP mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=10)
C-10 Transition to other mode
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 5: Low Power Consumption Mode
MN706-00002-1v0-E
107
MB9Axxx/MB9Bxxx Series
2. Configuration of CPU Operation Modes
Sub mode transition diagram
In sub mode, the sub oscillator clock is used as a master clock.
Figure 2-5 Sub mode transition diagram
Sub run mode
Sub sleep mode
STOP mode
Program reset
Sub timer mode
Sub oscillation stabilization waiting
Other mode
D-1D-2
D-4D-5
D-3
D-6
D-7
D-8
D-7
D-9
D-7
D-10
D-1 Transition to RUN mode (SORDY=1)
D-2 Start sub oscillation. (SORDY=0)
D-4 Software reset
D-5 Release software reset . D-3 Complete oscillation stabilization waiting .
(SORDY=1) D-6 SLEEP mode (WFI or WFE instruction at SLEEPDEEP =0)
D-7 Interrupt
D-8 TIMER mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=00)
D-9 STOP mode
(WFI or WFE instruction at SLEEPDEEP =1 and STM=10)
D-10 Transition to other mode
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 5: Low Power Consumption Mode
MN706-00002-1v0-E
108
MB9Axxx/MB9Bxxx Series
2. Configuration of CPU Operation Modes PLL mode transition diagram In PLL mode, the PLL clock is used as a master clock. Figure 2-6 PLL mode transition diagram PLL run mode PLL sleep mode STOP mode Program reset PLL timer mode PLL oscillation stabilization waiting Main mode E-1E-2 E-4E-5 E-3 E-6 E-7 E-8 E-7 E-9 E-10 Main oscillation stabilization waiting E-7 E-11 E-1 Transition to RUN mode (PLLRDY=1) E-2 Start PLL oscillation. (PLLRDY=0) E-4 Software reset E-5 Release software reset. E-3 Complete oscillation stabilization waiting. (PLLRDY=1) E-11 Complete oscillation stabilization waiting. E-6 SLEEP mode (WFI or WFE instruction at SLEEPDEEP=0) E-7 Interrupt E-8 TIMER mode (WFI or WFE instruction at SLEEPDEEP=1 and STM=00) E-9 STOP mode (WFI or WFE instruction at SLEEPDEEP=1 and STM=10) E-10 Transition to main mode MOSCE : MOSCE bit of System Clock Mode Control Register (SCM_CTL) SOSCE : SOSCE bit of System Clock Mode Control Register (SCM_CTL) PLLE : PLLE bit of System Clock Mode Control Register (SCM_CTL) RCS : RCS bit of System Clock Mode Control Register (SCM_CTL) MORDY : MORDY bit of System Clock Mode Status Register (SCM_STR) SORDY : SORDY bit of System Clock Mode Status Register (SCM_STR) PLRDY : PLRDY bit of System Clock Mode Status Register (SCM_STR) * For the SCM_CTL and SCM_STR Registers, refer to Chapter Clocks. T o ret urn from low speed CR timer mode, sub timer mode, or STOP mode, the voltage stabilization wait time (a f ew hundred of s) of the built-in regulator is ensured. After the wait time has lapsed, the system performs operations to return to each RUN mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 109 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes 3. Operations of Standby Modes This section explains operations of standby modes. Standby modes are classified into three types: SLEEP modes (high speed CR sleep, main sleep, PLL sleep, low speed CR sleep, and sub sleep), TIMER modes (high speed CR timer, main timer, PLL timer, low speed CR timer, and sub timer), and STOP mode. Clock operation states in standby modes The table below shows the states of the oscillator clock, CPU clock, AHB bus clock, and APB bus clock in SLEEP, TIMER, and STOP modes. Table 3-1 Clock operation states in SLEEP modes SLEEP modes High speed CR sleep mode Main sleep mode PLL sleep mode Low speed CR sleep mode Sub sleep mode High speed CR clock Operating Operating Operating Stopped Stopped Main clock Varies depending on the setting of the MOSCE bit. Operating Operating Stopped Stopped PLL clock Setting disabled Varies depending on the setting of the PLLE bit. Operating Stopped Stopped Low speed CR clock Operating Operating Operating Operating Operating Sub clock Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Operating USB PLL clock Setting disabled Varies depending on the setting of the UPLLEN bit.Varies depending on the setting of the UPLLEN bit. Stopped Stopped CPU clock Stopped AHB bus clock High speed CR clock Main clock PLL clock Low speed CR clock Sub clock APB0 bus clock High speed CR clock Main clock PLL clock Low speed CR clock Sub clock High speed CR clock Main clock PLL clock Low speed CR clock Sub clock APB1 bus clock * Whether or not operation is enabled is determined depending on the setting of the PBC1EN bit. High speed CR clock Main clock PLL clock Low speed CR clock Sub clock APB2 bus clock * Whether or not operation is enabled is determined depending on the setting of the PBC2EN bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 110 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes Table 3-2 Clock operation states in TIMER modes TIMER modes High speed CR timer mode Main timer mode PLL timer mode Low speed CR timer mode Sub timer mode High speed CR clock Operating Operating Operating Stopped Stopped Main clock Varies depending on the setting of the MOSCE bit. Operating Operating Stopped Stopped PLL clock Setting disabled Varies depending on the setting of the PLLE bit. Operating Stopped Stopped Low speed CR clock Operating Operating Operating Operating Operating Sub clock Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Varies depending on the setting of the SOSCE bit. Operating USB PLL clock Stopped Stopped Stopped Stopped Stopped CPU clock Stopped AHB bus clock Stopped APB0 bus clock Stopped APB1 bus clock Stopped APB2 bus clock Stopped Table 3-3 Clock operation states in STOP modes STOP mode High speed CR clock Main clock PLL clock Low speed CR clock Sub clock USB PLL clock CPU clock AHB bus clock APB0 bus clock APB1 bus clock APB2 bus clock Stopped MOSCE : MOSCE bit of System Clock Mode Control Register (SCM_CTL) SOSCE : SOSCE bit of System Clock Mode Control Register (SCM_CTL) PLLE : PLLE bit of System Clock Mode Control Register (SCM_CTL) UPLLEN : UPLLEN bit of USB-PL L Control Register-1 (UPCR1) APBC1EN : APBC1EN bit of Peripheral Bus Clock Frequency Division Register (APBC1_PSR) APBC2EN : APBC2EN bit of Peripheral Bus Clock Fequency Division Register (APBC2_PSR) * For the SCM_CTL and SCM_STR Registers, refer to Chapter Clocks. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 111 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes Return factors from standby modes The table below shows the factors by which the system returns from the SLEEP, TIMER, and STOP modes. Table 3-4 Return factors from standby modes SLEEP mode TIMER mode STOP mode Return factors by reset INITX pin input reset Low-voltage detection reset Software watchdog reset Hardware watchdog reset Clock failure detection reset Anomalous frequency detection reset INITX pin input reset Low-voltage detection reset Hardware watchdog reset Clock failure detection reset INITX pin input reset Low-voltage detection reset Return factors by interrupt Effective interrupt from each peripheral NMI interrupt External interrupt Hardware watchdog timer interrupt USB wake up interrupt Watch counter interrupt Low voltage detection interrupt NMI interrupt External interrupt USB wake up interrupt Low voltage detection interrupt FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 112 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes 3.1. Operations of SLEEP modes (high speed CR sleep, main sleep, PLL sleep, low speed CR sleep, and sub sleep modes) SLEEP mode is classified as one of standby modes. Enabling SLEEP mode stops CPU clocks, reducing the power consumption. Functions of SLEEP mode CPU and internal memory In SLEEP mode, the CPU clock is stopped. However, the AHB bus clock continues to be active. The internal memory active and data is held. Peripherals The APB0 bus clock is still active in SLEEP mode. The states of the APB1 and APB2 bus clocks vary depending on the APBC1EN and APBC2EN settings. Peri pherals are held in the state that is set at transition. Watch counter The watch counter has no effect in SLEEP mode. It continues operations based on the configuration that is provided before the transition to SLEEP mode. Oscillator clocks Ta b l e 3 - 1 (Clock operation states in SLEEP modes ) shows the status of each oscillator clock. Reset and interrupt Reset and interrupt ar e available to return from SLEEP mode. External bus The external bus is still active in SLEEP mode. Status of pin All pin settings are held in SLEEP mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 113 MB9Axxx/MB9Bxxx Series
3. Operations of Standby Modes SLEEP mode setting procedure Execute the following steps to change to SLEEP mode. 1. Set 0 to the SLEEPDEEP bit of the Cortex-M3 System Control Register. 2. Execute the WFI or WFE instruction. The system changes to the appropriate SLEEP mode according to the current clock mode indicated in the RCM bit of the System Clock Mode Control Register (SCM_CTL). For the System Clock Mode Control Register (SCM_CTL), refer to Chapter Clocks. Return from SLEEP mode The CPU returns from SLEEP mode in one of the following cases. Return by reset If a reset (INITX pin input reset, low-voltage detectio n reset, software watchdog reset, hardware watchdog reset, clock failure detection reset, or anomalous frequency detection reset) occurs, the CPU changes to high speed CR run mode regardless of clock mode. Return by interrupt If an effective interrupt is received from a periphe ral in SLEEP mode, the CPU returns from SLEEP mode and changes to RUN mode to fit clock mode indicated in the RCM bit of SCM_CTL. Table 3-5 Operation modes after the CPU returned from SLEEP mode by interrupt Status of master clock before transition to SLEEP mode RCM=000 (High speed CR oscillator) RCM=001 (Main oscillator) RCM=010 (PLL oscillator) RCM=100 (Low speed CR oscillator) RCM=101 (Sub oscillator) Operation modes after return by interrupt High speed CR run mode Main run mode PLL run mode Low speed CR run mode Sub run mode RCM: RCM bit of System Clock Mode Status Register (SCM_STR) * For the SCM_CTL and SCM_STR Registers, refer to Chapter Clocks. Waiting for oscillation stabilization at return When the CPU returns by reset, it waits for the stabili zation of high and low speed CR clock oscillations. If the CPU returns by interrupt, it does not need to wait for oscillation to stabilize. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 5: Low Power Consumption Mode MN706-00002-1v0-E 114 MB9Axxx/MB9Bxxx Series