Fujitsu Series 3 Manual
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3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 875 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TDR, the SSR:TDRE b it is set to 0. This causes the first bit to output. Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) output. 2. When the first bit of transmit data is output, the SSR:T DRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. If da ta transmission is enabled (SCR:TXE=1) and if the first transmit da ta is written in the TDR at a time other than the serial clock (SCK) signal detect level, th e first data bit is not output and the data transmission may fail. After the data transmission is enabled (SCR:TXE=1), the first data must be written in the TDR at a signal detect level of the serial clock (SCK). Data reception 1. If the serial data output is disabled (SMR:SOE =0) and data reception is enabled (SCR:RXE=1), the receive data is sampled at a falling edge of serial clock (SCK) input. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE is set to 0 and the first bit is output. Then, the transmit data is output in synchronization with a rising edge of the serial clock (SCK) input. When the first bit of transmit data is output, the SSR:T DRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a falling edge of the se rial clock (SCK) input. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If the receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. Continuous switching from data reception to transmission 1. Disable the serial data output (SMR:SOE=0), enab le a receive interrupt (SCR:RIE=1), enable data reception (SCR:RXE=1), and enable data transmissi on (SCR:TXE=1). If dummy data is written in the TDR at a signal detect level of serial clock (SCK), th e receive data is sampled at a falling edge of serial clock (SCK) input. 2. To continue data reception, write a dummy data in th e TDR between the time when a receive interrupt is requested and when the next serial clock (SCK) rises. 3. To switch the data reception to the data transmissi on, enable the serial data output (SMR:SOE=1), disable a receive interrupt (SCR:RIE=0), and disable data receptio n (SCR:RXE=0) between the time when a receive interrupt is requested and when th e next serial clock (SCK) rises. Also, output the transmit data in synchronization with a rising edge of serial clock after the transmit data has been written in the TDR and the data reception has completed. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 876 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations 3.4. SPI transfer (II) Features Item Description 1 Serial clock (SCK) signal detect level LOW 2 Transmit data output timing SCK signal falling edge 3 Receive data sampling SCK signal rising edge 4 Data length 5 to 9 bits Register settings The register values required for SPI data tr ansfer (II) are listed on the table below. Table 3-4 SPI transfer (II) register settings Bit 15 Bit 14 Bit 13Bit 12 Bit 11 Bit 10 Bit 09Bit 08 Bit 07 Bit 06Bit 05 Bit 04Bit 03 Bit 02 Bit 01Bit 00 UPCL MS SPIRIE TIE TBIE RXETXEMD2 MD1MD0WUCR SCINV BDS SCKE SOESCR/ SMR 0 1/0 1 * * * * * 0 1 0 0 1 * 1/0* REC - - - ORE RDRF TDRE TBISOP - - WT1 WT0 L2 L1 L0SSR/ ESCR 0 - - - - - - - 0 - - * * * * * D8D7 D6 D5 D4 D3 D2 D1D0TDR/ RDR * * * * * * * * * - B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0BGR1/ BGR0 - * * * * * * * * * * * * * * * 1 : Set to 1. 0 : Set to 0. * : User-dependent values The ab ove bit setting (1/0) varies depending on the master or slave mode operation. Set as follows. During m a ster mode operation: SCR:MS=0, SMR:SCKE=1 During slave mode operation: SCR:MS=1, SMR:SCKE=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 877 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations SPI transfer (II) timing chart Datatransmission SCK SOUT TDR RW TXE Data reception SIN RXE Sampling 1st byte RDRF TDRE 2nd byte RDR RD *A *B D7 D0 D7 D1 D2D3 D4D5D6 D0D1D2D3D4D5 D6 D7 D0 D7 D1 D2 D3 D4 D5D6 D0D1 D2 D3D4 D5 D6 * A : During slave mode transmission (MS=1, SOE=1), 4 machine cycles or more time is required after writing data in the TDR . * B : HIGH if SCR:MS=0 D0 of the 3rd byte if SCR:MS=1 and TDRE is LOW HIGH if SCR:MS=1 and TDRE is HIGH FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 878 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Master mode operation (Set SCR:MS=0 and SMR:SCKE=1.) Data transmission 1. If serial data output is enabled (SMR:SOE=1), da ta transmission is enabled (SCR:TXE=1) and data reception is disabled (SCR:RXE=0), and when the transmit data is written in the TDR, the SSR:TDRE bit is set to 0. This causes the transmit data to be output in synchronization with a falling edge of the serial clock (SCK) output. 2. The SSR:TDRE bit is set to 1 before a half cycle of a rising edge of the first serial clock (SCK) output. Therefore, if the transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. Data reception 1. If the serial data output is disabled (SMR:SOE=0), data transmission is enabled (SCR:TXE=1) and data reception is enabled (SCR:RXE=1), and when a dummy da ta is written in the TDR, the receive data is sampled at a rising edge of serial clock (SCK) output. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1) during this time, a r eceive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. To perform data reception only, write a dummy data in the TDR so t hat the serial clock (SCK) is output. If the FIFO transmission and reception are enabled, th e serial clocks (SCK) for the preset number of frames are output when the transmit fra mes are set in the FBYTE register. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE is set to 0 and the first bit is output. Then, the transmit data is output in synchronization with a falling edge of the serial clock (SCK) output. The SSR:TDRE bit is set to 1 before a half cycle of a rising edge of the first serial clock. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interrupt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a rising edge of the serial clock (SCK) output. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 879 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Continuous data transmit or receive waiting If anything other than (ESCR:WT1, ESCR.WT0)=(0, 0) is set for the continuous data transmission or reception, a wait is inserted between frames. - ESCR.WT1=0, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte1bit - ESCR.WT1=1, ESCR.WT0=0 (in master mode operation) SCK 1Byte 2Byte2bit - ESCR.WT1=1, ESCR.WT0=1 (in master mode operation) SCK 1Byte 2Byte3bit TDRE TDRE TDRE FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 880 MB9Axxx/MB9Bxxx Series
3. CSIO (Clock Sync Serial Interface) operations Slave mode operation (Set SCR:MS=1 and SMR:SCKE=0.) Data transmission 1. If serial data output is enabled (SMR:SOE=1) and data transmission is enabled (SCR:TXE=1) and when the transmit data is written in the TDR, the SSR:TDRE b it is set to 0. This causes the first bit to output. Then, the transmit data is output in synchronization w ith a falling edge of the serial clock (SCK) input. 2. When the first bit of transmit data is output, the SSR:T DRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. If da ta transmission is enabled (SCR:TXE=1) and if the first transmit da ta is written in the TDR at a time other than the serial clock (SCK) signal detect level, th e first data bit is not output and the data transmission may fail. After the data transmission is enabled (SCR:TXE=1), the first data must be written in the TDR at a signal detect level of the serial clock (SCK). Data reception 1. If the serial data output is disabled (SMR:SOE =0) and data reception is enabled (SCR:RXE=1), the receive data is sampled at a rising edge of serial clock (SCK) input. 2. When the last bit is received, th e SSR:RDRF bit is set to 1. If a receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive data (RDR) can be read during this time. 3. When the receive data (RDR) is read, the SSR:RDRF bit is cleared to 0. Data transmission and reception 1. To perform data transmission and reception simultaneously, enable the serial data output (SMR:SOE=1) and enable the data transmission and reception (SCR:TXE, RXE=1). 2. When the transmit data is written in the TDR, the SSR:TDRE is set to 0 and the first bit is output. Then, the transmit data is output in synchronization w ith a falling edge of the serial clock (SCK) input. When the first bit of transmit data is output, the SSR:T DRE bit is set to 1. If a transmit interrupt is enabled (SCR:TIE=1), a transmit interru pt request is output. During this time, the transmit data of the 2nd byte can be written in the register. 3. The receive data is sampled at a rising edge of the se rial clock (SCK) input. When the last bit of receive data is received, the SSR:RDRF bit is set to 1. If the receive interrupt is enabled (SCR:RIE=1), a receive interrupt request is output. The receive da ta (RDR) can be read during this time. When the receive data is read, the SSR:R DRF bit is cleared to 0. Continuous switching from data reception to transmission 1. Disable the serial data output (SMR:SOE=0), enab le a receive interrupt (SCR:RIE=1), enable data reception (SCR:RXE=1), and enable data transmissi on (SCR:TXE=1). If dummy data is written in the TDR at a signal detect level of serial clock (SCK), th e receive data is sampled at a falling edge of serial clock (SCK) input. 2. To continue data reception, write a dummy data in th e TDR between the time when a receive interrupt is requested and when the next serial clock (SCK) rises. 3. To switch the data reception to the data transmissi on, enable the serial data output (SMR:SOE=1), disable a receive interrupt (SCR:RIE=0), and disable data receptio n (SCR:RXE=0) between the time when a receive interrupt is requested and when th e next serial clock (SCK) rises. Also, output the transmit data in synchronization with a rising edge of serial clock after the transmit data has been written in the TDR and the data reception has completed. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 881 MB9Axxx/MB9Bxxx Series
4. Dedicated baud rate generator 4. Dedicated baud rate generator The dedicated baud rate generator functions in the master mode operation only. However, if receive FIFO is used, set the dedicated baud rate generator in the slave mode operation, too. CSIO (Clock Sync Serial In terface) baud rate selection The dedicated baud rate generator settings vary depending on the master or slave mode operation. [1] During master mode operation Divide the internal clock frequency us ing the dedicated baud rate generator, and select a baud rate. This generator provides two internal reload counters, which support transmitting and receiving serial clocks respectively. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). The internal clock frequency is divided by the reload counter set value. [2] During slave mode operation The dedicated baud rate generator does not function in the slave mode operation (SCR:MS=1). (An external clock, entered from the SCK clock input pin, is used directly.) If receive FIFO is used, set the dedicated baud ra te generator eve n in the slave mode operation. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051 MN706-00002-1v0-E 882 MB9Axxx/MB9Bxxx Series
4. Dedicated baud rate generator
4.1. Baud rate settings
This section explains how to set the baud rate. Also, the calculation result of serial clock
frequency is shown.
Calculating the baud rate
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0).
The baud rate is obtained in the following formulas.
(1) Reload value
(2) Calculation example
To set the 16MHz bus clock, use the internal clock, and set the 19200-bps baud rate, set the reload
value as follows. Reload value:V = (16 x 1000000)/19200 - 1 = 832
Therefore, the baud rate is:
b = (16 x 1000000)/(832 + 1) = 19208bps
(3) Baud rate error
The baud rate error can be calculated by the following equation.
Error (%) = (Calculated value - Target value)/Target value x 100
Example: To set the 20MHz bus clock and 153600-bps target baud rate:
Reload value = (20 x 1000000)/153600 - 1 = 129
Baud rate (Calculated value) = (20 x 1000000)/(129 + 1) = 153846 (bps)
Error (%) = (153846 - 153600)/153600 x 100 = 0.16 (%)
V = / b - 1
V : Reload value; b : Baud rate; : Bus clock frequency
If th e
reload value is set to 0, the reload counter is stopped.
If the relo ad
value is even, the HIGH and LOW width of serial clock are as follows. If the value is
odd, the serial clock has the same HIGH and LOW signal width.
If SMR:SCINV=0, the HIGH width of serial clock is longer for 1 cycle of bus clock.
If SMR:SCINV=1, the LOW width of serial clock is longer for 1 cycle of bus clock.
Set the reload value to 3 or more.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19-3: CSIO \050Clock Sync Serial Interface\051
MN706-00002-1v0-E
883
MB9Axxx/MB9Bxxx Series
4. Dedicated baud rate generator Reload values and baud rates for each bus clock frequency Table 4-1 Reload values and baud rates 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32 MHz Baud rate (bps) Value ERRValue ERR ValueERRValueERRValueERR Value ERR 8 M - - - - - - - - - - 3 0 6 M - - - - - - - - 3 0 - - 5 M - - - - - - 3 0 - - - - 4 M - - - - 3 0 4 0 5 0 7 0 2.5 M - - 3 0 - - - - - - - - 2 M 3 0 4 0 7 0 9 0 11 0 15 0 1 M 7 0 9 0 15 0 19 0 23 0 31 0 500000 15 0 19 0 31 0 39 0 47 0 63 0 460800 - - - - - - - - 51 -0.16 - - 250000 31 0 39 0 63 0 79 0 95 0 127 0 230400 - - - - - - - - 103 -0.16 - - 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 207 -0.16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 68 -0.6486 0.22 138 0.08173 0.22 207 -0.16 277 0.08 76800 103 -0.16 129 -0.16 207 -0.16259 -0.16 311 -0.16 416 0.08 57600 138 0.08 173 0.22 277 0.08346 -0.16 416 0.08 555 0.08 38400 207 -0.16 259 -0.16 416 0.08 520 0.03 624 0 832 -0.04 28800 277 0.08 346