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5. Endianness and Valid Byte Lanes 
 
Example: 
When a byte access is performed to a 16-bit wide target, only 2 bytes are valid according to endianness 
shown in the above table. Data in the internal bus is assigned to 16 bits according to endianness, and input 
or output. 
 
31 0
23 15 7
Unused
Little endian
HADDR[1]=0
310
23 15 7
H*DATA
External I/O
MDATA HADDR[1]=1
 
 
HADDR: AHB address input 
As shown in the above figure, only HADDR[1] is involved in data assignment. This is also the case with 
during a half word access. During
 a word access, the external bus interface generates addresses 
automatically, and executes accesse s twice corresponding to the HADDR [1] value. The dual access is a 
serial access in which the address changes while the chip select signal is LOW. 
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5. Endianness and Valid Byte Lanes 
 
The following figure shows a correlation between internal data and ex ternal I/O when the 8-bit wide target 
is accessed. 
Only a single byte is valid according to endianness. 
 
31
Unused
HADDR[1:0]= 10
HADDR[1:0]=01HADDR[1:0]=11  HADDR[1:0]=00
23 15
70
31 23 15 70
Internal bus data
H*DATA
External I/O
MDATA
Little endian
 
 
For an 8-bit target, the HADDR[1:0] value determines the I/O data. 
When a word or half word access is performed, the ex
ternal bus interface automatically generates addresses, 
and operates at least a single access. This app lies to every type of access independent of settings. 
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6. Connection Examples 
 
6. Connection Examples 
This section provides an example of connections with external devices. 
 8-bit SRAM 
Figure 6-1  shows an example of connecting an 8-bit SRAM. 
Figure 6-1 Example 8-bit SRAM connection 
 
This LSI
x8 SRAM
MAD [24:0]
MCSX [0] MOEX
MWEX
MDATA [7:0] Adr
CS
OE
WE
DQ [7:0]
 
 

 8-bit SRAM   2 
Figure 6-2  shows an example of connecting two 8-bit SRAMs. 
Figure 6-2 Example dual 8-bit SRAMx2 connection 
 
This LSI
x8 SRAM
x8 SRAM
MDATA  [7:0]
MDATA  [15:8]
MAD [24:1]
MCSX [0]
MDQM [0]
MDQM [1]
A
CS
OE
WE
DQ [7:0]
A
CS
OE
WE
DQ [7:0]
MOEX
MDQM [1:0]
MDATA [15:0]
 
 
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6. Connection Examples 
 
 16-bit SRAM 
Figure 6-3  shows an example of connecting a 16-bit SRAM. 
Figure 6-3 Example 16-bit SRAM connection 
 
This LSI
X16 SRAM
 
 MAD [24:1]
MCSX [0] MOEX
MWEX
MDQM [1:0]
MDATA [15:0] A
CS
OE
WE
DQM [1:0]
DQ [15:0]
 
 
  8-bit NAND 
Figure 6-4  shows an example of connecting an 8-bit NAND flash memory. 
Figure 6-4 Example 8-bit NAND flash memory connection 
 
This LSI
x8 NAND
MAD [24:0]
MCSX [0] MNCLE
MNALE
MNREX
MNWEX
MDATA [7:0] A
CS
CLE
ALE
RE
WE
DQ [7:0]
 
 
 
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7. Registers 
 
7. Registers 
This section explains the configuration and functions of registers used for the external bus 
interface. 
The following explains the registers used for the external bus interface. The bit width of every register is 32. 
Each register can be accessed by the APB interface w ith 32-bit width (word). Write 0 to reserved areas. 
A rewritten register value is not immediately applied  to the operation. When you rewrite a register value 
during access to an external memory, the value is act ually rewritten and reflected on the operation after the 
accessing process of the external memo ry is finished and then a time period of a few PCLK cycles passes. 
Read the register value to check that the rewriting has actually been applied to the operation. 
Ta b l e  7 - 1  lists the registers. 
Table 7-1 Register list 
Abbreviation Register name See 
MODE0 to MODE7  Mode Register 0 to Mode Register 7  7.1 
TIM0 to TIM7 Timing Register 0 to Timing Register 7  7.2 
AREA0 to AREA7 Area Register 0 to Area Register 7  7.3 
 
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7. Registers 
 
7.1.  Mode Register 0 to Mode Register 7 
The following shows the configuration of the Mode Register (0 to 7). 
 
bit 31 30 29 28 27 26 25242322 21 20 19 18 17 16 
Field Reserved 
Attribute - 
Initial  value  - 
                 
bit 15 14 13 12 11 10 9 876 5 4 3 2 1 0 
Field Reserved TESTPAGENAND
WEOFF RBMON WDTH 
Attribute -  R/WR/W 
Initial 
value  - 0 0 0 0 0 0*1 
 
[bit 6] TEST 
Always set this bit to 0. It must not be set to 1. 
The read value is 0. 
 
[bit 5] PAGE (PAGE access mode): NOR flash memory page access mode 
This bit controls the mode of NOR flash memory page access. 
In NOR flash memory page access mode, the first read  access cycle (FRADC) setting can generate the first 
address cycle. Subsequently, the  read access cycle (RACC) setting can  continue the access until it reaches 
the 16-byte boundary. 
When you select NOR flash memory page access mode, set the RBMON bit to 0 and the read access 
cycle (RADC) to 0. 
Bit Description 
0  NOR flash memory page access mode is turned OFF (Initial value) 
1 NOR flash memory page access mode is turned ON 
 
[bit 4] NAND: NAND flash memory mode 
This bit controls the mode used to connect with a NAND flash memory. 
To enable the access to a NAND flash memory, set this bit to 1. 
In NAND flash memory mode, the corresponding MCSX is fixed to LOW and, subsequently, the pin 
dedicated to the NAND flash memory is used during  the access. If this bit is set to 0 while the NAND 
flash memory is unused, then MCSX is fixed to HIGH, enabling the NAND flash memory to maintain a 
low power consumption state. 
Bit Description 
0  NAND flash memory page mode is turned OFF (Initial value) 
1 NAND flash memory mode is turned ON 
 
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7. Registers 
 
[bit 3] WEOFF (WEX OFF): Write Enable OFF 
This bit can disable the write enable signal (MWEX) operation. 
When the byte mask signal (MDQM) is used as a de vice write enable signal, disabling unnecessary MWEX 
operation can reduce current consumption. When this bit is set to disable, MWEX is fixed to HIGH. 
Bit Description 
0  Enable [Initial value] 
1 Disable 
 
[bit 2] RBMON: Read Byte Mask ON 
This bit can enable the byte mask signal (MDQM) for read access. 
The setting controls the output of u nnecessary data from a device for whic h the byte mask signal is enabled. 
This is helpful to reduce power consumption. 
Bit Description 
0 Disable [Initial value] 
1 Enable 
 
[bit 1:0] WDTH: Data Width 
These bits specify the data bit width of a device to be connected. 
Bit 1  Bit 0 Description 
0 0 8 bits [Initial value] 
0 1  16 bits 
1 0 Setting disabled 
1 1 Setting disabled 
 
 
If you write a 

disabled value to a TEST or WDTH bit, operation of the exte rnal bus int
 erface is not 
guaranteed. 
 
 
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7. Registers 
 
7.2.  Timing Register 0 to Timing Register 7 
The following shows the configuration of the Timing Register (0 to 7). 
 
bit 31 30 29 28 27 2625242322212019 18 17 16
Field WIDLC WWEC WADC WACC 
Attribute R/W 
Initial  value  0000 0101 0101 1111 
                 
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field RIDLC FRADC RADC RACC 
Attribute R/W 
Initial  value  1111 0000 0000 1111 
 
[bit 31:28] WIDLC: Write Idle Cycle 
These bits set the number of idle cycles after write access. 
Bit 31  Bit 30 Bit 29 Bit 28 Description 
0 0 0 0 1 cycle [Initial value] 
...  ... 
1 1 1  1 16 cycles 
 
  [bit 27:24] WWEC: Write Enable Cycle 
These bits set the number of assert cycles of write enable. 
The setting of these bits affects the byte mask signal (MDQM). 
Bit 27  Bit 26 Bit 25 Bit 24 Description 
0 0 0 0 1 cycle 
...  ... 
0  1 0 1 6 cycles [Initial value] 
... 
... 
1 1 1  0 15 cycles 
1 1 1  1 Setting disabled 
 
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7. Registers 
 
[bit 23:20] WADC: Write Address Setup cycle 
These bits set the number of setup cycles of write address. 
The address is output during the cycle set by these bits, but a write enable signal is not asserted until the set 
cycle starts. 
Bit 23 Bit 22 Bit 21 Bit 20 Description 
0 0 0 0 1 cycle 
...  ... 
0  1 0 1 6 cycles [Initial value] 
... 
... 
1 1 1  0 15 cycles 
1 1 1  1 Setting disabled 
 
[bit 19:16] WACC: Write Access Cycle 
These bits set the number of cycles required for write access. 
The address remains unchanged duri ng the cycle set by these bits. 
The number of cycles set by these bits must be equa l to or more than the sum of the address setup cycle 
(WADC) and the write enable cycle (WWEC). 
Bit 19  Bit 18 Bit 17 Bit 16 Description 
0 0 0 0 Setting disabled 
0 0 0  1 Setting disabled 
0 0 1  0 3 cycles 
...  ... 
1  1 1 1 16 cycles [Initial value] 
 
[bit 15:12] RIDLC: Read Idle Cycle 
These bits set the number of idle cycles after read access. 
They are used to avoid data collision caused by a  write access occurring immediately after a read access. 
Bit 15 Bit 14 Bit 13 Bit 12 Description 
0 0 0 0 1 cycle 
...  ... 
1  1 1 1 16 cycles [Initial value] 
 
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7. Registers 
 
[bit 11:8] FRADC: First Read Address Cycle 
These bits exclusively set a NOR flash memory that supports page mode access. 
They set the initial wait time of the address during read access to flash memory. 
The address for the set cycle is retained only during  the first cycle. After the first access, the access is 
performed according to the numb er of cycles set by RACC. 
In page mode access, MCSX and MOEX are asserted simultaneously. 
If values other than 0 is set to these bits , set the read access setup cycle (RADC) to 0. 
Bit 11 Bit 10  Bit 9 Bit 8 Description 
0 0 0 0 0 cycles [Initial value] 
...  ... 
1 1 1  1 15 cycles 
 
[bit 7:4] RADC: Read  Address Setup cycle 
These bits set the number of se tup cycles of read address. 
Within the read address setup cycle, MCSX and address  are asserted but MOEX is not asserted. If 0 is set 
to any of these bits, MOEX an d MCSX are always asserted. 
The set value must be less than the numb er of read access cycles. (RADC < RACC). 
When using NOR flash memory page acces s mode, set these bits to 0b0000. 
If the access size is more than the target width, or if  a device such as NAND flash memory needs to switch 
HIGH and LOW of read enable (MOEX or MNREX), set these bits to 0b0001 or a higher value. 
Bit 7  Bit 6Bit 5 Bit 4 Description 
0 0 0 0 0 cycles [Initial value] 
... 
... 
1 1 1  1 15 cycles 
 
[bit 3:0] RACC: Read Access Cycle 
These bits set the number of cycles required for read access. 
The address remains unchanged during th e cycle specified by these bits, and the data is captured at the last 
cycle. 
Bit 3  Bit 2Bit 1 Bit 0 Description 
0 0 0  0 1 cycle 
...  ... 
1  1 1 1 16 cycles [Initial value] 
 
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