Fujitsu Series 3 Manual
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FUJITSU SEMICONDUCTOR LIMITED
4.1. Clock Selection Register (CLK_SEL)
The clock selection register (CLK_SEL) selects the input clock (FCL) and sets the division
clocks (WCCK0 to 3) to be output.
bit 15 to 11 10 9 8
Field res res SEL_OUT
Attribute R/W R/W R/W
Initial value 0b00000 0b00 0
bit 7 to 1 0
Field res SEL_IN
Attribute R/W R/W
Initial value 0b0000000 0
[bit15:11, bit7:1] res : Reserved bits 0 is always read.
Writing is ignored.
[bit10: 9] res : Reserved bits Always...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-408.png "Page 409
FUJITSU SEMICONDUCTOR LIMITED
4.1. Clock Selection Register (CLK_SEL)
The clock selection register (CLK_SEL) selects the input clock (FCL) and sets the division
clocks (WCCK0 to 3) to be output.
bit 15 to 11 10 9 8
Field res res SEL_OUT
Attribute R/W R/W R/W
Initial value 0b00000 0b00 0
bit 7 to 1 0
Field res SEL_IN
Attribute R/W R/W
Initial value 0b0000000 0
[bit15:11, bit7:1] res : Reserved bits 0 is always read.
Writing is ignored.
[bit10: 9] res : Reserved bits Always...")
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4. Registers of the Watch Counter Prescaler
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: Watch Counter Prescaler
FUJITSU SEMICONDUCTOR CONFIDENTIAL 9
4.2. Division Clock Enable Register (CLK_EN)
The division clock enable register (CLK_EN) is a register to enable a count down of the
division counter.
bit 7 to 2 1 0
Field res CLK_EN_R CLK_EN
Attribute R/W R/W R/W
Initial value 0b000000 0 0
[bit7:2] res : Reserved bits 0 is always read.
Writing is ignored.
[bit1] CLK_EN_R : Division...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-409.png "Page 410
4. Registers of the Watch Counter Prescaler
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER: Watch Counter Prescaler
FUJITSU SEMICONDUCTOR CONFIDENTIAL 9
4.2. Division Clock Enable Register (CLK_EN)
The division clock enable register (CLK_EN) is a register to enable a count down of the
division counter.
bit 7 to 2 1 0
Field res CLK_EN_R CLK_EN
Attribute R/W R/W R/W
Initial value 0b000000 0 0
[bit7:2] res : Reserved bits 0 is always read.
Writing is ignored.
[bit1] CLK_EN_R : Division...")
1. Overview of the Watch Counter CHAPTER: Watch Counter This chapter explains the functions and operations of the watch counter. 1. Overview of the Watch Counter 2. Configuration of the Watch Counter 3. Interrupts of the Watch Counter 4. Explanation of Operations and Setting Pr ocedure Examples of the Watch Counter 5. Registers of the Watch Counter CODE: 9BFWC-E01.2_FW09-J00.4 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 375 MB9Axxx/MB9Bxxx Series
1. Overview of the Watch Counter 1. Overview of the Watch Counter The watch counter is a timer that counts down starting from the specified value, and it generates an interrupt request at the time that the 6-bit down counter enters an underflow condition. Watch counter For the watch counter, one of the four types of clock (WCCK0, WCCK1, WCCK2, and WCCK3) selected by the CS1 and CS0 bits of the watch counter control register (WCCR) is used as a count clock of the 6-bit down counter. A number between 0 and 63 can be set as the value used for counting by the 6-bit down counter. If 60 is the count value used for a counting period of 1 sec ond, an interrupt request is generated at an interval of 1 minute. If 0 is the count value used for a counting period of 1 second, an interrupt request is generated at an interval of 64 seconds An interrupt request can be generated at the time that the 6-bit down counter enters an underflow condition. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 376 MB9Axxx/MB9Bxxx Series
2. Configuration of the Watch Counter 2. Configuration of the Watch Counter This section shows the watch counter block diagram. Block diagram of the watch counter Figure 2-1 shows a block diagram of the watch counter. Figure 2-1 Block diagram of the watch counter Internal bus WCIF WCIE CS0 CS1 WCOP WCEN Count clock selection 6-bit down counter Underflow Interrupt request Counter clearing RLC5 RLC4 RLC3 RLC2 RLC1 RLC0 CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 Counter value Reload value Enabling of interrupts Watch counter reload register Watch counter read register Watch counter control register WCCK0 WCCK1 WCCK2 WCCK3 WCCK 0 to 3 : Count clock (before selection) 6-bit down counter This is the 6-bit down counter of the watch counter. It reloads the value set in the watch counter reload register (WCRL) and starts counting down. Watch counter reload register (WCRL) This register specifies the value used by the watch co unter to start counting. The 6-bit down counter counts down starting from the value set in this register. Watch counter read register (WCRD) This register reads the value in the 6-bit down counte r. Also, the register can be read to check the count value. Watch counter control register (WCCR) This register controls the operation of the watch counter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 377 MB9Axxx/MB9Bxxx Series
3. Interrupts of the Watch Counter 3. Interrupts of the Watch Counter The 6-bit down counter enters an underflow condition when the value in the 6-bit down counter becomes 0b000001, and an underflow interrupt request is then generated. Interrupts of the watch counter Ta b l e 3 - 1 outlines the interrupts that can be used with the watch counter. Table 3-1 Interrupts of the watch counter Interrupt request Interrupt request flag Interrupt request enabled Clearing an interrupt request Underflow interrupt request WCIF=1 for WCCR WCIE=1 for WCCR Write 0 to the WCIF bit for WCCR WCCR : Watch counter control register If ge neration of interrupt requests is enabled while the in terrupt request flag is 1, an interrupt request is generated at the same time. To enable generation of the interrupt request, do either of the following. Clear interrupt requests before enablin g the generation of interrupt requests. Clear interrupt requests simultaneously with interrupts enabled. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 378 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 4. Explanation of Operations and Setting Procedure Examples of the Watch Counter This section explains operations of the watch counter. Also, examples of procedures for setting the operating state are shown. Setting procedure examples of the watch counter To operate the watch counter, follow the procedure below. (1) Select a count clock by using the CS1 and CS0 bits of the watch counter control register (WCCR). (2) Set a count value to the RLC5 to RLC0 bits in the watch counter reload register (WCRL). (3) Enable the operation of the watch counter by usin g the WCEN bit (WCEN = 1) of the watch counter control register (WCCR). Start a countdown. Counting is performed at the rising edge of the count clock. (4) If the 6 -bit down counter enters an underflow condition, the value of the WCIF bit in the watch counter control register (WCCR) is changed to 1. At this time, if generation of underflow interrupt requests has been enabled by the WCIE bit in the watch counter control register (WCCR), an underflow interrupt request is generated. Also, the value that is set in the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is reloaded in the 6-bit down counter and the countdown is restarted. (5) If the value of the RLC5 to RLC0 bits in the watch counter reload register (WCRL) is changed to another value while the watch counter is active, the watch counter is updated with the new value at the next reload time. (6) The underflow interrupt request is cleared when 0 is written to the WCIF bit in the watch counter control register (WCCR). (7) The 6-bit down counter is cleared to 0b000000 and the counting operation is stopped when 0 is written to the WCEN bit in the watch counter control register (WCCR). CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 379 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Figure 4-1 shows the operation of the watch counter. Figure 4-1 Operation explanation figure of the watch counter WCEN bit Count clock CS1 and CS0 bits(1) RLC5 to RLC0 bits CTR5 to CTR0 bits WCIF bit 0 7 65432198765 4 7 9 (4) (6) (5) (3) (7) (2) The peri phe ral clock (PCLK) is used for the settings of each register of the watch counter. Since the count cl oc k and peripheral clock (PCLK) are not synchronized, an error of up to 1T (T: Count clock period) may occur at the count start time, depending on the time at which 1 is written to the WCEN bit in the watch counter control register (WCCR). Even at transition of the timer mode, the watch counte r continues operating as long as the main clock or sub clock is operating. The timer mode can be canceled with the watch counter interrupt processing routine. Under the following condition, verify that the watch counter is stopped by checking the WCOP bit (WCOP=0) in the watch counter control register (WCCR) before reactivating the watch counter. Condition: In case of activating the watch counter af ter the watch counter is stopped by writing 0 to the WCEN in the watch counter control register (WCCR) by using the WCEN bit (WCEN = 1). CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 380 MB9Axxx/MB9Bxxx Series
5. Registers of the Watch Counter 5. Registers of the Watch Counter This section explains the registers for the watch counter. List of the registers for the watch counter Table 5-1 List of registers for the watch counter Abbreviated Register Name Register Name See WCRD Watch counter read register 5.1 WCRL Watch counter reload register 5.2 WCCR Watch counter control register 5.3 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 381 MB9Axxx/MB9Bxxx Series
5. Registers of the Watch Counter 5.1. Watch Counter Read Register (WCRD) This register reads the value in the 6-bit down counter. bit 7 6 5 4 3 2 1 0 Field res CTR5 CTR4 CTR3 CTR2 CTR1 CTR0 Attribute R R R R R R R Initial value 0b00 0 0 0 0 0 0 [bit7:6] res : Reserved bits 0 is always read. Writing is ignored. [bit5:0] CTR5 to CTR0 : Counter read bits These bits can read the counter value. Writing is ignored. If the 6-bit down counter is operating when its value is read, the register value m ust be read twice and verified to be the same value. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 382 MB9Axxx/MB9Bxxx Series
5. Registers of the Watch Counter 5.2. Watch Counter Reload Register (WCRL) This register specifies the value used by the watch counter to start counting. The 6-bit down counter counts down starting from the value set in the register. The register specifies the reload va lue for the 6-bit down counter. If the 6-bit down counter enters an underflow condition, the value in this register is re loaded in the 6-bit down counter, and the countdown is restarted. bit 15 14 13 12 11 10 9 8 Field res RLC5 RLC4 RLC3 RLC2 RLC1 RLC0 Attribute R/W R/W R/W R/W R/W R/W R/W Initial value 0b00 0 0 0 0 0 0 [bit15:14] res : Reserved bits 0 is always read. Writing is ignored. [bit13:8] RLC5 to RLC0 : Counter reload value setting bit These bits set the reload value for the 6-bit down counter. The 6-bit counter counts downwards from the reload value and enters an underflow condition when its value reaches 1. If 0 is set in these bits, it performs 64 countdowns from 63 to 0. If this bit is modified during counting, the modified value is valid at reloading after underflow. If th e value of these bits is changed to another value while the 6-bit down counter is active, an underflow occurs and the new val ue is then reloaded. If the value of RLC bit is changed to another value at the same time that an underflow interrupt request is generated, the correct value is not reloaded. Be sure to rewrite the value of RLC bit either when the watch counter is stopped or in the interrupt processing routine before an interrupt request is generated. To verify whether the reload value is correctly set, read this register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 383 MB9Axxx/MB9Bxxx Series
5. Registers of the Watch Counter 5.3. Watch Counter Control Register (WCCR) This register selects a count clock for the watch counter or enables/disables generation of interrupt requests. The register also enables/disables the operation of the watch counter. bit 23 22 21 20 19 18 17 16 Field WCEN WCOP res CS1 CS0 WCIE WCIF Attribute R/W R R R/W R/W R/W R/W Initial value 0 0 0b00 0 0 0 0 [bit23] WCEN : Watch counter operation enable bit This bit enables the operation of the watch counter. The peripheral clock (PCLK) is used for the settings of each register of the watch counter. Since the count clock and the peripheral clock (PCLK) are not synchronized, an error of up to 1T (T: count clock period) may occur at the count start time, depending on the time at which 1 is written to WCEN bit of watch counter control register (WCCR). Before writing 1 to this bit to start the operation of the watch counter, verify that the watch counter is stopped by checking the WCOP bit (WCOP=0). bit Explanation 0 The watch counter is disabled/stopped. The value in the 6-bit down counter is cleared to 0b000000. 1 The watch counter is enabled/started. [bit22] WCOP : Watch counter operating state flag This bit indicates the operatin g state of the watch counter. bit Explanation 0 The watch counter is stopped. 1 The watch counter is active. [bit21:20] res : Reserved bits 0 is always read. Writing is ignored. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 13-2: Watch Counter MN706-00002-1v0-E 384 MB9Axxx/MB9Bxxx Series