Fujitsu Series 3 Manual
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4. Registers
4.1. I/O Select Register (BTSEL0123)
This register selects the I/O mode for channels 0 to 3 of the base timer.
Register configuration
bit 15 14 13 12 11 10 9 8
Field SEL23_3SEL23_2 SEL23_1 SEL23_0SEL01_3SEL01_2 SEL01_1 SEL01_0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Register functions
[bit 15:12] SEL23_3 to SEL23_0: I/O select bits for Ch.2/Ch.3
Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-444.png "Page 445
4. Registers
4.1. I/O Select Register (BTSEL0123)
This register selects the I/O mode for channels 0 to 3 of the base timer.
Register configuration
bit 15 14 13 12 11 10 9 8
Field SEL23_3SEL23_2 SEL23_1 SEL23_0SEL01_3SEL01_2 SEL01_1 SEL01_0
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
Register functions
[bit 15:12] SEL23_3 to SEL23_0: I/O select bits for Ch.2/Ch.3
Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit...")
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4. Registers
[bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0
0 0 1 I/O mode 1
(Timer full mode)
0
0 1 0 I/O mode 2
(Shared external trigger mode)
0
0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0
1 0 0 I/O mode 4
(Timer start/stop mode)
0
1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0
1 1 0 I/O mode 6
(Software-based startup an
d timer...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-445.png "Page 446
4. Registers
[bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1
Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit
0 0 0 0 I/O mode 0
(Standard 16-bit timer mode)
0
0 0 1 I/O mode 1
(Timer full mode)
0
0 1 0 I/O mode 2
(Shared external trigger mode)
0
0 1 1 I/O mode 3
(Shared channel signal trigger mode)
0
1 0 0 I/O mode 4
(Timer start/stop mode)
0
1 0 1 I/O mode 5
(Software-based simultaneous startup mode)
0
1 1 0 I/O mode 6
(Software-based startup an
d timer...")
3. I/O Mode I/O mode 7 (Timer start mode) This mode uses the output waveform from the even channel (TOUT signal) as input signals (ECK/TGIN/TIN signals) of the odd channel. Table 3-23 shows the external pins used when this mode is selected. Table 3-23 External pins used when I/O mode 7 is selected. Even channel Odd channel Number of input pins 1 Not used Number of output pins 1 1 Table 3-24 shows the internal signals to which the external pins connect, and signals input or output. Table 3-24 External pin connections and input/output signals when I/O mode 7 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn Input Even channel ECK/ TGIN/TIN * Input to the even channel and used as one of the following signals: External clock (ECK signal) External startup trigger (TGIN signal) Waveform to be measured (TIN signal) TIOBn+1 - - Not used n : Even * : The usage of input waveforms (ECK/TGIN/TIN signals) differs depending on the Timer Control Register (TMCR) setting. Figure 3-9 shows the block diagram of I/O mode 7 (Timer start mode). Figure 3-9 I/O mode 7 (Timer start mode) block diagram ECK TGIN TIN TOUT ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.nTIOBn+1 TIOAn+1 TIOBn TIOAn COUT n: Even Table 3-25 shows signal connections in I/O mode 7. Table 3-25 I/O mode 7 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin Input to Ch.n+1 as ECK/TGIN/TIN signals Output to another channel as a COUT signal Input signal from the TIOBn pin Input to Ch.n as ECK/TGIN/TIN signals Ch.n+1 TOUT signal Output from the TIOAn+1 pin n : Even The start timing of Ch.n is the same as that for I/O mode 4. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 405 MB9Axxx/MB9Bxxx Series
3. I/O Mode I/O mode 8 (Shared channel signal trigger and timer start/stop mode) This mode inputs the COUT signal from channels below the two channels as a CIN signal, and uses it as an external startup trigger (TGIN signal). Table 3-26 shows the external pins used when this mode is selected. Table 3-26 External pins used when I/O mode 8 is selected. Even channel Odd channel Number of input pins Not used Number of output pins 1 1 Table 3-27 shows the internal signals to which the external pins connect, and signals input or output. Table 3-27 External pin connections and input/output signals when I/O mode 8 is selected. External pin I/O Connected to (internal signal) Signal input/output TIOAn Output Even channel TOUT Outputs the even channel waveform TIOAn+1 Output Odd channel TOUT Outputs the odd channel waveform TIOBn TIOBn+1 - - Not used n : Even Figure 3-10 shows the block diagram of I/O mode 8 (Shared channel signal trigger and timer start/stop m ode). Figure 3-10 I/O mode 8 (Shared channel signal trigger and timer start/stop mode) block diagram DTRG ECK TGIN TIN TOUT DTRG ECK TGIN TIN TOUT Base timer Ch.n+1 Base timer Ch.n TIOBn+1 TIOAn+1 TIOBn TIOAn COUT CIN n: Even Table 3-28 shows signal connections in I/O mode 8. Table 3-28 I/O mode 8 signal connections Signal Connected to Ch.n TOUT signal Output from the TIOAn pin Ch.n+1 TOUT signal Output from the TIOAn+1 pin CIN signal * Input to Ch.n and Ch.n+1 as ECK/TGIN/TIN and DTRG signals Output to another channel as a COUT signal n : Even * : The COUT signal from another channel is input as a CIN signal. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 406 MB9Axxx/MB9Bxxx Series
3. I/O Mode
The following shows Ch.n-2/n-1 signals that can be input to ECK/TGIN/TIN of Ch.n/n+1.
Signal that the peripheral clock generates by synchronizing TIOBn-2 input in I/O mode 2.
Trigger signal input from Ch.n-4/n-3 in I/O mode 3.
TIOAn-2 output in I/O mode 4.
TIOAn-2 output in I/O mode 6.
TIOAn-2 output in I/O mode 7.
Trigger signal input from Ch.n-4/n-3 in I/O mode 8.
The ch a
nnels set to this mode use the COUT signal from lower 2 channels (n-2 and n-1) as a CIN signal.
(Example :
If channels 2 and 3 are set to this mode, they use the COUT signal from channels 0 and 1.)
Therefore, channels 0 and 1 cannot be set to this mode.
Select the rising edge as a trigger input edge, for the channel set in this mode, using the EGS1 and EGS0
bits in the Timer Control Register (TMCR) of th e base timer. (Set EGS1 and EGS0 to 0b01.)
However, do not enable this setting if the timer func tion is set to the 16/32-bit PWC timer using FMD2 to
FMD0 bits in the Timer Control Register (TMCR) of the base timer (FMD2 to FMD0 are set to 0b100).
Base timer stops operating when a falling edge is detected in the DTRG signal.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-1: Base Timer I/O Select Function
MN706-00002-1v0-E
407
MB9Axxx/MB9Bxxx Series
4. Registers 4. Registers This section provides the register list of the base timer I/O select function. Base Timer I/O Select Function Registers Table 4-1 Base timer I/O select function register list Abbreviation Register name See BTSEL0123 I/O Select Register 4.1 BTSEL4567 I/O Select Register 4.2 BTSSSR Software-based Simultaneous Startup Register 4.3 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 408 MB9Axxx/MB9Bxxx Series
4. Registers 4.1. I/O Select Register (BTSEL0123) This register selects the I/O mode for channels 0 to 3 of the base timer. Register configuration bit 15 14 13 12 11 10 9 8 Field SEL23_3SEL23_2 SEL23_1 SEL23_0SEL01_3SEL01_2 SEL01_1 SEL01_0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Register functions [bit 15:12] SEL23_3 to SEL23_0: I/O select bits for Ch.2/Ch.3 Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer start/stop mode) 0 1 1 1 I/O mode 7 (Timer start mode) 1 0 0 0 I/O mode 8 (Shared channel signal trigger and timer start/stop mode) Others Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 409 MB9Axxx/MB9Bxxx Series
4. Registers [bit 11:8] SEL01_3 to SEL01_0: I/O select bits for Ch.0/Ch.1 Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer start/stop mode) 0 1 1 1 I/O mode 7 (Timer start mode) 1 0 0 0 I/O mode 8 (Shared channel signal trigger and timer start/stop mode) Others Setting disabled Ch an nels 0 and 1 are the lowest channels of the base timer, and cannot use the modes that use signal from lower ch an nels. Therefore, the following modes cannot be selected for the channels: I/O mode 3 (Shared channel signal trigger mode) I/O mode 8 (Shared channel signal trigger and timer start/stop mode) Before rewriting this register, set the base timer to reset mode using the FMD2 to FMD0 bits in the Timer Control Register (TMCR) of the base timer. (Set FMD2 to FMD0 to 0b000.) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 410 MB9Axxx/MB9Bxxx Series
4. Registers 4.2. I/O Select Register (BTSEL4567) This register selects the I/O mode for channels 4 to 7 of the base timer. Register configuration bit 15 14 13 12 11 10 9 8 Field SEL67_3SEL67_2 SEL67_1 SEL67_0SEL45_3SEL45_2 SEL45_1 SEL45_0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Register functions [bit 15:12] SEL67_3 to SEL67_0: I/O select bits for Ch.6/Ch.7 Bit 15 Bit 14 Bit 13 Bit 12 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer start/stop mode) 0 1 1 1 I/O mode 7 (Timer start mode) 1 0 0 0 I/O mode 8 (Shared channel signal trigger and timer start/stop mode) Others Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 411 MB9Axxx/MB9Bxxx Series
4. Registers [bit 11:8] SEL45_3 to SEL45_0: I/O select bits for Ch.4/Ch.5 Bit 11 Bit 10 Bit 9 Bit 8 I/O select bit 0 0 0 0 I/O mode 0 (Standard 16-bit timer mode) 0 0 0 1 I/O mode 1 (Timer full mode) 0 0 1 0 I/O mode 2 (Shared external trigger mode) 0 0 1 1 I/O mode 3 (Shared channel signal trigger mode) 0 1 0 0 I/O mode 4 (Timer start/stop mode) 0 1 0 1 I/O mode 5 (Software-based simultaneous startup mode) 0 1 1 0 I/O mode 6 (Software-based startup an d timer start/stop mode) 0 1 1 1 I/O mode 7 (Timer start mode) 1 0 0 0 I/O mode 8 (Shared channel signal trigger and timer start/stop mode) Others Setting disabled Before rewriting th is register, set the base timer to reset mo d e using the FMD2 to FMD0 bits in the Timer Control Register (TMCR) of the base timer. (Set FMD2 to FMD0 to 0b000.) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 412 MB9Axxx/MB9Bxxx Series
4. Registers FUJITSU SEMICONDUCTOR LIMITED Chapter: Base Timer I/O Select Function FUJITSU SEMICONDUCTOR CONFIDENTIAL 28 4.3. Software-based Simultaneous Startup Register (BTSSSR) This register starts up multiple base timer channels using software. Up to 16 channels can be started simultaneously if the bits corresponding to the channel are set to 1. Register configuration bit 15 - 0 Field SSSR15 to 0 Attribute W Initial value X Register functions [bit 15:0] SSSR15 to SSSR0: Softwa re-based simultaneous startup bit SSSRx Software-based simultaneous startup bit 0 Writing 0 to this bit is invalid 1 Starts Ch.x of the base timer x : 15 to 0 Do not write to this register unless set to either of the following modes: I/O mode 5 (Software-based simultaneous startup mode) I/O mode 6 (Software-based startup and timer start/stop mode)(Even channels only) For the channel started up by using this register, select the rising edge as a trigger input edge using the EGS1 and EGS0 bits in the Timer Control Register (T MCR) of the base timer. (Set EGS1 and EGS0 to 0b01.) CHAPTER 14-1: Base Timer I/O Select Function MN706-00002-1v0-E 413 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 414 MB9Axxx/MB9Bxxx Series