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5. Usage Precautions 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: I/O PORT 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  65 
  Rreserved Bit 
This bit is read out as 0 except for the ADE rese rved bit. When writing, always write 0. The ADE 
reserved bit is read out as 1.  When writing, always write 1. 
 Connecting External Bus Pin and SRAM 
When accessing SRAM via external bus, either perform pull-up setting for the pin or connect it to external 
pull-up pin. 
  Multi-function Serial Pin Group 
When there are some multi-function serial inputs/output s, set each input/output to the port of the same 
group. The port of the same group means that relo cate function numbers attached to the pin name are the 
same, just like xxx_0 or yyy_1. 
The following  Ta b l e  5 - 1 shows example setting.   
Table 5-1 Multi-function Serial Interface example setting 
Serial Data Output Serial Clock  Input/Output  Serial Data Input   Effective Port   
 
Pin SIN1_0 
(Port 0)  Port 0 
 Pin SCK1_
0 
(Port 0) 
Pin SIN1_1 
(Port 1) 
Pin SIN1_0 
(Port 0) 
Pin SOUT1_ 0 
(Port 0) 
Pin SCK1_1 
(Port 1) 
Pin SIN1_1 
(Port 1) 
Pin SIN1_0 
(Port 0) 
Pin SCK1_0 
(Port 0) 
Pin SIN1_1 
(Port 1) 
Pin SIN1 
(Port 0) 
Setting Disabled 
Pin SOUT1_ 1 
(Port 1) 
Pin SCK1_1 
(Port 1) 
Pin SIN1_1 
(Port 1)  Port 1 

 Peripheral Function Output 
As output pins for peripheral functions are uniquely determined by EPFR settings, Output for peripheral 
functions cannot be assigned to separate pins.   
(Disabled example) Assign multifunction serial output SOUT1_0 and SOUT1_1 to the same output.   
  Pin Settings and Operation Mode 
For JTAG settings, see Chapter Debug.   
For state of each pin during standby  mode or reset, see Data Sheet. 
 Product Specifications and Peripheral Function Assignment 
Functions which are assigned to pins (GPO, peripheral output and I/O) vary in different products. 
Please see the pin function table of the data sheet to confirm the pin function of each product. 
Do not select a function for a pin which is not available in your product by using the EPFR register setting. 
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Chapter: Clock supervisor 
This chapter explains clock supervisor functions. 
 
1.
 Overview 
2. Configurations and Block Diagrams 
3. Explanation of Operations 
4. Setup Procedure Examples 
5. Operation Examples 
6. Register list 
7. Usage Precautions 
   
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFCSV-E02.1 
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1. Overview 
This section provides an overview of clock supervisor functions. 
The clock supervisor includes the following two types of functions. 
 Clock failure detection (CSV: Clock failu re detection by clock Super Visor) 
The clock failure detection monitors the main and sub clocks. If a rising edge of the monitored clock is not 
detected within the specified period, this function determines that the oscillator has failed, and outputs a 
system reset request. 
 Anomalous frequency detection (FCS: anomalous Frequency detection by 
Clock Super visor) 
The anomalous frequency detection monitors frequency of the main clock. Within the specified period 
between an edge and the next edge of the divided clock of high-speed CR, this function counts up the 
internal counter value using the main clock. If the count value reaches out of  the set window range, the 
function determines that the main clock frequency is anomalous, and outputs an interrupt request or a 
system reset request to the CPU. 
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2.  Configurations and Block Diagrams 
This section explains the block diagrams of clock supervisor functions. 
 Clock failure detection 
Figure 2-1  shows the block diagram of the clock failure detection. 
Figure 2-1 Clock Failure Detection Block Diagram 
 
Main clock 
counter
Control circuit/ registers
Sub clock counter
Main OSC
Sub OSC
Low-speed CR CSV_RESET
High-speed CR
  
 
The clock failure detection consists of the following three types of blocks. 
 Control circuit/registers 
  This block includes a circuit controlling clock failure detection, 
   Also includes setup registers enabling/disabling the clock failure detection. 
 Main clock counter 
A counter that monitors the main clock with the high-speed CR clock. 
 Sub clock counter 
A counter that monitors the sub clock with the low-speed CR clock. 
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 Anomalous frequency detection 
Figure 2-2  shows the block diagram of the anomalous frequency detection. 
Figure 2-2 Anomalous Frequency Detection Block Diagram 
 
Frequency 
counter
Control circuit/registers and 
window registers
Edge 
detectiondivider
FCS_RESET
FCS_INT
Main OSC
High-speed CR
  
  The anomalous frequency detection consists of the following three types of blocks. 
 Control circuit/register s and window registers 
  This block includes a circuit controllin g the anomalous frequency detection. 
   Also includes setup registers enabling/disabling the anomalous frequency detection. 
   Also includes window registers defining the frequency range for measurements. 
 Frequency counter 
A counter based on the main clock. 
 Divider/edge detection 
  This block divides the high-speed CR. 
   Also detects rising edges of the divided clock of high-speed CR.  
 
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3.  Explanation of Operations 
This section explains the operations of clock supervisor functions. 
 Clock failure detection 
The clock failure detection monitors the main and sub clocks. If a rising edge of the monitored clock is not 
detected within the specified period, this function determines that the oscillator has failed, and outputs a 
system reset request. 
  This reset request is referred to as the CSV reset request. 
   CSV function monitors each of the main and sub clocks independently. 
   It stops monitoring when the main and sub oscillators stop oscillating. 
   It stops monitoring while waiting for oscillation stabilization wait time. 
   When the oscillation stabilization wait time of main and sub oscillators ends, CSV function is 
automatically enabled. 
 
 
  Each  of t
h

e main and sub clocks can be enabled/disabled independently using the CSV_CTL register. 
   The m
ai
n  cl

ock is monitored with the high-speed CR clock, and the sub clock is monitored with the 
low-speed CR clock. When a rising edge is not detected within 32 clocks of high-speed CR for the main 
clock, or within 32 clocks of low-speed CR for the sub clock, this function determines that the oscillator 
has failed. 
 
  Anomalous frequency detection 
The anomalous frequency detection monitors the main clock. 
Within the specified period between an edge and the next edge of the divided clock of high-speed CR, this 
function counts up the internal counter using the main  clock. If the count value reaches out of the set 
window range, the function determines that the main clock frequency is anomalous, and outputs an interrupt 
request or a system reset request to the CPU. 
   This interrupt request is referred to as the FCS in terrupt request, and reset request as the FCS reset 
request. 
   The FCS function only monitors frequency of the main clock. 
   It stops monitoring when the main oscillator stops oscillating. 
   It stops monitoring while waiting for oscillation stabilization wait time. 
   The FCS function is started with software, a user program. 
 
 
  If th e FC

S reset is enabled: 
An interrupt req u

est occurs the first time a counter va lue deviates from the set window. If the interrupt 
request has not been cleared, and th e counter value falls out of the specified window, a system reset 
request is output. 
If the FCS reset is not enabled, the reset request is masked. 
   The counter value, if it goes ou t of the specified window, is stored in the FCSWD_CTL register. 
 
 
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4.  Setup Procedure Examples 
This section explains examples of setting up clock supervisor functions. 
 Example clock failure detection setup procedure 
 
  
Stop Monitoring? 
Oscillation stabilization wait time of 
main and sub clocks end
No 
Ye s
No
End 
Access the CSV_CTL register 
Disable the enable bit 
Clock failure detection function  enables 
Failure Detected? 
Ye s  
The CSV reset occurs 
Enable main and sub clock oscillators 
Start 
 
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 Example frequency detection setup procedure 
 
 
Start 
 
 
Access CSV_CTL 
Enable/disable the FCS reset 
Access FCSWL_CTL 
Set lower frequency window 
Access INT_CLR 
Clear the FCS interrupt source 
End 
Access CSV_CTL 
Set FCD (Count Edge setting) 
Access FCSWH_CTL 
Set upper frequency window Is the count value out of the window? No
Ye s
Ye s 
Is the interrupt flag set? 
FCS interrupt occurs 
Restart interrupt handling/FCS function 
No
The FCS reset occurs 
Is the FCS reset enabled? No
Ye s
Access CSV_CTL 
Turn ON the FCS function 
Access INT_ENR 
Enable/disable the FCS interrupt 
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5. Operation Examples 
This section explains examples of clock supervisor operations. 
 Clock failure detection 
Figure 5-1  provides an example of cloc k failure detect ion operation. 
Figure 5-1 Example clock failure detection operation 
Main clock
High-speed  CR clock
Main clock is missing
32 x CR clocks
CSV reset
Reset occurs
 
1. The main clock stops due to failure. 
2.  The function counts up clocks using the high-speed CR clock. 
3.  If the main clock keeps stopping during 32 clocks of high-speed CR, the function determines that the 
clock has failed and issues the CSV reset. 
Note:  In case of the sub clock, the function determines that the sub clock has failed if it keeps stopping  during 32 clocks of low-speed CR. 
Figure 5-2  provides an example of the clock failu re detection 
o
 peration in stop mode. 
Figure 5-2 Example clock failure detection operation in stop mode 
 
Main clock 
(Sub clock)
High-speed  CR clock 
(Low-speed  CR clock)
Stop mode
Main (Sub) clock stops
High-speed CR clock stops 
(Low-speed CR clock stops)
RUN STOPWaiting for 
oscillation 
stabilization RUN
Waiting for oscillation 
stabilization
Clock monitoring is  activeClock monitoring is disabledClock monitoring is active
  
1. In stop mode, the main clock and high-speed CR clock stop. 
Meanwhile, the clock monitoring function also stops. 
2.  Upon the release of stop mode, oscillation of main  clock and CR clock restart, waiting for oscillation 
stabilization. Meanwhile, the clock monitoring function keeps stopping. 
3.  When the oscillation stabilization wait time ends, the clock monitoring restarts. 
 
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