Fujitsu Series 3 Manual
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FUJITSU SEMICONDUCTOR LIMITED
[bit 8] FCSDE: FCS function enable bit
bit Description
When 0 is written The FCS function is disabled [Initial value]
When 1 is written The FCS function is enabled.
When read The register value is read.
[bits 7:2] Reserved bits 0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1] SCSVE: Sub CSV function enable bit
bit Description
When 0 is written The sub CSV function is disabled
When 1 is written The sub CSV function is enabled....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-345.png "Page 346
FUJITSU SEMICONDUCTOR LIMITED
[bit 8] FCSDE: FCS function enable bit
bit Description
When 0 is written The FCS function is disabled [Initial value]
When 1 is written The FCS function is enabled.
When read The register value is read.
[bits 7:2] Reserved bits 0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1] SCSVE: Sub CSV function enable bit
bit Description
When 0 is written The sub CSV function is disabled
When 1 is written The sub CSV function is enabled....")
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6.2. CSV status register (CSV_STR)
The CSV_STR register indicates the status of CSV function.
Register configuration
bit 7 6 5 4 3 2 1 0
Field Reserved SCMF MCMF
Attribute - R R
Initial value 6b000000 1b0 1b0
Register functions
[bits 7:2] Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1] SCMF : Sub clock failure detection flag
bit Description
When written No effect
When 0 is read No sub clock failure...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-346.png "Page 347
FUJITSU SEMICONDUCTOR LIMITED
6.2. CSV status register (CSV_STR)
The CSV_STR register indicates the status of CSV function.
Register configuration
bit 7 6 5 4 3 2 1 0
Field Reserved SCMF MCMF
Attribute - R R
Initial value 6b000000 1b0 1b0
Register functions
[bits 7:2] Reserved bits
0b000000 is read from these bits.
Set these bits to 0b000000 when writing.
[bit 1] SCMF : Sub clock failure detection flag
bit Description
When written No effect
When 0 is read No sub clock failure...")
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6.3. Frequency detection window setting register (Upper) (FCSWH_CTL)
The FCSWH_CTL register configures the frequency detection window setting register
(Upper).
Register configuration
bit 15 0
Field FWH
Attribute R/W
Initial value 160xFFFF
Register functions
[bits 15:0] FWH: Frequency detection window setting bits (Upper)
bits 15:0 Description
When written Any value can be written to these bits.
When read The register value is read.
Set a...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-347.png "Page 348
FUJITSU SEMICONDUCTOR LIMITED
6.3. Frequency detection window setting register (Upper) (FCSWH_CTL)
The FCSWH_CTL register configures the frequency detection window setting register
(Upper).
Register configuration
bit 15 0
Field FWH
Attribute R/W
Initial value 160xFFFF
Register functions
[bits 15:0] FWH: Frequency detection window setting bits (Upper)
bits 15:0 Description
When written Any value can be written to these bits.
When read The register value is read.
Set a...")
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FUJITSU SEMICONDUCTOR LIMITED
6.4. Frequency detection window setting register (Lower) (FCSWL_CTL)
The FCSWL_CTL register configures the frequency detection window setting register (Lower).
Register configuration
bit 15 0
Field FWL
Attribute R/W
Initial value 160x0000
Register functions
[bits 15:0] FWL: Frequency detection window setting bits (Lower)
bits 15:0 Description
When written Any value can be written to these bits.
When read The register value is read.
Set a...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-348.png "Page 349
FUJITSU SEMICONDUCTOR LIMITED
6.4. Frequency detection window setting register (Lower) (FCSWL_CTL)
The FCSWL_CTL register configures the frequency detection window setting register (Lower).
Register configuration
bit 15 0
Field FWL
Attribute R/W
Initial value 160x0000
Register functions
[bits 15:0] FWL: Frequency detection window setting bits (Lower)
bits 15:0 Description
When written Any value can be written to these bits.
When read The register value is read.
Set a...")
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FUJITSU SEMICONDUCTOR LIMITED
6.5. Frequency detection counter register (FCSWD_CTL)
The FCSWD_CTL register indicates the counter value of frequency detection using the main
clock.
Register configuration
bit 15 0
Field FWD
Attribute R
Initial value 160x0000
Register functions
[bits 15:0] FWD: Frequency detection count data
bits 15:0 Description
When written No effect
When read The count value is read.
This reg
ister retains the count value when detecting an error.
...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-349.png "Page 350
FUJITSU SEMICONDUCTOR LIMITED
6.5. Frequency detection counter register (FCSWD_CTL)
The FCSWD_CTL register indicates the counter value of frequency detection using the main
clock.
Register configuration
bit 15 0
Field FWD
Attribute R
Initial value 160x0000
Register functions
[bits 15:0] FWD: Frequency detection count data
bits 15:0 Description
When written No effect
When read The count value is read.
This reg
ister retains the count value when detecting an error.
...")
7. Usage Precautions FUJITSU SEMICONDUCTOR LIMITED Chapter: Clock supervisor FUJITSU SEMICONDUCTOR CONFIDENTIAL 20 7. Usage Precautions This section explains the precautions for using clock supervisor functions. For details on enabling and clearing the frequency detection interrupt sources, see Chapter Clocks. For details on clock failure detection and anomalous frequency detection reset sources, see Chapter Resets. Operation after the occurrence of a reset. After the occurrence of a reset triggered by clock failure detection, clock mode returns to high-speed CR. Do not select the faulty clock again. The internal high-speed CR clock for use of the frequency detection The frequency failure detection is affected by the frequency accuracy of internal high-speed CR itself. When you configure frequency window, therefore, the accuracy of internal high-speed CR must be considered for th e window value. Do not trim the high-speed CR clock after the anomalous frequency detection has been enabled. The order of the frequency detection settings before using Before enabling FCS (FCSDE=1), specify the count cy cle (FCD), reset enable (FCSRE), and frequency window (FWH/FWL) settings. If you want to change any of FCD/FCSRE/FWH/FWL after FCS has been enabled, stop the FCS function before changing the setting. Do not change the setting while FCS is enabled. The enable settings of the anomalous frequency detection before using Depending on the setting of the FCSRE bit in the CSV control register (CSV_CTL), operation during anomalous frequency detection varies. Ta b l e 7 - 1 shows the setting list. Table 7-1 List of the FCS function and FCSRE bit settings FCSRE=0 FCSRE=1 FCSDE=0 Stops FCS function Stops FCS function FCSDE=1 Enables FCS function Generates an interrupt upon error detection Enables FCS function An interrupt occurs upon the first error detection A reset occurs upon the second error detection Interrupt settings for the frequency detection and main timer mode The internal bus clock stops while the clock is in main timer mode. In this mode, an interrupt does not occur even if an error is detected while FCSRE is set to 0. In main timer mode, therefore, do not set FCSRE to 0. If FCSRE is set to 1, a reset occurs. The settings for CSV OFF and external reset. When CSV function is set to OFF, the CSV reset is not generated, and moreover, the external reset (INITX) is not accepted. So, it is recommended not to turn OFF the CSV function, if you don’t have special reason. CHAPTER 10: Clock supervisor MN706-00002-1v0-E 315 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 316 MB9Axxx/MB9Bxxx Series
1. Overview CHAPTER: Watchdog timer This chapter describes the watchdog timer. 1. Overview 2. Configuration and Block Diagram 3. Operations 4. Setting Procedure Example 5. Operation Example 6. Registers 7. Notes CODE: 9BFWDT-E02.2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 317 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview This section describes the overview of the watchdog timer. The watchdog timer is a function to detect runaway of user program. If the watchdog timer is not cleared within the specified interval time, it judges that a user program is out of control, and outputs a system reset request or an interrupt request to CPU. This interrupt is called a watchdog in terrupt request, and a reset request is called a watchdog reset request. During watchdog timer operation, it is required to clear continually and periodically before the specified interval time has elapsed. If an abnormal operation of user program such as hanging up prevents it from being periodically cleared, it underflows and outputs a watchdog interrupt request or a watchdog reset request. This MCU has two kinds of watchdog timers as follows. Software watchdog timer The software watchdog timer is activated by user program. A divided clock of APB bus clock is used for a count clock. It counts cycles while CPU program is operating, and it stops counting while APB clock of the standby mode (timer mode, stop mode, and during oscillation stabilization wait time of the source clock). The count value is retained so that it continues counting after returning from the standby mode. The software watchdog timer is stopped by all the resets. Hardware watchdog timer The hardware watchdog timer is activated by tuning on the device, and after releasing all the resets except software resets without an intervention of software. The hardware watchdog timer can be stopp ed by accessing a register by software. Low-speed CR clock (CLKLC) is used for a count clock. It counts cycles while CLKLC is operated, and it st ops counting while CLKLC is stopped in the standby mode (stop mode). The count value is retained so that it continues counting after returning from the standby mode. Software/hardware watchdog timer Each watchdog timer has a lock register, accessing to a ll the registers of watchdog timers can not be done unless accessing and releasing a lock with a certain procedure. The watchdog timers can be re loaded by accessing to the watchdog clear register. When the first underflow of the watchdog counter is generated, an interrupt request is generated. When the second underflow is generated without clearing th e interrupt request, a reset request is generated. This function can be set by the register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 318 MB9Axxx/MB9Bxxx Series
2. Configuration and Block Diagram 2. Configuration and Block Diagram This section shows the configuration and block diagram of the watchdog timer. Figure 2-1 Block Diagram of Software Watchdog Timer FUJITSU SEMICONDUCTOR LIMITED APB bus SWDG reset SWDG interrupt TOOL break signal Software Watchdog Timer System reset APB interface 32bit down counter Control register Lock register Value register Load register Interrupt/ reset generation circuit Control logic/register SWDG clock Clear register CHAPTER 11: Watchdog timer MN706-00002-1v0-E 319 MB9Axxx/MB9Bxxx Series
2. Configuration and Block Diagram Figure 2-2 Block Diagram of Hardware Watchdog Timer FUJITSU SEMICONDUCTOR LIMITED Control register Hardware Watchdog Timer APB interface 32bit down counter Control register Lock register Value register Load register Interrupt/ reset generation circuit Control logic/register System reset TOOL break signal HWDG clock Clear register APB bus HWDG interruptHWDG reset CHAPTER 11: Watchdog timer MN706-00002-1v0-E 320 MB9Axxx/MB9Bxxx Series
3. Operations 3. Operations This section shows the operation of watchdog timer. The watchdog timer consists of the following blocks. Software Watchdog Timer Control register / logic This circuit controls the software watchdog timer. It consists of the load register, the lock regi ster, the control register, and the clear register. Load register (WdogLoad) This register is a 32-bit register used to set count interval cycles of the software watchdog timer. The initial value is 0xFFFFFFFF. Table 3-1 shows the examples of interval time setting. Table 3-1 Examples of Interval Time Setting of Software Watchdog Timer Count Frequency Interval Set Value Interval Time 40MHz 0xFFFFFFFF [initial value] Approx. 107s 20MHz 0xFFFFFFFF [initial value] Approx. 214s 40MHz 0x0000FFFF Approx. 1.6ms 20MHz 0x0000FFFF Approx. 3.2ms Lock register (WdogLock) This register controls accesses of all the registers of the software watchdog timer. Writing a value of 0x1ACCE551 enables write acces s to all the other registers of the software watchdog timer. Control register (WdogControl) This register sets an interrupt enable of the software watchdog and a reset enable of the software watchdog. Clear register (WdogIntClr) This is a clear register of the software watchdog timer. Writing any 32-bit value reloads the timer counter from the set value set to the load register, and continues counting. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 321 MB9Axxx/MB9Bxxx Series
3. Operations Watchdog Timer Counter (32-bit Down Counter) This is a 32-bit down counter. The count value is re loaded from the set value of the load register (WdogLoad) by accessing to the clear register (WdogIntClr) before the coun ter value becomes 0 by decrementing. Ta b l e 3 - 2 shows the down counter reload condition. Table 3-2 Down Counter Reload Condition of Software Watchdog Timer Reload Conditions Accessing to the clear register (WdogIntClr) When the down counter reaches 0 When the load register (WdogLoad) is modified When the watchdog is stopped by writing INTEN=0 to the control register (WdogControl), and reactivated by writing INTEN=1 Value register (WdogValue) This register can read the counter value of the watchdog timer. Interrupt and reset generation circuit When an underflow of the watchdog timer counter is detected, a watchdog interrupt and a watchdog reset are generated due to the register setting. Interrupt status register (WdogRIS) This register shows the status of a software watchdog interrupt. Activation of software watchdog timer Access to the control register (WdogControl), and enable the watchdog reset. Ta b l e 3 - 3 shows the combination of watchdog interrupt and watchdog reset settings. Table 3-3 Combination of software watchdog interrupt and reset Interrupt Reset Operation Disable Disable The watchdog timer is not operated Enable Disable An interrupt is generated underflow Disable Enable The watchdog timer is not operated Enable Enable An interrupt is generated at the first underflow A reset is generated at the second underflow [Initial setting] Enabling an interrupt of the control register (WdogControl) becomes an activation trigger of the watchdog timer. Reload and lock of the register of the software watchdog timer The register has not been locked with initial condition after reset. When you wish to enable locking, write any values other than 0x1ACCE551 to the WdogLock register with software. When you access the clear register, write 0x1ACCE551 to the WdogLock register to release the lock. The value set to the load register (WdogLoad) is reloaded by writing an arbitrary value to the clear register (WdogIntClr). After accessed the clear register, it will not be automatically locked. Lock it again with software. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 322 MB9Axxx/MB9Bxxx Series
3. Operations Halting the software watchdog timer The software watchdog timer is stopped by accessing to the control register (WdogControl), and writing 0 to the watchdog interrupt enable bit. The software watchdog timer is stopped by generating a reset. Hardware Watchdog Timer Control register / logic This is a circuit to control the hardware watchdog timer. It consists of the load register, the lock regi ster, the control register, and the clear register. Load register (WDG_LDR) This register is a 32-bit register used to set count interval cycles of the hardware watchdog timer. The initial value is 0x00 00FFFF (down counter for 16 bits=> approx. 655ms @ 100kHz (TYP)). For the frequency of CLKLC which is a count clock, see data sheet. Lock register (WDG_LCK) This register controls the accesses of all the regist ers of the hardware watchdog timer. Writing a value of 0x1ACCE551 enables write access to all the regist ers except the control register (WDG_CTL). Control register (WDG_CTL) This register sets watchdog interrupt enable and wa tchdog reset enable. To access this register, it is required to write 0x1ACCE551 to the lock register , and also write 0xE5331AAE to the lock register. In case of not writing the correct value after writin g 0x1ACCE551, it is necessary to repeat the process from the beginning. Clear register (WDG_ICL) This is a clear register of the hardware watchdog timer. Writing any 8-bit value, and also write an arbitrary reversal value reloads the timer counter from the set value set to the load register, and continues counting. Watchdog Timer Counter (32-bit down counter) This is a 32-bit down counter. The count value is re loaded from the set value of the load register (WDG_LDR) by accessing to the clear register (WDG_ ICL) before the counter value becomes 0 by decrementing. Ta b l e 3 - 4 shows the down counter reload condition. Table 3-4 Down Counter Reload Condition of Hardware Watchdog Timer Reload Conditions Accessing to the clear register (WDG_ICL) When the down counter reaches 0 When the load register (WDG_LDR) When the watchdog is stopped by writing INTEN=0 to the control register (WDG_CTL), and reactivated by writing INTEN=1 Value register (WDG_VLR) This register can read the counter value of the current watchdog timer. However, during tool break, a correct value can be read when the watchdog timer is stopped. Except during tool break, an inaccurate value may be read due to asynchronous reading. In this case, a countermeasur e is necessary such as comparing read values after reading it twice. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 323 MB9Axxx/MB9Bxxx Series
3. Operations Interrupt and reset generation circuit When an underflow of the watchdog timer counter is detected, a watchdog interrupt and a watchdog reset are generated due to the register setting. Interrupt status register (WDG_RIS) This register shows the status of a hardware watchdog interrupt. Activation of hardware watchdog timer Writing 0x1ACCE551 to the lock register (WDG_LCK) and then writing a reversal value 0xE5331AAE to it enables to access to the control register (WDG_CTL) also. Access to the control register (WDG_CTL), and en able the watchdog interrupt and the watchdog reset. Table 3-5 shows the combination of watchdog interrupt and watchdog reset settings. Table 3-5 Combination of hardware watchdog interrupt and reset Interrupt Reset Operation Disable Disable The watchdog timer is not operated Enable Disable An interrupt is generated underflow Disable Enable The watchdog timer is not operated Enable Enable An interrupt is generated at the first underflow A reset is generated at the second underflow [Initial setting] Enabling an interrupt of the control register (WDG_CTL) becomes an activation trigger of the hardware watchdog timer. Reload and lock of the register of the hardware watchdog timer The value set to the load register is reloaded by wr iting an arbitrary value to the clear register (WDG_ICL). After reloading, the regi ster is locked again. Unlock is required each time accessing to the clear register hereafter. Stopping the hardware watchdog timer Writing 0x1ACCE551 to the lock register (WDG_LCK) and then writing a reversal value 0xE5331AAE to it enable s to access to the control register (WDG_CTL). The hardware watchdog timer is stopped by accessi ng to the control register (WDG_CTL), and writing 0 to the watchdog interrupt enable bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 11: Watchdog timer MN706-00002-1v0-E 324 MB9Axxx/MB9Bxxx Series