Fujitsu Series 3 Manual
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FUJITSU SEMICONDUCTOR LIMITED
[bit 3] RIE: Receive interrupt enable bit
This bit enables or disables an output of receive interrupt request to the CPU.
If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of erro r flag bits (SSR:ORE) is
1, a receive interrupt request is output.
Bit Description
0 Disables the receive interrupt.
1 Enables the receive interrupt.
To recei ve
data using the INT bit of I
2C Bus Control Register (IBCR) when DMA mode is disabled...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1065.png "Page 1066
FUJITSU SEMICONDUCTOR LIMITED
[bit 3] RIE: Receive interrupt enable bit
This bit enables or disables an output of receive interrupt request to the CPU.
If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of erro r flag bits (SSR:ORE) is
1, a receive interrupt request is output.
Bit Description
0 Disables the receive interrupt.
1 Enables the receive interrupt.
To recei ve
data using the INT bit of I
2C Bus Control Register (IBCR) when DMA mode is disabled...")
![Page 1067
FUJITSU SEMICONDUCTOR LIMITED
5.3. I2C Bus Status Register (IBSR)
The I2C Bus Status Register (IBSR) shows the iteration start, acknowledgement, data
direction, arbitration lost, stop condition, I2C bus status, and bus error detection.
bit 15 ... 8 7 6 5 4 3 2 1 0
Field (SSR) FBT RACKRSA TRX AL RSC SPC BB
Attribute R R R R R R/W R/W R
Initial
value 0 0 0 0 0 0 0 0
[bit 7] FBT: First byte bit
This bit indicates the first byte.
The FBT bit is set when:
1.
The (iteration) start...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1066.png "Page 1067
FUJITSU SEMICONDUCTOR LIMITED
5.3. I2C Bus Status Register (IBSR)
The I2C Bus Status Register (IBSR) shows the iteration start, acknowledgement, data
direction, arbitration lost, stop condition, I2C bus status, and bus error detection.
bit 15 ... 8 7 6 5 4 3 2 1 0
Field (SSR) FBT RACKRSA TRX AL RSC SPC BB
Attribute R R R R R R/W R/W R
Initial
value 0 0 0 0 0 0 0 0
[bit 7] FBT: First byte bit
This bit indicates the first byte.
The FBT bit is set when:
1.
The (iteration) start...")
![Page 1068
FUJITSU SEMICONDUCTOR LIMITED
[bit 5] RSA: Reserved address detection bit
This bit shows that the reserved address has been detected.
The RSA bit is set (RSA=1) when: 1.
The 1st byte is 0000xxxx or 1111xxxx. where, x can be 0 or 1.
The RSA bit is reset (RSA=0) when:
1.
The (iteration) start condition is detected.
2.
The stop condition is detected.
3.
The I2C interface operation is disabled (ISMK:EN bit=0).
4.
A bus error is detected (IBCR:BER bit=1).
If the RSA bit is set to 1 in the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1067.png "Page 1068
FUJITSU SEMICONDUCTOR LIMITED
[bit 5] RSA: Reserved address detection bit
This bit shows that the reserved address has been detected.
The RSA bit is set (RSA=1) when: 1.
The 1st byte is 0000xxxx or 1111xxxx. where, x can be 0 or 1.
The RSA bit is reset (RSA=0) when:
1.
The (iteration) start condition is detected.
2.
The stop condition is detected.
3.
The I2C interface operation is disabled (ISMK:EN bit=0).
4.
A bus error is detected (IBCR:BER bit=1).
If the RSA bit is set to 1 in the...")
![Page 1069
FUJITSU SEMICONDUCTOR LIMITED
[bit 4] TRX: Data direction bit
This bit indicates the data transmission direction.
The TRX bit is set when: 1.
The (iteration) start condition is sent in master mode.
2.
Bit 8 of the 1st byte is 1 in slave mode (in the slave mode transmission direction).
The TRX bit is reset when:
1.
An arbitration lost occurs (AL=1).
2.
Bit 8 of the 1st byte is 0 in slave m ode (in the slave mode reception direction).
3.
Bit 8 of the 1st byte is 1 in master mode (in the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1068.png "Page 1069
FUJITSU SEMICONDUCTOR LIMITED
[bit 4] TRX: Data direction bit
This bit indicates the data transmission direction.
The TRX bit is set when: 1.
The (iteration) start condition is sent in master mode.
2.
Bit 8 of the 1st byte is 1 in slave mode (in the slave mode transmission direction).
The TRX bit is reset when:
1.
An arbitration lost occurs (AL=1).
2.
Bit 8 of the 1st byte is 0 in slave m ode (in the slave mode reception direction).
3.
Bit 8 of the 1st byte is 1 in master mode (in the...")
![Page 1070
FUJITSU SEMICONDUCTOR LIMITED
[bit 2] RSC: Iteration start condition check bit
This bit shows that an iteration start condition is detected in master or slave mode.
The RSC bit is set when: 1.
When an iteration start condition is detected after acknowledgement, during the master or slave mode operation.
The RSC bit is reset when:
1.
The RSC bit is set to 0.
2.
The IBCR:MSS bit is set to 1.
3.
The I2C interface operation is disabled (ISMK:EN bit=0).
It is invalid to set this bit to 1.
Bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1069.png "Page 1070
FUJITSU SEMICONDUCTOR LIMITED
[bit 2] RSC: Iteration start condition check bit
This bit shows that an iteration start condition is detected in master or slave mode.
The RSC bit is set when: 1.
When an iteration start condition is detected after acknowledgement, during the master or slave mode operation.
The RSC bit is reset when:
1.
The RSC bit is set to 0.
2.
The IBCR:MSS bit is set to 1.
3.
The I2C interface operation is disabled (ISMK:EN bit=0).
It is invalid to set this bit to 1.
Bit...")
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FUJITSU SEMICONDUCTOR LIMITED
If no acknowledgement response is sent while data is received in slave mode due to the reserved address
being detected, slave mode is released. In this case, this bit is not set to 1 even if the next stop
condition is detected.
When a read-modify-write instruction is issued, 1 is read.
[bit 0] BB: Bus state bit
This bit shows the bus state.
The BB bit is set when:
1.
LOW is detected in SDA or SCL of the I2C bus.
The BB bit is reset when:
1.
The stop...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1070.png "Page 1071
FUJITSU SEMICONDUCTOR LIMITED
If no acknowledgement response is sent while data is received in slave mode due to the reserved address
being detected, slave mode is released. In this case, this bit is not set to 1 even if the next stop
condition is detected.
When a read-modify-write instruction is issued, 1 is read.
[bit 0] BB: Bus state bit
This bit shows the bus state.
The BB bit is set when:
1.
LOW is detected in SDA or SCL of the I2C bus.
The BB bit is reset when:
1.
The stop...")
![Page 1072
FUJITSU SEMICONDUCTOR LIMITED
5.4. Serial Status Register (SSR)
The Serial Status Register (SSR) is used to check the transmission or reception state.
bit 15 14 13 12 11 10 9 8 7 ... 0
Field REC TSET DMA TBIE ORE RDRFTDRETBI (IBSR)
Attribute R/W R/W R/W R/W R R R R
Initial
value 0 0 0 0 0 0 1 1
[bit 15] REC: Receive error flag clear bit
This bit clears the ORE bit of Se rial Status Register (SSR).
If this bit is set to 1, the ORE bit is cleared.
This bit has no effect if...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1071.png "Page 1072
FUJITSU SEMICONDUCTOR LIMITED
5.4. Serial Status Register (SSR)
The Serial Status Register (SSR) is used to check the transmission or reception state.
bit 15 14 13 12 11 10 9 8 7 ... 0
Field REC TSET DMA TBIE ORE RDRFTDRETBI (IBSR)
Attribute R/W R/W R/W R/W R R R R
Initial
value 0 0 0 0 0 0 1 1
[bit 15] REC: Receive error flag clear bit
This bit clears the ORE bit of Se rial Status Register (SSR).
If this bit is set to 1, the ORE bit is cleared.
This bit has no effect if...")
![Page 1073
FUJITSU SEMICONDUCTOR LIMITED
[bit 13] DMA: DMA mode enable bit
This bit enables or disables DMA mode.
If this bit is set to 1, an interrupt condition is generated during DMA transfer.
If this bit is set to 0, an interrupt cond ition is generated during normal data transfer.
Table 2-1.
For details, see
Bit Description
0 Disables DMA mode.
1 Enables DMA mode.
This bit state
can be changed only when the ISMK:EN bit is 0.
[bit 12] TBIE: Transmit bus idle interrupt enable bit...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1072.png "Page 1073
FUJITSU SEMICONDUCTOR LIMITED
[bit 13] DMA: DMA mode enable bit
This bit enables or disables DMA mode.
If this bit is set to 1, an interrupt condition is generated during DMA transfer.
If this bit is set to 0, an interrupt cond ition is generated during normal data transfer.
Table 2-1.
For details, see
Bit Description
0 Disables DMA mode.
1 Enables DMA mode.
This bit state
can be changed only when the ISMK:EN bit is 0.
[bit 12] TBIE: Transmit bus idle interrupt enable bit...")
![Page 1074
FUJITSU SEMICONDUCTOR LIMITED
[bit 10] RDRF: Receive data full flag bit
This flag shows the state of Receive Data Register (RDR).
If the SMR:RIE bit and the receive data flag bit (RDR F) are 1, a receive interrupt request is issued.
When the receive data is loaded in the RDR, this bit is set to 1. When data is read from the Receive
Data Register (RDR), this bit is cleared to 0.
This bit is set at the falling edge of SCL signal (bit 8 of data).
This bit is also set even when a NACK...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1073.png "Page 1074
FUJITSU SEMICONDUCTOR LIMITED
[bit 10] RDRF: Receive data full flag bit
This flag shows the state of Receive Data Register (RDR).
If the SMR:RIE bit and the receive data flag bit (RDR F) are 1, a receive interrupt request is issued.
When the receive data is loaded in the RDR, this bit is set to 1. When data is read from the Receive
Data Register (RDR), this bit is cleared to 0.
This bit is set at the falling edge of SCL signal (bit 8 of data).
This bit is also set even when a NACK...")
![Page 1075
FUJITSU SEMICONDUCTOR LIMITED
[bit 9] TDRE: Transmit data empty flag bit
This flag shows the state of Transmit Data Register (TDR).
If the SMR:TIE and TDRE bits are 1, a Transmit Interrupt Request is output.
If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data.
When data is loaded to a shift register for transmission and its transmission is started, this bit is set to 1
to indicate that the TDR does not have the valid data.
If the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1074.png "Page 1075
FUJITSU SEMICONDUCTOR LIMITED
[bit 9] TDRE: Transmit data empty flag bit
This flag shows the state of Transmit Data Register (TDR).
If the SMR:TIE and TDRE bits are 1, a Transmit Interrupt Request is output.
If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data.
When data is loaded to a shift register for transmission and its transmission is started, this bit is set to 1
to indicate that the TDR does not have the valid data.
If the...")
FUJITSU SEMICONDUCTOR LIMITED If no acknowledgement response is sent while data is received in slave mode due to the reserved address being detected, slave mode is released. In this case, this bit is not set to 1 even if the next stop condition is detected. When a read-modify-write instruction is issued, 1 is read. [bit 0] BB: Bus state bit This bit shows the bus state. The BB bit is set when: 1. LOW is detected in SDA or SCL of the I2C bus. The BB bit is reset when: 1. The stop condition is detected. 2. The I2C interface operation is disabled (ISMK:EN bit=0). 3. A bus error is detected (IBCR:BER bit=1). Bit Description 0 The bus is in idle state. 1 The bus is in transmission state. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1035 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 5.4. Serial Status Register (SSR) The Serial Status Register (SSR) is used to check the transmission or reception state. bit 15 14 13 12 11 10 9 8 7 ... 0 Field REC TSET DMA TBIE ORE RDRFTDRETBI (IBSR) Attribute R/W R/W R/W R/W R R R R Initial value 0 0 0 0 0 0 1 1 [bit 15] REC: Receive error flag clear bit This bit clears the ORE bit of Se rial Status Register (SSR). If this bit is set to 1, the ORE bit is cleared. This bit has no effect if set to 0. When it is read, 0 is always read. Description Bit During writing During reading 0 No effect. 0 is always read. 1 Clears the Receive Error flag (ORE). [bit 14] TSET: Transmit empty flag set bit This bit sets the TDRE bit of Serial Status Register (SSR). If it is set to 1 and if the TDRE bit and DMA mode are enabled (DMA=1), the TBI bit is set. This bit has no effect if set to 0. When it is read, 0 is always read. Description Bit Write Read 0 No effect. 0 is always read. 1 The TDRE bit is set. Set this b it to 1 only when the IBCR:INT bit is 1. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1036 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED [bit 13] DMA: DMA mode enable bit This bit enables or disables DMA mode. If this bit is set to 1, an interrupt condition is generated during DMA transfer. If this bit is set to 0, an interrupt cond ition is generated during normal data transfer. Table 2-1. For details, see Bit Description 0 Disables DMA mode. 1 Enables DMA mode. This bit state can be changed only when the ISMK:EN bit is 0. [bit 12] TBIE: Transmit bus idle interrupt enable bit (Effective only when DMA mode is enabled) This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. If DMA mode is enabled (DMA=1) and both TBIE and TBI bits are 1, a transmit bus idle interrupt request is output. If DMA mode is disabled (DMA=0), this bit is set to 0 . In such case, this bit is set to 0. If data is written, this writing is ignored and the 0 is maintained. Bit Description 0 Disables the transmit bus idle interrupt. 1 Enables the transmit bus idle interrupt. [bit 11] ORE: Overrun error flag bit If an overrun occurs during data receptio n, this bit is set to 1. This is cleared if the REC bit of Serial Status Register (SSR) is set to 1. If the ORE and SMR:RIE bits are 1, a receive interrupt request is output. If this flag is set, the Receive Data Register (RDR) is invalid. If the receive FIFO is used and if this flag is set, the received data is not stored in the receive FIFO. Bit Description 0 No overrun error occurred. 1 An overrun error occurred. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1037 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED [bit 10] RDRF: Receive data full flag bit This flag shows the state of Receive Data Register (RDR). If the SMR:RIE bit and the receive data flag bit (RDR F) are 1, a receive interrupt request is issued. When the receive data is loaded in the RDR, this bit is set to 1. When data is read from the Receive Data Register (RDR), this bit is cleared to 0. This bit is set at the falling edge of SCL signal (bit 8 of data). This bit is also set even when a NACK is responded. (*1) If the receive FIFO is used and if a certain count of data is received by the receive FIFO, the RDRF bit is set to 1. If the receive FIFO is used and if this buffer is emptied, this bit is cleared to 0. If all of the following conditions are satisfied and if th e receive idle state continues for more than 8 baud rate clocks, the interrupt flag (SSR:RDRF) is set to 1. The receive FIFO idle detection enable bit (FCR:FRIIE) is 1. The number of data sets stored in the recei ve FIFO does not reach the transfer count. The IBCR:BER bit is 0. If the RDR data is read during counting of 8 clocks, this counter is reset to 0 and counting for 8 clocks is restarted. *1) NACK response: The SDA bit of I 2C bus is H during acknowledgement. Bit Description 0 The Receive Data Register (RDR) is empty. 1 The Receive Data Register (RDR) contains data. If all of the following conditions are satisfied, the SCL flag is set to LOW after acknowledgement was transmitted. If the RDRF bit is set to 0, the SCL flag is released from the LOW state. The receive FIFO is not used. DMA mode is enabled (IBCR:DMA=1). Data is received in the 2nd or subsequent by te (IBSR:TRX=0), and the RDRF bit is 1. The IBCR:WSEL bit is 0. If all of the following conditions are satisfied, the SCL flag is set to LOW immediately after single-byte data reception. If the RDRF bit is set to 0, the SCL flag is released from the LOW state. The receive FIFO is not used. DMA mode is enabled (IBCR:DMA=1). Data is received in the 2nd or subsequent by te (IBSR:TRX=0), and the RDRF bit is 1. The IBCR:WSEL bit is 1. If the receive FIFO is used and DMA mode is enabled for data reception (DMA=1), the SCL flag is set to LOW when the receive FIFO is filled with data. If data is read from the RDR even once, the SCL flag is released from the LOW state. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1038 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED [bit 9] TDRE: Transmit data empty flag bit This flag shows the state of Transmit Data Register (TDR). If the SMR:TIE and TDRE bits are 1, a Transmit Interrupt Request is output. If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data. When data is loaded to a shift register for transmission and its transmission is started, this bit is set to 1 to indicate that the TDR does not have the valid data. If the TSET bit of Serial Status Register (SSR) is set to 1, this flag is set. If an arbitration lost or a bus error is detected, use this flag to set the TDRE bit to 1. Bit Description 0 The Transmit Data Register (TDR) contains data. 1 The Transmit Data Register is empty. [bit 8] TBI: Transmit bus idle flag bit (Effective only when DMA mode is enabled) This bit shows that no data is sent by the I2C when DMA mode is enabled (DMA=1). If DMA mode is enabled (DMA=1) and the TBI bit is set to 1 in the 2nd or subsequent byte, the SCL flag is set to LOW. If the TBI bit is set to 0, the SCL flag is cleared from the LOW state. The TBI bit is set when: 1. The WSEL bit is 1, master mode is selected, an d the TDRE bit is 1 in the 2nd or subsequent byte. 2. The WSEL bit is 1, the slave mode transmission is selected, and the SSR:TDRE bit is 1 in the 2nd or subsequent byte. 1. Master mode is selected, the reserved address is not detected in the 1st byte, and the SSR:TDRE bit is 1. 2. The WSEL bit is 0, master mode is selected, an d the TDRE bit is 1 in the 2nd or subsequent byte. 3. The WSEL bit is 0, the slave mode transmission is selected, and the SSR:TDRE bit is 1 in the 2nd or subsequent byte. The transmit buffer empty flag set bit (TSET) is set to 1. The TBI bit is reset when: 1. The transmit data is written in the Transmit Data Register (TDR). If this bit is 1 and if the transmit bus idle interrup t is enabled (SCR:TBIE=1), a transmit interrupt request is output. If DMA mode is disabled (DMA=0), this bit is undefined. Bit Description 0 During data transmission 1 No data transmission CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1039 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED
5.5. Receive Data Register/Transmit Data Register (RDR/TDR)
The Receive and Transmit Data Registers are allocated at the same address. This register
functions as the Receive Data Register when data is read from it. This register operates as
the Tr
ansmit Data Register when data is written in it.
Receive Data Register (RDR)
bit 15 ... 8 7 6 5 4 3 2 1 0
Field D7 D6 D5 D4 D3 D2 D1 D0
Attribute R R R R R R R R
Initial
value 0
0 0 0 0 0 0 0
The Receive Data Register (RDR) is a data buffer register for serial data reception.
When a serial data signal is sent to the serial data line (SDA pin), it is converted by a shift register and
stored in the Receive Data Register (RDR).
When the first byte is received, a received address is not stored in the Receive Data Register (RDR).
However, when the first byte is a reserved address, a received address is stored in the Receive Data
Register (RDR). In this case, the least significan t bit (RDR:D0) is the data direction bit. (*1)
When the received data is stored in the Receive Da ta Register (RDR), the receive data full flag bit
(SSR:RDRF) is set to 1.
When data is read from the Receive Data Register (RDR), the receive data full flag bit (SSR:RDRF) is
cleared to 0 automatically. *1) The first byte indicates data after the (iteration) start condition.
If the receive FIFO is used and if a certain count of data is received by the receive FIFO, the SSR:RDRF
bit is set to 1.
If the receive FIFO is used and if this buffer is emptied, the SSR:RDRF bit is cleared to 0.
CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051
MN706-00002-1v0-E
1040
MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Transmit Data Register (TDR) bit 15 ... 8 7 6 5 4 3 2 1 0 Field D7 D6 D5 D4 D3 D2 D1 D0 Attribute W W W W W W W W Initial value 1 1 1 1 1 1 1 1 The Transmit Data Register (TDR) is a data bu ffer register for serial data transmission. Data of the Transmit Data register (TDR) is output to the serial data line (SDA pin) with the MSB first order. When the first byte is transmitted, the least signi ficant bit (TDR:D0) indicates the data transmission direction. When the transmit data is written in the Transmit Da ta Register (TDR), the transmit data empty flag (SSR:TDRE) is cleared to 0. When data is transferred to a shift register for tran smission, the transmit data empty flag (SSR:TDRE) is set to 1. If transmit FIFO is disabled and if the data empty fl ag (SSR:TDRE) is 0, the transmit data cannot be written in the Transmit Data Register (TDR). If transmit FIFO is used, the transmit data can be written until this buffer is filled with it even if the data empty flag (SSR:TDRE) is 0. The Tr ansm it Data Register is a write-only register. Wh ile the Receive Data Register is a read-only regist er. As these two registers are allocated at the same addre ss, the write and read values differ from each other. Therefore, the INC/DEC instruction and other read-m odify-write (RMW) instructions cannot be used. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1041 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 5.6. 7-bit Slave Address Mask Register (ISMK) The 7-bit Slave Address Mask Register (ISMK) is used to compare or set each bit of the slave address. bit 15 14 13 12 11 10 9 8 7 ... 0 Field EN SM6 SM5 SM4 SM3 SM2 SM1 SM0 (ISBA) Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 1 1 1 1 1 1 1 [bit 15] EN: I2C interface operation enable bit This bit enables or disables the I2C interface operation. If set to 0: The I 2C interface operation is disabled. If set to 1: The I2C interface operation is enabled. Bit Description 0 Disable 1 Enable This bit is not cleared to 0 even if the BER bit of IBSR register is set to 1. The baud rate generator must be set only when this bit is 0. When this bit is 0, set both the 7-bit Slave Address Register and the 7-bit Slave Address Mask Register. If the I2C interface operation is disabled (EN=0), da ta transmission is inhibited immediately. If you have set the IBCR:MSS bit to 0 to generate a Stop condition and if you wish to disable the I2C interface operation, make sure that the stop condition has occurred. Then, disable the interfacing (EN=0). If the EN bit is set to 0 during data transmission, a pulse may be generated on the SDA/SCL signal of the I2C bus. [bit 14:8] SM6 to SM0: Slave address mask bits These bits specify to exclude th e 7-bit slave address and the received address from comparison. If set to 1, the address is compared. If set to 0, the address matching is assumed. Bit 14:8 Description 0 Does not compare the bits. 1 Compares the bits. This register must be set only when the EN bit is 0. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1042 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 5.7. 7-bit Slave Address Register (ISBA) The 7-bit Slave Address Register (ISBA) is used to set the slave address. bit 15 ... 8 7 6 5 4 3 2 1 0 Field (ISMK) SAEN SA6 SA 5 SA4 SA3 SA2 SA1 SA0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 7] SAEN: Slave address enable bit This bit enables the slave address detection. If set to 0: The slave address is not detected. If set to 1: The ISBA and ISMK settings and the received 1st byte are compared. Bit Description 0 Disable 1 Enable [bit 6:0] SA6 to SA0: 7-bit slave address If the slave address detection is enabled (SAEN=1), the 7-bit Slave Address Register (ISBA) compares the 7-bit data, which has been received after detection of (iteration) start condition, with this register value. If all bits match each other, slave mode is sel ected and an ACK is output. At this time, the received slave address is stored in this regi ster (if SAEN=0, no ACK is output). If an address bit is set to 0 in the ISMK register, it is not compared. Bit 6:0 Description 6-0 7-bit slave address The reserved address cannot be set. This register must be set only when the EN bit of ISMK register is 0. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1043 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 5.8. Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency division ratio of serial clocks. bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field - (BGR1) (BGR0) Attribute - R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W Initial value - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The Baud Rate Generator Registers are used to set a frequency division ra tio of serial clocks. The BGR1 register corresponds to the high-order bits , and the BGR0 register corresponds to the low-order bits. The reload value to be counted can be written, and the BGR1/0 set value can be read. When the reload value is written in Baud Rate Gene rator Registers 1 and 0 (BGR1 and BGR0), the Reload counter starts its counting. [bit 15] Reserved bit This bit value is undefined during reading. It has no effect during writing. [bit 14:8] BGR1: Baud Rate Generator Register 1 Bit 14:8 Description Write Writes data in bit 8 to 14 of reload counter. Read Reads the BGR1 set value. [bit 7:0] BGR0: BAUD RATE GENERATOR REGISTER 0 Bit 7:0 Description Write Writes data in bit 0 to 7 of reload counter. Read Reads the BGR0 set value. Data must be written in the Baud Rate Generator Registers (BGR1 and BGR0) by 16-bit data accessing. The Baud Rate Generator Registers must be set when the EN bit of ISMK register is 0. The baud rate must be set regardless of master or slave mode selection. In operation mode 4 (I2C mode), operate the bus clock at a frequency no lower than 8 MHz. Also note that setting of a baud rate generator that exceeds 400 kbps is prohibited. CHAPTER 19-5: I2C Interface \050I2C Communications Control Interface\051 MN706-00002-1v0-E 1044 MB9Axxx/MB9Bxxx Series