Fujitsu Series 3 Manual
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1. Configuration Chapter: PPG Configuration This chapter explains PPG configuration. 1. Configuration CODE: 9BFPPGTOP-E01.2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-1: PPG Configuration MB9Axxx/MB9Bxxx Series MN706-00002-1v0-E 615
1. Configuration 1. Configuration This section explains the unique PPG configuration. The following shows the unique PPG configuration. PPG output GATE Signal Circuit PPG1 PPG Trigger Enable Register Timing Generator Circuit 0 To interrupt unit GATE signal (GATE0, GATE2, GATE4, GATE8, GATE10, GATE12) RTO output PPG module PPG0 PPG2 PPG4 PPG3 PPG5 PPG7 PPG6 PPG8 PPG9 PPG10 PPG11 PPG12 PPG13 PPG14 PPG15 Multi Function Timer Unit 0 Multi Function TimerUnit 1 RTO output RTO output RTO output RTO output RTO output PPG output PPG output PPG output PPG output PPG output Timing Generator Circuit 1 PPG connection PPG output is transferred from the output RTO pin of the multifunction timer via the multifunction timer module. PPG output and PPG interrupt are connected only to the PPG0, PPG2, PPG4, PPG8, PPG10, and PPG12. Therefore, no output is obtained from other PPG channels. A PPG start factor can be set to a PPG channel with no output connected, but no output is obtained from such a PPG channel. Furthermore, any PPG operation mode (8-bit, 8+8-bit, 16-bit, or 16+16-bit mode) can be selected, but no output is obtained from a PPG channel with no output connected. Differences between timing generators 0 and 1 Timing generator 0 Compare Register : CO MP0/COMP2/COMP4/COMP6 PPG channel to be triggered : ch.0/ch.2/ch.4/ch.6 Timing generator 1 Compare Register : CO MP1/COMP3/COMP5/COMP7 PPG channel to be triggered : ch.8/ch.10/ch.12/ch.14 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-1: PPG Configuration MN706-00002-1v0-E 616 MB9Axxx/MB9Bxxx Series
1. Configuration FUJITSU SEMICONDUCTOR LIMITED Chapter: PPG Configuration FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 Combinations of operation modes and PPG channels with output enabled PPG channel 8-bit mode 8+8-bit mode 16-bit mode 16+16-bit mode PPG ch.0 PPG0 output PPG0 output PPG ch.1 Not available PPG0 prescaler PPG0 output PPG0 output PPG ch.2 PPG2 output PPG2 output PPG ch.3 Not available PPG2 prescaler PPG2 output PPG0 prescaler PPG ch.4 PPG4 output PPG4 output PPG ch.5 Not available PPG4 prescaler PPG4 output PPG4 output PPG ch.6 Not available Not available PPG ch.7 Not available Not available Not available PPG4 prescaler PPG ch.8 PPG8 output PPG8 output PPG ch.9 Not available PPG8 prescaler PPG8 output PPG8 output PPG ch.10 PPG10 output PPG10 output PPG ch.11 Not available PPG10 prescaler PPG10 output PPG8 prescaler PPG ch.12 PPG12 output PPG12 output PPG ch.13 Not available PPG12 prescaler PPG12 output PPG12 output PPG ch.14 Not available Not available PPG ch.15 Not available Not available Not available PPG12 prescaler Setting the EDGE bit in the PPG GATE Function Control Register The EDGE bit in the PPG GATE Function Contro l Register can be set only to EDGE=0. * : Started only at the rising edge of the GATE signal. CHAPTER 16-1: PPG Configuration MN706-00002-1v0-E 617 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 618 MB9Axxx/MB9Bxxx Series
1. Overview Chapter: PPG This chapter describes the PPG timer. 1. Overview 2. Configuration and Block Diagrams 3. Operations 4. Setup Procedure Example 5. Registers 6. Notes CODE: 9BFPPG-E01.2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 619 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview This section describes the overview of PPG timer. The Programmable Pulse Generator (PPG) module can perform pulse output of arbitary cycle and duty ratio controled by timer operation. Features of PPG module 8-bit PPG output 2-channel independent operating mode is supported. 16-bit PPG output operating mode is supported. 8+8-bit PPG output operating mode is supported. 16+16-bit PPG output operating mode is supported. PPG can be inverted the output level, including the initial output level during PPG stop. PPG can be selected arbitary cycl e by selecting PPG count clock. PPG can output the pulses with arbitary duty ratio by register setting. This module can also be used in conjunction with an external circuit to form a D/A converter. When the reload value count is ended and an underflow occurs, PPG is activated. This activation occurs if an interrupt is enabled by the Control Register (PPGC Register). PPG start trigger conditions PPG start trigger can be selected from following three conditions. Start triggered by register writing Start triggered by the Timing Generator Circuit Start triggered by GATE signal from the multifunction timer FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 620 MB9Axxx/MB9Bxxx Series
2. Configuration and Block Diagrams 2. Configuration and Block Diagrams This section shows the configuration and block diagrams of PPG timer. PPG circuit block diagram Figure 2-1 shows the block diagram of the PPG circuit. Figure 2-1 PPG circuit block diagram PPG output APB SignalAPB Interface PPG Output Circuit Interrupt Output Circuit Control Registers DOWN counter Reload Circuit To interrupt unit GATE signal from multifunction timer PPG module GATE Signal Circuit PPG Trigger Circuit Timing Generator Circuit The PPG module consists of the following functional blocks. GATE Signal Circuit This circuit sets the start or stop signal to PPG module when receiving a GATE signal from the multifunction timer. Timing Generator Circuit This is a PPG start timing generator circuit. This circuit generates a PPG start timing signal, using its built-in compare register. Simultaneous startup or a delayed startup of PPG is allowed by the compare register setting. The details are given in the following sections. PPG trigger circuit This is a PPG trigger circuit containing PPG start register. This circuit generates a start trigger signal when the register is enabled. Up to eight channels can be started simultaneously (in 16-bit mode). Control registers These registers contain the setting registers of count clock cycle and PPG operation mode. DOWN Counter This is a down counter for PPG pulse generation. This counter loads the value of reload register and generates output pulses. Reload Circuit This circuit sets the LOW width and HIGH width of output pulse to be reloaded into the down counter. This circuit inverts the pin output level at reloading. PPG Output Circuit This circuit outputs PPG pulse. An output level at PPG STOP can be set by the register setting. Interrupt Output Circuit This circuit outputs a preset interrupt signal. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 621 MB9Axxx/MB9Bxxx Series
2. Configuration and Block Diagrams Timing generator block diagram Figure 2-2 and Figure 2-3 show the block diagram of timing generator circuits 0 and 1, respectively. Figure 2-2 Block diagram of timing generator circuit 0 FUJITSU SEMICONDUCTOR LIMITED STRMONI Figure 2-3 Block diagram of timing generator circuit 1 In Figure 2-2 and Figure 2-3 , PPGxTG(x=0,2,4,6,8,10,12,14) is a PPG start trigger signal. The Timi ng Ge nerator Circuit consists of the following functional blocks. Prescaler This circuit sets the divided clock of PCLK (the APB bus clock) for the counter clock. 8-bit Counter This is an UP Counter. The count clock is used from the prescaler. Compare circuit This circuit compares an 8-bit co unter value with the COMP register value, and generates a PPG start trigger signal. COMP Register This register sets a generation timing of each PPG start trigger signal. Prescaler 8-bit CounterCOMP0PCLK Compare Circuit COMP2 Compare Circuit COMP4 Compare Circuit COMP6 Compare Circuit Set/ClearPPG0TG Set/Clear Set/Clear PPG2TG PPG4TG PPG6TG Set/Clear Prescaler 8-bit CounterCOMP1 STR MONI PCLK Compare Circuit COMP3 Compare Circuit COMP5 Compare Circuit COMP7 Compare Circuit Set/ClearPPG8TG Set/Clear Set/Clear PPG10TG PPG12TG PPG14TG Set/Clear CHAPTER 16-2: PPG MN706-00002-1v0-E 622 MB9Axxx/MB9Bxxx Series
3. Operations 3. Operations This section shows the opration of PPG timer. 3.1 PPG circuit operations 3.2 Timing generator circuit operations FUJITSU SEMICONDUCTOR LIMITED CHAPTER 16-2: PPG MN706-00002-1v0-E 623 MB9Axxx/MB9Bxxx Series
3. Operations 3.1. PPG circuit operations The PPG module can output pulse signals having arbitary cycle and duty ratio. The pulse output can be controlled based on the timer operation. PPG functions The PPG timer starts decrem enting the down counter value being set in the LOW width reload register by triggered. During this time, the output is set to LOW. After an underflow occurs, the output is inverted to HIGH. Then, the PPG timer starts decrementing the value being set in the HIGH width reload register. When an underflow occurs, the output is inverted to LOW again. Thus, PPG can generate pulses having arbitary LOW and HIGH pulse width. Figure 3-1 shows an operation example of 8/16bit-PPG operating mode when PPG is started by register writing . Figure 3-1 Operation example when PPG is started by register writing FUJITSU SEMICONDUCTOR LIMITED The operation starts when PENn=1 is set. * When LOW pulse waves are processed The operation stops w hen PENn=0 is set.T x (H+1)T x (L+1 ) T x (L+1) PENn PPG output Sta r t Stopped even wh en counting Repeated for LOW pulses Explanation of symbols used in Figure 3-1 L : PRLL value P1 = T x (L+1) H : PRLH value T : Input clock cycle Ph = T x (H+1) Pl : LOW pulse width Ph : HIGH pulse width 1. When PENn Register is set to 1, PPG output starts. 2. The 8/16-bit PPG timer has two reload registers (PR LL/PRLH) for each channel. The values set in the reload registers are reloaded alte rnately into the down counters. 3. After LOW level pulses are output during T x (L+1) counting, HIGH level pulses are output during T x (H+1) counting. After T x (H+1) counting are finished, T x (L+1) counting start again and LOW level pulses output again. This output rep eats until the PENn Register is set to 0. 4. The operation stops if PENn Register is set to 0. The pulse output is stopped even when pulses are counted. Relation between reload value and pulse width The pulse width to be output is the value that multiplies the cycle of the count clock by the value in the reload register plus 1. Note that the pulse width will be one cycle of the count clock when the reload register value is set to 00 H at operating the 8- bit PPG and when the reload register value is set to 0000H at operating the 16-bit PPG. Note that the pulse width will be 256 cycles of the count clock when the reload register value is set to FF H at operating the 8-bit PPG and the pulse width will be 65536 cycles of the count clock when the reload re gister value is set to FFFF H at operating the 16-bit PPG. Interrupts If an interrupt is enabled by the Control Register ( PPGC Register) setting, an interrupt occurs when the reload value is counted out and an underflow occurs. The interrupt occurs when LOW pul se ends and HIGH pulse ends. However, if the PPGC.INTM bit is set to 1, an interrupt only occurs when HIGH width pulse ends. CHAPTER 16-2: PPG MN706-00002-1v0-E 624 MB9Axxx/MB9Bxxx Series