Fujitsu Series 3 Manual
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4. CAN Registers
When the transfer directi on is reading (WR/RD=0)
[bit 6] Mask: Mask data update bit
Bit Function
0 Indicates that data (ID mask + MDir +
MXtd) is not transferred from a message
object*1 to IFx Master Register 1 or 2. [Initial value]
1 Indicates that data (ID mask + MDir
+ MXtd) is transferred from a message
object*1 to IFx Master Register 1 or 2.
*1: See 4.4 Message objects .
[bit 5] Arb: Arbitration data update bit
Bit Function
0 Indicates that data (ID +...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1275.png "Page 1276
4. CAN Registers
When the transfer directi on is reading (WR/RD=0)
[bit 6] Mask: Mask data update bit
Bit Function
0 Indicates that data (ID mask + MDir +
MXtd) is not transferred from a message
object*1 to IFx Master Register 1 or 2. [Initial value]
1 Indicates that data (ID mask + MDir
+ MXtd) is transferred from a message
object*1 to IFx Master Register 1 or 2.
*1: See 4.4 Message objects .
[bit 5] Arb: Arbitration data update bit
Bit Function
0 Indicates that data (ID +...")
![Page 1277
4. CAN Registers
[bit 1] Data A: Data 0-3 update bit
Bit Function
0 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is
held. [Initial value]
1 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is
updated.
*1: See 4.4 Message objects .
[bit 0] Dat a B: Data 4-
7 update bit
Bit Function
0 Indicates that data of the message object
*1 and CAN Data Register B1 or B2 is
held. [Initial value]
1 Indicates that data of the message...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1276.png "Page 1277
4. CAN Registers
[bit 1] Data A: Data 0-3 update bit
Bit Function
0 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is
held. [Initial value]
1 Indicates that data of the message object
*1 and CAN Data Register A1 or A2 is
updated.
*1: See 4.4 Message objects .
[bit 0] Dat a B: Data 4-
7 update bit
Bit Function
0 Indicates that data of the message object
*1 and CAN Data Register B1 or B2 is
held. [Initial value]
1 Indicates that data of the message...")
4. CAN Registers 4.3.6. IFx Data Registers A1, A2, B1, and B2 (IFxDTA1, IFxDTA2, IFxDTB1, and IFxDTB2) The IFx Data Registers A1, A2, B1, and B2 are used to write or read message object sending or receiving data to or from the message RAM. Those registers are used only to send or receive a data frame, and not to send or receive a remote frame. Register configuration addr+3 addr+2 addr+1 addr+0 IFx Data A Register 1 (Little endian) Data(1) Data(0) IFx Data A Register 2 (Little endian) Data(3) Data(2) IFx Data B Register 1 (Little endian) Data(5) Data(4) IFx Data B Register 2 (Little endian) Data(7) Data(6) IFx Data A Register 2 (Big endian) Data(2) Data(3) IFx Data A Register 1 (Big endian) Data(0) Data(1) IFx Data B Register 2 (Big endian) Data(6) Data(7) IFx Data B Register 1 (Big endian) Data(4) Data(5) - IFx Data Register bit 15 7 14 6 13 5 12 4 11 3 10 2 9 1 8 0 Field Data Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Register functions Send message data setting The set data is sent in the order of Data(0), Data(1 ), ..., Data(7), beginning with the MSB (bit 7 or bit 15). Received message data The received message data is stored in the order of Data(0), Data(1), ..., Data(7), beginning with the MSB (bit 7 or bit 15). If th e received message data is lower than eight by tes in length, undefined data is written to the rem aining bytes of the Data Register. To transfer data to a message object, it is processed every four bytes in the Data A or Data B Register; therefore, it is impossible to update only a part of 4-byte data. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1245 MB9Axxx/MB9Bxxx Series
4. CAN Registers 4.4. Message objects The message RAM provides 32 message objects. To avoid a confliction when simultaneously accessing the message RAM from the CPU and the CAN controller, the CPU cannot directly access message objects. The message RAM is accessed via the IFx Message Interface Register. This section explains the configuration and functions of a message object. Configuration of message object NewDatUMask MsgVal Msk28-0 ID28-0 MXtd Xtd MDir Dir EoB DLC3-0Data0Data1 MsgLst Data2 RxIE Data3 TxIEIntPndRmtEnTxRqst Data4Data7Data6Data5 Message object A me ssage object is not initialized using the Init bit of the CAN Control Register or the hardware reset function. For t h e hardware reset function, release the hardware reset function, and initialize the message RAM using the CPU or set MsgVal of the message RAM to 0. Functions of message object The ID28-0, Xtd, and Dir bits are used to indicate the ID and message type when sending a message. They are used in the acceptance filter to gether with the Msk28-0, MXtd, and MDir bits when receiving a message. ID, IDE, RTR, DLC, and DATA in a data or remote frame that passed through the acceptance filter are respectively stored in ID28-ID0, Xtd, Dir, DLC3-DLC0, and Data7-Data0 of a message object. Xtd indicates whether the received frame is an extension or st andard frame. If Xtd is 1, a 29-bit ID (extension frame) is received. If Xtd is 0, a 11-bit ID (standard frame) is received. When the received data or remote frame matches one or more message objects, it is stored in the message object with the lowest message number. For details, see Acceptance Filter for Received Messages in 3.3 Message reception . MsgV al : Valid message bi t Bit Function 0 Message objects are invalid. Disables message sending/receiving. 1 Message objects are valid. Enables message sending/receiving. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1246 MB9Axxx/MB9Bxxx Series
4. CAN Registers Reset the MsgVal bit of an unused m essage object to 0 before clearing the Init bit of the CAN Control Register to 0. Be sure to reset the MsgVal bit of a message object to 0 before changing the value of ID28-0, Xtd, Dir, or DLC3-0. If the MsgVal bit of a message object is cleared to 0 during transmission, the TxOk bit of the CAN Status Register is set to 1 when transmission has been completed. However, the TxRqst bits of the message object and CAN Transmit Request Register ar e not cleared to 0. Use the Message Interface Register to clear the TxRqst bit to 0. UMask : Acceptance mask enable bit Bit Function 0 Does not use Msk28-0, MXtd, or MDir. 1 Uses Msk28-0, MXtd, or MDir. Chang e the value of the UMask bit when the Init bit of the CAN Control Register is 1 or the MsgVal bit is 0. When t he Dir bit is 1 and the RmtEn bit is 0, operations vary depending on the setting of the UMask bit. If the UMask bit is 1, reset the TxRqst bit to 0 when a remote frame has been received through the acceptance filter. The received ID, IDE, RTR, and DLC are stored in a message object, and the NewDat bit is set to 1 while data remains unchanged (data is handled as a data frame). If the UMask bit is 0, the TxRqst bit is held an d a remote frame is ignored even if it has been received. ID28-0 : Message ID Function ID28 - ID0 Specifies a 29-b it ID (extension frame). ID28 - ID18 Specifies a 11-bit ID (standard frame). Msk28-0: ID mask Bit Function 0 Masks the bit that corresponds to the ID of a message object. 1 Does not mask the bit that corresponds to the ID of a message object. Xtd: Extension ID enable bit Bit Function 0 Uses the 11-bit ID (standar d frame) for message object. 1 Uses the 29-bit ID (extension frame) for message object. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1247 MB9Axxx/MB9Bxxx Series
4. CAN Registers MXtd : Extension ID mask bit Bit Function 0 Does not compare the set value of the Xtd bit in a message object with that of the IDE bit of a received frame. Determine whet her to perform the comparison as the ID of a standard frame or extension frame based on the IDE bit of a received frame. 1 Compares the set value of the Xtd bit in a message object with that of the IDE bit of a received frame. When a 11-bit ID (standard frame) is set to a message object, the ID of a received data frame is written to ID28 to ID18. Msk28 to Msk18 are used to mask the ID. Dir: Message direction bit Bit Function 0 Indicates the receiving direction. When the TxRqst bit is set to 1, a remote frame is sent. When the TxRqst bit is set to 0, a data frame that passed through the acceptance filter is received. 1 Indicates the transmission direction. When the TxRqst bit is set to 1, a data frame is sent. When the TxRqst is 0 and the RmtEn bit is 1, the CAN controller sets the TxRqst bit to 1 if a data frame that passed through the acceptance filter is received. MDir : Message direction mask bit Bit Function 0 Masks the message direction bit (Dir) through the acceptance filter. 1 Does not mask the message direction bit (Dir) through the acceptance filter. Always set th e Mdir bit to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1248 MB9Axxx/MB9Bxxx Series
4. CAN Registers EoB: End of buffer bit (For details, see 3.4 FIFO buffer function .) Bit Function 0 Indicates that a message object is used as a FIFO buffer, not the last message. 1 Indicates a single message object or the last message object in the FIFO buffer. The Eo B bit is used to configure a FIFO buff er for message objects 2 to 32. When processing a single message object without using a FIFO buffer, be sure to set the EoB bit to 1. NewDat: Data update bit Bit Function 0 Indicates that no valid data resides. 1 Indicates that valid data resides. MsgLst : Message lost Bit Function 0 Message lost does not occur. 1 Message lost occurs. The MsgLst bi t is valid only when th e Dir bit is 0 (receiving direction). RxIE: Receiving interrupt flag enable bit Bit Function 0 Does not change the value of the IntPnd bit after frame receiving has succeeded. 1 Changes the IntPnd bit to 1 af ter frame receiving has succeeded. TxIE: Transmission interrupt flag enable bit Bit Function 0 Does not change the value of the IntPnd bit after frame transmission has succeeded. 1 Changes the IntPnd bit to 1 af ter frame transmission has succeeded. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1249 MB9Axxx/MB9Bxxx Series
4. CAN Registers IntPnd: Interrupt pending bit Bit Function 0 No interrupt cause is detected. 1 An interrupt cause is detected. If other high-priority interrupt is not found, the IntId bit of the CAN Interrupt Register indicates this message object. RmtEn: Remote enable Bit Function 0 Does not change the value of the TxRqst bit when a remote frame has been received. 1 Sets the TxRqst bit to 1 when a remote frame is received while the Dir bit is 1. When t he Dir bit is 1 and the RmtEn bit is 0, operations vary depending on the setting of the UMask bit. If the UMask bit is 1, reset t h e TxRqst bit to 0 when a remote frame has been received through the acceptance filter. The received ID, IDE, RTR, and DL C are stored in a message object. The NewDat bit is set to 1 while data remains unchanged (data is handled as a data frame). If the UMask bit is 0, the TxRqst bit is held and a remote frame is ignored even if it has been received. TxRqst : Transmission request bit Bit Function 0 Indicates the sending idle state (neither the sending state nor the sending wait state). 1 Indicates the sending or sending wait state. DLC3-0: Data length code Bit Function 0-8 The data frame length is 0 to 8 bytes. 9-15 Setting disabled. 8-byte length if specified. The receive d DLC is stored in the DLC bit if a data frame is received. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1250 MB9Axxx/MB9Bxxx Series
4. CAN Registers Data 0-7: Data 0 to 7 Function Data 0 First data byte in CAN data frame Data 1 2nd data byte in CAN data frame Data 2 3rd data byte in CAN data frame Data 3 4th data byte in CAN data frame Data 4 5th data byte in CAN data frame Data 5 6th data byte in CAN data frame Data 6 7th data byte in CAN data frame Data 7 8th data byte in CAN data frame Serial da ta is ou tput from the MSB (bit 7 or bit 15) to the CAN bus. If the receive d message data is lower than eight by tes in length, undefined data is written to the remaining bytes of the Data Register. To transfer data to a message object, it is processed every four bytes in the Data A or Data B Register; therefore, it is impossible to update only a part of 4-byte data. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1251 MB9Axxx/MB9Bxxx Series
4. CAN Registers 4.5. Message handler registers Message handler registers are all in read only mode. The TxRqst, NewDat, IntPnd, and MsgVal bits of a message object and the IntId bit indicate the status. Message handler registers CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2) CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1252 MB9Axxx/MB9Bxxx Series
4. CAN Registers 4.5.1. CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) The CAN Transmit Request Register indicates the TxRqst bit of all message objects. This register checks which message object transmission request is pending by reading the TxRqst bit. Register configuration - CAN Transmit Request Register 2 (High-order byte) bit 15 14 13 12 11 10 9 8 Field TxRqst32-25 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Transmit Request Register 2 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field TxRqst24-17 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Transmit Request Register 1 (High-order byte) bit 15 14 13 12 11 10 9 8 Field TxRqst16-9 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 - CAN Transmit Request Register 1 (Low-order byte) bit 7 6 5 4 3 2 1 0 Field TxRqst8-1 Attribute R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX Initial value 0 0 0 0 0 0 0 0 Register functions TxRqst32-1: Transmission request bit Bit Function 0 Indicates the sending idle state (neither the sending state nor the sending wait state). 1 Indicates the sending or sending wait state. The following shows conditions to set or reset the TxRqst bit. Setting conditions Set 1 to the WR/RD bit of the IFx Command Mask Register and 1 to the TxRqst bit, and write data to the IFx Command Request Register to set the TxRqst bit to a specific message object. Set 1 to the WR/RD bit of the IFx Command Mask Register, 0 to the TxRqst bit, and 1 to the Control bit, and 1 to the TxRqst bit of the IFx Me ssage Control Register. Then write data to the IFx Command Request Register to set the TxRqst bit to a specific message object. If the Dir bit is 1 and the RmtEn bit is 1, the Tx Rqst bit is set by receiving a remote frame that passed through the acce ptance filter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1253 MB9Axxx/MB9Bxxx Series
4. CAN Registers Resetting conditions Set 1 to the WR/RD bit of the IFx Command Mask Register, 0 to the TxRqst bit, and 1 to the Control, and 0 to the TxRqst bit of the IFx Message Control Register. Then write data to the IFx Command Request Register to reset the TxRqst bit of a specific message object. The TxRqst bit is reset when frame transmission has finished successfully. If the Dir bit is 1, the RmtEN bit is 0, and th e UMask bit is 1, the TxRqst bit is reset by receiving a remote frame that passed through the acceptance filter. In on e o f the following conditions, the messages may not be sent until any of the events described below occurs. Condition s : (1) A message buffer with the lowest priority is used for transmission. (2) The TxRqst bit was previously set to 1, but is set to 0 to abort transmission. (3) The TxRqst bit is set to 1 again at the timing of (2). Events : - A valid message flows on the CAN bus. - A transmission request is issued to another message buffer. - CAN is initialized by the Init bit. If canceling the transmission is required to suit system operations, execute the following steps. 1. Execute one of the following steps. Do not use a message buffer with the lowest priority as a send message buffer. After aborting the transmission, generate any of the above events. 2. Set the TxRqst bit to 1 again. If the message objects of ID28-0, DLC3-0, Xtd, and Data7-0 are changed while the TxRqst bit is 1, message objects before and after the change are mixed for transmission, or the message objects after the change may not be transmitted. Therefore, be sure to change them while the TxRqst bit is 0. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1254 MB9Axxx/MB9Bxxx Series