Fujitsu Series 3 Manual
Have a look at the manual Fujitsu Series 3 Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 86 Fujitsu manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
![Page 1354
1. Register Map
1. Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Module/function name and its base address
Clock/Reset
Base_Address : 0x4001_0000
FUJITSU SEMICONDUCTOR LIMITED
Base_Add re
ss Register
+ Addrress +3 +2 +1 +0
SCM_CTL[B,H,W]0x000 - - -
00000-0-
SCM_STR[B,H,W]0x004 - - -
00000-0-
STB_CTL[B,H,W] 0x008 00000000 00000000 -------- ---0--00
RST_STR[B,H,W] 0x00C -
-
-------0 00000-01...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1353.png "Page 1354
1. Register Map
1. Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Module/function name and its base address
Clock/Reset
Base_Address : 0x4001_0000
FUJITSU SEMICONDUCTOR LIMITED
Base_Add re
ss Register
+ Addrress +3 +2 +1 +0
SCM_CTL[B,H,W]0x000 - - -
00000-0-
SCM_STR[B,H,W]0x004 - - -
00000-0-
STB_CTL[B,H,W] 0x008 00000000 00000000 -------- ---0--00
RST_STR[B,H,W] 0x00C -
-
-------0 00000-01...")
![Page 1355
1. Register Map
FLASH_IF Base_Address : 0x4000_0000
Base_Address
Register
+ Address +3 +2 +1 +0
FASZR[B,H,W] 0x000
-------- -------- -------- ------10
FRWTR[B,H,W] 0x004 -------- -------- -------- ------10
FSTR[B,H,W] 0x008
-------- -------- -------- ------0X
0x00C *
FSYNDN[B,H,W] 0x010 -------- -------- -------- -----000
0x014 - 0x0FF - - - -
CRTRMM[B,H,W] 0x100
-------- -------- ------XX XXXXXXXX
0x104-0xFFF - - - -
FUJITSU SEMICONDUCTOR LIMITED
APPENDIXES
MN706-00002-1v0-E...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1354.png "Page 1355
1. Register Map
FLASH_IF Base_Address : 0x4000_0000
Base_Address
Register
+ Address +3 +2 +1 +0
FASZR[B,H,W] 0x000
-------- -------- -------- ------10
FRWTR[B,H,W] 0x004 -------- -------- -------- ------10
FSTR[B,H,W] 0x008
-------- -------- -------- ------0X
0x00C *
FSYNDN[B,H,W] 0x010 -------- -------- -------- -----000
0x014 - 0x0FF - - - -
CRTRMM[B,H,W] 0x100
-------- -------- ------XX XXXXXXXX
0x104-0xFFF - - - -
FUJITSU SEMICONDUCTOR LIMITED
APPENDIXES
MN706-00002-1v0-E...")
![Page 1356
1. Register Map
Clock/Reset Base_Address : 0x4001_0000
Base_Address
Register
+ Address +3 +2 +1 +0
SCM_CTL[W] 0x000 - - -
00000-0-
SCM_STR[W] 0x004 - - -
00000-0-
STB_CTL[W] 0x008
00000000 00000000 -------- ---0--00
RST_STR[W] 0x00C - -
-------0 0000--01
BSC_PSR[W] 0x010 - - -
-----000
APBC0_PSR[W] 0x014 - - -
------00
APBC1_PSR[W] 0x018 - - -
1--0--00
APBC2_PSR[W] 0x01C - - -
1--0--00
SWC_PSR[W] 0x020 - - -
X-----00
0x024 - 0x027 - - - -
TTC_PSR[W] 0x028 - - -...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1355.png "Page 1356
1. Register Map
Clock/Reset Base_Address : 0x4001_0000
Base_Address
Register
+ Address +3 +2 +1 +0
SCM_CTL[W] 0x000 - - -
00000-0-
SCM_STR[W] 0x004 - - -
00000-0-
STB_CTL[W] 0x008
00000000 00000000 -------- ---0--00
RST_STR[W] 0x00C - -
-------0 0000--01
BSC_PSR[W] 0x010 - - -
-----000
APBC0_PSR[W] 0x014 - - -
------00
APBC1_PSR[W] 0x018 - - -
1--0--00
APBC2_PSR[W] 0x01C - - -
1--0--00
SWC_PSR[W] 0x020 - - -
X-----00
0x024 - 0x027 - - - -
TTC_PSR[W] 0x028 - - -...")
2. Pin Description FUJITSU SEMICONDUCTOR LIMITED Chapter: Debug Interface FUJITSU SEMICONDUCTOR CONFIDENTIAL 8 2.4. Internal Pull-Ups of JTAG Pins As specified by the IEEE Standard, this series provides the JTAG pins that have internal pull-ups. If the functions of the pins are changed from JTAG to GPIO, the user can control pull-ups by setting the appropriate registers in the GPIO. Table 2-4 Enabled or disabled state of internal pull-ups of JTAG pins Pull-up with JTAG pins enabled *1 TCK/SWCLK Enabled TMS/SWDIO Enabled TDI Enabled TDO/SWO Enabled *2 TRSTX Enabled *1 : Pull-up is enabled on reset. *2 : Pull-up is disabled on output. CHAPTER 24: Debug Interface MN706-00002-1v0-E 1315 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 1316 MB9Axxx/MB9Bxxx Series
1. Register Map APPENDIXES This chapter shows the register map. 1. Register Map CODE: 9BFREGMAP-E01.2 FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1317 MB9Axxx/MB9Bxxx Series
1. Register Map
1. Register Map
Register map is shown on the table every module/function.
[How to read the each table]
Module/function name and its base address
Clock/Reset
Base_Address : 0x4001_0000
FUJITSU SEMICONDUCTOR LIMITED
Base_Add re
ss Register
+ Addrress +3 +2 +1 +0
SCM_CTL[B,H,W]0x000 - - -
00000-0-
SCM_STR[B,H,W]0x004 - - -
00000-0-
STB_CTL[B,H,W] 0x008 00000000 00000000 -------- ---0--00
RST_STR[B,H,W] 0x00C -
-
-------0 00000-01
The register table is represented in the little-endian.
When performing a data access, the addresses should be as below.
Word access : Address should be multiples of 4 (least significant 2 bits should be 0x00)
Half word access : Address should be multiples of 2 (least significant bit should be 0x0)
Byte access : -
Do not access the test register area.
Initial value after reset 1 : Initial value is 1
0 : Initial value is 0
X : Initial value is undefined
- : Reserved bit
Register name
Access unit (B : byte, H : half word, W : word)
Rightmost register address
(For word-length access, the +0
column of the register is the LSB of the data.
)
- : Reserved area
* : Test register area
APPENDIXES
MN706-00002-1v0-E
1318
MB9Axxx/MB9Bxxx Series
1. Register Map FLASH_IF Base_Address : 0x4000_0000 Base_Address Register + Address +3 +2 +1 +0 FASZR[B,H,W] 0x000 -------- -------- -------- ------10 FRWTR[B,H,W] 0x004 -------- -------- -------- ------10 FSTR[B,H,W] 0x008 -------- -------- -------- ------0X 0x00C * FSYNDN[B,H,W] 0x010 -------- -------- -------- -----000 0x014 - 0x0FF - - - - CRTRMM[B,H,W] 0x100 -------- -------- ------XX XXXXXXXX 0x104-0xFFF - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1319 MB9Axxx/MB9Bxxx Series
1. Register Map Clock/Reset Base_Address : 0x4001_0000 Base_Address Register + Address +3 +2 +1 +0 SCM_CTL[W] 0x000 - - - 00000-0- SCM_STR[W] 0x004 - - - 00000-0- STB_CTL[W] 0x008 00000000 00000000 -------- ---0--00 RST_STR[W] 0x00C - - -------0 0000--01 BSC_PSR[W] 0x010 - - - -----000 APBC0_PSR[W] 0x014 - - - ------00 APBC1_PSR[W] 0x018 - - - 1--0--00 APBC2_PSR[W] 0x01C - - - 1--0--00 SWC_PSR[W] 0x020 - - - X-----00 0x024 - 0x027 - - - - TTC_PSR[W] 0x028 - - - ------0 0x02C - 0x02F - - - - CSW_TMR[W] 0x030 - - - -000000 PSW_TMR[W] 0x034 - - - ---0-000 PLL_CTL1[W] 0x038 - - - 00000000 PLL_CTL2[W] 0x03C - - - ---00000 CSV_CTL[W] 0x040 - - -111--00 ------11 CSV_STR[W] 0x044 - - - ------00 FCSWH_CTL[W] 0x048 - - 11111111 11111111 FCSWL_CTL[W] 0x04C - - 00000000 00000000 FCSWD_CTL[W] 0x050 - - 00000000 00000000 DBWDT_CTL[W] 0x054 - - - 0-0----- 0x058 - 0x05F - - - - INT_ENR[W] 0x060 - - - --0--000 INT_STR[W] 0x064 - - - --0--000 INT_CLR[W] 0x068 - - - --0--000 0x06C - 0xFFF - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1320 MB9Axxx/MB9Bxxx Series
1. Register Map HW WDT Base_Address : 0x4001_1000 Base_Address Register + Address +3 +2 +1 +0 WDG_LDR[W] 0x000 00000000 00000000 11111111 11111111 WDG_VLR[W] 0x004 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WDG_CTL[W] 0x008 - - - ------11 WDG_ICL[W] 0x00C - - - XXXXXXXX WDG_RIS[W] 0x010 - - - -------0 0x014 - 0xBFF - - - - WDG_LCK[W] 0xC00 00000000 00000000 00000000 00000001 0xC04 - 0xFFF - - - - SW WDT Base_Address : 0x4001_2000 Base_Address Register + Address +3 +2 +1 +0 WdogLoad[W] 0x000 11111111 11111111 11111111 11111111 WdogValue[W] 0x004 11111111 11111111 11111111 11111111 WdogControl[W] 0x008 - - - ------00 WdogIntClr[W] 0x00C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX WdogRIS[W] 0x010 - - - -------0 0x014 - 0xBFF - - - - WdogLock[W] 0xC00 00000000 00000000 00000000 00000000 0xC04 - 0xFFF - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1321 MB9Axxx/MB9Bxxx Series
1. Register Map Dual_Timer Base_Address : 0x4001_5000 Base_Address Register + Address +3 +2 +1 +0 Timer1Load[W] 0x000 00000000 00000000 00000000 00000000 Timer1Value[W] 0x004 11111111 11111111 11111111 11111111 Timer1Control[W] 0x008 -------- -------- -------- 00100000 Timer1IntClr[W] 0x00C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Timer1RIS[W] 0x010 -------- -------- -------- -------0 Timer1MIS[W] 0x014 -------- -------- -------- -------0 Timer1BGLoad[W] 0x018 00000000 00000000 00000000 00000000 Timer2Load[W] 0x020 00000000 00000000 00000000 00000000 Timer2Value[W] 0x024 11111111 11111111 11111111 11111111 Timer2Control[W] 0x028 -------- -------- -------- 00100000 Timer2IntClr[W] 0x02C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Timer2RIS[W] 0x030 -------- -------- -------- -------0 Timer2MIS[W] 0x034 -------- -------- -------- -------0 Timer2BGLoad[W] 0x038 00000000 00000000 00000000 00000000 0x040 - 0xFFF - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1322 MB9Axxx/MB9Bxxx Series
1. Register Map MFT unit0 Base_Address : 0x4002_0000 MFT unit1 Base_Address : 0x4002_1000 Base_Address Register + Address +3 +2 +1 +0 OCCP0[H,W] 0x000 - - 00000000 00000000 OCCP1[H,W] 0x004 - - 00000000 00000000 OCCP2[H,W] 0x008 - - 00000000 00000000 OCCP3[H,W] 0x00C - - 00000000 00000000 OCCP4[H,W] 0x010 - - 00000000 00000000 OCCP5[H,W] 0x014 - - 00000000 00000000 OCSB10[B,H,W] OCSA10[B,H,W] 0x018 - - -110--00 00001100 OCSB32[B,H,W] OCSA32[B,H,W] 0x01C - - -110--00 00001100 OCSB54[B,H,W] OCSA54[B,H,W] 0x020 - - -110--00 00001100 OCSC[B,H,W] 0x024 - - --000000 - TCCP0[H,W] 0x028 - - 11111111 11111111 TCDT0[H,W] 0x02C - - 00000000 00000000 TCSA0[B,H,W] 0x030 - - 000---00 01000000 TCSB0[B,H,W] 0x034 - - -------- -----000 TCCP1[H,W] 0x038 - - 11111111 11111111 TCDT1[H,W] 0x03C - - 00000000 00000000 TCSA1[B,H,W] 0x040 - - 000---00 01000000 TCSB1[B,H,W] 0x044 - - -------- -----000 TCCP2[H,W] 0x048 - - 11111111 11111111 TCDT2[H,W] 0x04C - - 00000000 00000000 TCSA2[B,H,W] 0x050 - - 000---00 01000000 TCSB2[B,H,W] 0x054 - - -------- -----000 OCFS32[B,H,W] OCFS10[B,H,W] 0x058 - - 00000000 00000000 OCFS54[B,H,W] 0x05C - - - 00000000 ICFS32[B,H,W] ICFS10[B,H,W] 0x060 - - 00000000 00000000 0x064 - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1323 MB9Axxx/MB9Bxxx Series
1. Register Map Base_Address Register + Address +3 +2 +1 +0 ICCP0[H,W] 0x068 - - XXXXXXXX XXXXXXXX ICCP1[H,W] 0x06C - - XXXXXXXX XXXXXXXX ICCP2[H,W] 0x070 - - XXXXXXXX XXXXXXXX ICCP3[H,W] 0x074 - - XXXXXXXX XXXXXXXX ICSB10[B,H,W] ICSA10[B,H,W] 0x078 - - ------00 00000000 ICSB32[B,H,W] ICSA32[B,H,W] 0x07C - - ------00 00000000 WFTM10[H,W] 0x080 - - 00000000 00000000 WFTM32[H,W] 0x084 - - 00000000 00000000 WFTM54[H,W] 0x088 - - 00000000 00000000 WFSA10[H,W] 0x08C - - ---00000 000000 WFSA32[H,W] 0x090 - - ---00000 000000 WFSA54[H,W] 0x094 - - ---00000 000000 WFIR[H,W] 0x098 - - 00000000 0000--00 NZCL[H,W] 0x09C - - -------- ---00000 ACCP0[H,W] 0x0A0 - - 00000000 00000000 ACCPDN0[H,W] 0x0A4 - - 00000000 00000000 ACCP1[H,W] 0x0A8 - - 00000000 00000000 ACCPDN1[H,W] 0x0AC - - 00000000 00000000 ACCP2[H,W] 0x0B0 - - 00000000 00000000 ACCPDN2[H,W] 0x0B4 - - 00000000 00000000 ACSB[B,H,W] 0x0B8 - - - -000-111 ACSA[B,H,W] 0x0BC - - --000000 --000000 ATSA[H,W] 0x0C0 - - --000000 --000000 0x0C4 - 0xFFF - - - - FUJITSU SEMICONDUCTOR LIMITED APPENDIXES MN706-00002-1v0-E 1324 MB9Axxx/MB9Bxxx Series