Home > Fujitsu > Controller > Fujitsu Series 3 Manual

Fujitsu Series 3 Manual

Add to Favourites
    Download as PDF Print this page Share this page

    Have a look at the manual Fujitsu Series 3 Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 86 Fujitsu manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.

    View all the pages
    Page
    of 1384
    Add page 921 to Favourites
    image text
    Enable zoom 
    							 
4. Dedicated baud rate generator 
 
4.2.  CSIO (Clock Sync Serial Interface) setup procedure 
and program flow 
The CSIO (Clock Sync Serial Interface) allows bidirectional and synchronous serial data 
transmission. 
 CPU-to-CPU connection 
Select the bidirectional communication for the CSIO (C lock Sync Serial Interface). Connect two CPUs to 
each other as shown in Figure 4-1 . 
Figure 4-1 A connection example for CSIO (Clock Sync Serial Interface) bidirectional communication 
 
CPU_1 (Master)CPU_2 (Slave)
SOT
SIN
SCKSOT
SIN
SCK
  
  Flowcharts 
  If FIFO is not used 
 
Figure 4-2 An example of bidirectional communication flowchart (if FIFO is not used) 
 
(Master system)
Start
Set an operation 
format.
Set the 1-byte data 
in TDR and start 
communication.
RDRF=1
Read and process 
the receive data.
(Slave system)
Send data. Start
RDRF=1
Read and process 
the receive data.
Send the 1-byte 
data.
Yes
No No
Send data.
(ANS)
Set an operation format. (Matched with the 
master system)
Yes
  
  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
885 
MB9Axxx/MB9Bxxx  Series
    Add page 922 to Favourites
    image text
    Enable zoom 
    							 
4. Dedicated baud rate generator 
 
  If FIFO is used 
Figure 4-3 An example of bidirectional communication flowchart (if FIFO is used) 
 
(Master system)
Start
Set an operation 
format.
Set N bytes in the 
transmit FIFO buffer, 
and set FDRQ bit to 
0.
RDRF=1
(Slave system)
Send data. Start
RDRF=1
Yes
Yes
No No
Send data.
(ANS)
Enable the transmit/ receive FIFO.
Read and process 
the FBYTE data.
Read and process 
the FIFOBYTE data.
Set N bytes in the 
transmit FIFO buffer, 
and set FDRQ bit to 
0.
Set an operation format.
(Matched with the master system)
Set the receive  FBYTE.
Enable the transmit/receive FIFO.
Set the receive 
FBYTE.
  
   
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
886 
MB9Axxx/MB9Bxxx  Series
    Add page 923 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.  CSIO (Clock Sync Serial Interface) registers 
This section provides a list of CSIO (Clock Sync Serial Interface) registers. 
  CSIO (Clock Sync Serial  Interface) register list 
 
Table 5-1 CSIO (Clock Sync Serial Interface) register list 
  bit 15                           bit 8 bit 7                            bit 0
SCR (Serial Control Register)  SMR (Serial Mode Register) 
SSR (Serial Status Register) ESCR (Extended Communication Control Register)
RDR1/TDR1 (Transmit/Receive Data register 1)RDR0/TDR0 (Transmit/Receive Data register 0)
BGR1 (Baud Rate Generator Register 1) BGR0 (Baud Rate Generator Register 0) 
CSIO 
- - 
FCR1 (FIFO Control Register 1)  FCR0 (FIFO Control Register 0) FIFO 
FBYTE2 (FIFO2 Byte Register)  FBYTE1 (FIFO1 Byte Register) 
 
Table 5-2 CSIO (Clock Sync Serial Interface) bit assignment 
 Bit 15  Bit 14 Bit 13 Bit 12  Bit 11 Bit 10 Bit 09Bit 08 Bit 07 Bit 06Bit 05 Bit 04Bit 03  Bit 02  Bit 01Bit 00
SCR/ 
SMR  UPCL MS SPIRIE TIE TBIERXETXEMD2MD1MD0WUCRSCINV BDS SCKESOE
SSR/ 
ESCR  REC - - - ORE RDRFTDRETBISOP- - WT1WT0 L2 L1 L0
TDR/ 
RDR  - D8D7D6 D5 D4 D3 D2 D1 D0
BGR1/ 
BGR0 - B14 B13B12 B11 B10B9 B8B7 B6 B5 B4 B3 B2 B1 B0
- - 
- 
FCR1/ 
FCR0 FTST1 FTST0 
- FLSTE  FRIIE FDRQ FTIEFSEL - FLST FLDFSET FCL2 FCL1  FE2FE1
FBYTE2/ 
FBYTE1  FD15 FD14 FD13FD12 FD11 FD10FD9FD8FD7FD6FD5FD4FD3 FD2 FD1FD0
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
887 
MB9Axxx/MB9Bxxx  Series
    Add page 924 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.1.  Serial Control Register (SCR) 
The Serial Control Register (SCR) is used to  enable/disable a transmit/receive interrupt, 
enable/disable a transmit idle interrupt, and enable/disable data transmission and reception. 
Also, the register can set the SPI connection and reset the CSIO settings. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field UPCL MS SPI RIE TIE TBIE RXE TXE (SMR) 
Attribute  R/W R/W R/W  R/W R/W R/W R/W R/W    
Initial 
value  0 0 0 0 0 0 0 0    
 
[bit 15] UPCL: Programmable clear bit  Initializes the CSIO internal state. 
If set to 1: 
  The CSIO is reset directly (software reset). Howe ver, the current register settings are kept. The 
transmit or receive state is  disconnected immediately. 
   The baud rate generator reloads the BGR1/0 register value and restarts operation. 
   All of transmit/receive inte rrupt causes (SSR:TDRE, TBI, RDRF, ORE) are cleared. 
 
If set to 0: 
No operation is affected. 
0 is always read during reading. 
Description Bit  During writing During reading 
0 No  effect. 
1 Programmable  clear 0 is always read. 
 
 
  Disable an  i

nterrupt first, and then execute the progra mm
 able clear instruction. 
   If the FIFO operation is used, disable it (FCR0:FE2,  FE1=0) first and then execute the programmable 
clear instruction. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
888 
MB9Axxx/MB9Bxxx  Series
    Add page 925 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 14] MS: Master/Slave function select bit 
Selects the master or slave mode. 
  If set to 0: The master mode is selected. 
   If set to 1: The slave mode is selected. 
 
Bit Description 
0 Master  mode 
1 Slave mode 
 
 
  If th e sla

ve mode is selected and if SMR:SCKE =0, the extern
 al clock is entered directly. 
   After you have set the MS bit, enable data reception (RXE=1). 
 
[bit 13] SPI: SPI corresponding bit  This bit allows th e SPI co

mmunication. 
   If set to 0: Normal synchronous communication is started. 
   If set to 1: The SPI is corresponded. 
 
Bit Description 
0  Normal Sync transfer 
1 SPI  correspond 
 
[bit 12] RIE: Receive interrupt enable bit    This bit enables or disables an output  of receive interrupt request to the CPU. 
   If the RIE bit and the receive data flag bit (SSR:RDRF) are 1, or if any of error  flag bits (ORE) is 1, 
a receive interrupt request is output. 
 
Bit Description 
0  Disables the receive interrupt. 
1  Enables the receive interrupt. 
 
[bit 11] TIE: Transmit interrupt enable bit    This bit enables or disables an output of Transmit Interrupt Request to the CPU. 
   If the TIE and SSR:TDRE bits are 1, a Transmit Interrupt Request is output. 
 
Bit Description 
0  Disables a transmit interrupt. 
1  Enables a transmit interrupt. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
889 
MB9Axxx/MB9Bxxx  Series
    Add page 926 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 10] TBIE: Transmit bus idle interrupt enable bit 
  This bit enables or disables an output of tr ansmit bus idle interrupt request to the CPU. 
   If the TBIE bit and SSR:TBI bit are 1, a tr ansmit bus idle interrupt request is output. 
 
Bit Description 
0  Disables the transmit bus idle interrupt. 
1  Enables the transmit bus idle interrupt. 
 
[bit 9] RXE: Data receive enable bit  Enables or disables a CSIO data reception. 
  If set to 0: The data frame reception is disabled. 
   If set to 1: The data frame reception is enabled. 
 
Bit Description 
0  Disables data reception. 
1  Enables data reception. 
 
 
  If data reception is disabled (RXE=0),  the 

current data  reception is stopped immediately
 . 
   After you have set the MS bit and SMR:SCINV bit, enable the data reception (RXE=1). 
 
[bit 8] TXE: Data transmission enable bit  Enables or disables a CS IO 

data transmission. 
   If set to 0: The data frame transmission is disabled. 
   If set to 1: The data frame transmission is enabled.   
 
Bit Description 
0  Disables the transmission. 
1  Enables the transmission. 
 
 
If dat a

 transmission is disabled (TXE=0), the current data transmission is stopped immediately. 
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
890 
MB9Axxx/MB9Bxxx  Series
    Add page 927 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.2.  Serial Mode Register (SMR) 
The Serial Mode Register (SMR) is used to select an operation mode, to set a transmission 
direction, data length and serial clock inversion, and to enable or disable an output of serial 
data and clock to their pins. 
 
Bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SCR) MD2 MD1 MD0 WUCRSCINVBDS SCKE SOE 
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7:5] MD2, MD1, MD0: Operation mode set bits  These bits set an operation mode. 
0b000: Sets operation mode 0 (async normal mode). 
0b001: Sets operation mode 1 (async multiprocessor mode). 
0b010: Sets operation mode 2 (clock sync mode). 
0b011: Sets operation mode 3 (LIN communication mode). 
0b100: Sets operation mode 4 (I
2C mode). 
This section explains the registers and their operation in operation mode 2 (clock sync mode). 
Bit 7  Bit 6Bit 5  Description 
0 0 0 Operation mode 0 (async normal mode) 
0  0 1 Operation mode 1 (async multiprocessor mode) 
0  1 0 Operation mode 2 (clock sync mode) 
0  1 1 Operation mode 3 (LIN communication mode) 
1 0 0  Operation mode 4 (I2C mode) 
* This section explains the registers in operation mode 2. 
 
  Any  b

it setting other than above is inhibited. 
   To switch th e cu

rrent operation mode, issue a programmable clear in struction (SCR:UPCL=1) and switch 
the operation mode continuously. 
   After the operation mode has been switched, set each register correctly. 
 
[bit 4] WUCR: Wake-up control bit  Selects a pin to be  

used for an external interrupt. 
If this bit is set to 0: The INT pin is set as an external interrupt pin. 
If set to 1: The SCK pin is set as an external interrupt pin. 
Bit Description 
0  Disables the Wake-up function. 
1  Enables the Wake-up function. 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
891 
MB9Axxx/MB9Bxxx  Series
    Add page 928 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 3] SCINV: Serial clock invert bit 
Inverts the serial clock format. 
If set to 0: 
  The signal detect level of serial clock output is set to HIGH. 
   The transmit data is output at a falling edge of serial clock during normal transfer, but it is output in 
synchronization with a rising edge of serial clock during SPI transfer. 
   The receive data is sampled at a rising edge of serial clock during normal transfer, but it is sampled at a 
falling edge of serial clock during SPI transfer. 
 
If set to 1: 
   The signal detect level of serial clock output is set to LOW. 
   The transmit data is output at a rising edge of serial clock during normal transfer, but it is output in 
synchronization with a falling edge of serial clock during SPI transfer. 
   The receive data is sampled at a falling edge of serial  clock during normal transfer, but it is sampled at a 
rising edge of serial clock during SPI transfer. 
 
Bit Description 
0  Signal level HIGH detection format 
1  Signal level LOW detection format 
 
 
  Always set th is b

it when tran
 smission and reception are disabled (TXE=RXE=0). 
   After you have set the SCINV bit,  enable data reception (SCR:RXE=1). 
 
[bit 2] BDS: Transfer direction select bit  Specifies to transm it th

e least significant bit of the tran smit serial data first (LSB first; BDS=0) or the most 
significant bit first (MSB first; BDS=1). 
Bit Description 
0  LSB first (The least significant bit is first transferred.) 
1 MSB first (The most significa nt bit is first transferred.) 
 
 
Always set th is b

it when transmission an d reception are disabled  (SCR:T
 XE=RXE=0). 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
892 
MB9Axxx/MB9Bxxx  Series
    Add page 929 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
[bit 1] SCKE: Master mode serial clock output enable bit 
This bit controls the serial clock I/O port. 
Bit Description 
0  Disables a serial clock output. 
1  Enables a serial clock output. 
 
 
If this 

bit is used as the SCK pi n, the GPIO must also be se
 t. 
 
[bit 0] SOE: Serial data output enable bit  This bit enab les or 

disables a serial data output. 
Bit Description 
0  Disables a serial data output. 
1  Enables a serial data output. 
 
 
If this 

bit is used as the SOUT pin, the GPIO must also be set. 
  
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
893 
MB9Axxx/MB9Bxxx  Series
    Add page 930 to Favourites
    image text
    Enable zoom 
    							 
5. CSIO (Clock Sync Serial Interface) registers 
 
5.3.  Serial Status Register (SSR) 
The Serial Status Register (SSR) is used to check the current transmission/reception state, 
check the Receive Error flag, and clears the Receive Error flag. 
 
Bit 15 14 13 12 11 10 9 8 7 ... 0 
Field REC - - - ORE RDRFTDRETBI (ESCR) 
Attribute  R/W - -  - R R  R R    
Initial 
value  0 - - - 0 0 1 1    
 
[bit 15] REC: Receive error flag clear bit  This bit clears the ORE flag of th e Serial Status Register (SSR). 
   If this bit is set to 1, the error flag is cleared. 
   This bit has no effect if set to 0. 
 
0 is always read during reading. 
Description Bit  During writing  During reading 
0 No effect. 
1 Clears the Receive Error flag (FRE, ORE).  0 is always read. 
 
[bit 14:12] Reserved bits  This bit value is undefined when read. 
This bit has no effect when written. 
 
[bit 11] ORE: Overrun error flag bit    If an overrun occurs during data receptio n, this bit is set to 1. This is cleared if the REC bit of Serial 
Status Register (SSR) is set to 1. 
   If the ORE and SCR:RIE bits are 1, a receive interrupt request is output. 
   If this flag is set, data of the R eceive Data Register (RDR) is invalid. 
   If this flag is set when receive FIFO is used, the recei ve FIFO enable bit is cleared and the receive data is 
not stored in receive FIFO. 
 
Bit Description 
0  No overrun error occurred. 
1 An overrun error occurred. 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  19-3: CSIO  \050Clock  Sync Serial  Interface\051 
MN706-00002-1v0-E 
894 
MB9Axxx/MB9Bxxx  Series
    All Fujitsu manuals Comments (0)