Fujitsu Series 3 Manual
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5. USB Function Registers 5.3. EP1 to 5 Control Registers (EP1C to EP5C) The EP1 to 5 Control Registers (EP1C to EP5C) control Endpoints 1 to 5. The following figure shows the bit configuration of the EP1 to 5 Control Registers (EP1C to EP5C). EP1 Control Register (EP1C) bit 15 14 13 12 11 10 9 8 Field EPEN TYPE DIR DMAE NULE STAL PSK1 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 11 0 0 0 0 1 bit 7 6 5 4 3 2 1 0 Field PSK1 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 EP2 to 5 Control Registers (EP2C to EP5C) bit 15 14 13 12 11 10 9 8 Field EPEN TYPE DIR DMAE NULE STAL Reserved Attribute R/W R/W R/W R/W R/W R/W R/W - Initial value 0 11 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 Field Reserved PKS5 to 2 Attribute - R/W R/W R/W R/W R/W R/W R/W Initial value 0 1 0 0 0 0 0 0 Except DM AE, NULE, and STAL, the EP1 to 5 Control Registers (EP1C to EP5C) must be configured while bot h of the bit 7 RST in the UDC Control Register (UDCC) and bit 15 BFINI in the EP0 to 5 Status Registers (EP1S to EP5S) are 1. They mu st not be rewritten while USB is running. The following explains the function of each bit in the EP1 to 5 Control Registers (EP1C to EP5C). [bit 15] EPEN: Endpoints 1 to 5 Enable Bits (EndP oint1 to 5 ENable) This bit enables the Endpoint. Based on the EPEN bit setting, the Endpoint is configured by the host as those used by the function. TYPE, DIR and PKS in the EP1 to EP5 Control Registers are valid as the configuration information. Bit Description 0 Disables the Endpoint 1 Enables the Endpoint FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1115 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [bit 14:13] TYPE: Endpoint Transfer Type Select Bits (endpoint TYPE) These bits specify the transfer type the Endpoint support. Bit 14:13 Description 00 Setting disabled 01 Setting disabled 10 Bulk transfer 11 Interrupt transfer [bit 12] DIR: Endpoint Transfer Dire ction Select Bit (endpoint DIRection) This bit specifies the transfer direction the Endpoint support. Bit Function operating mode Host operating mode (EP1 and EP2 only) 0 OUT Endpoint IN Endpoint 1 IN Endpoint OUT Endpoint [bit 11] DMAE: DMA Automatic Transfer Enable Bit (DMA Enable) This bit sets a mode that uses DMA for writing or r eading transfer data to/from send/receive buffer, and automatically transfers the send/receive data synchronized with an data request in the IN or OUT direction by the host. Until the data size set in the DMA is reached, the data is transferred. Bit Description 0 Releases the automatic buffer transfer mode 1 Sets the automatic buffer transfer mode The CPU mu st not access t he send/receive buffer while the DMAE bit is s et to 1 . For data transfer in the OUT direction, set the DMA transfer size to the multiples of that set in PKS in the EP1 to 5 Control Registers (EP1C to EP5C). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1116 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [bit 10] NULE: Null Automatic Transfer Enable Bit (NULl Enable set) When a data transfer request in IN the direction is received while automatic buffer transfer mode is set (DMAE = 1), this bit sets a mode that transfers 0-byte data automatically upon the detection of the last packet transfer. Bit Description 0 Releases the NULL automatic transfer mode 1 Sets the NULL automatic transfer mode For data transfer in th e OUT direction or when automatic buffer transfer m ode is not set, the NULL bit configuration does not affect communication. [bit 9] STAL: Endpoints 1 to 5 Stall Setting Bit (STALl set) This bit can set Endpo i nt to the STALL state (STALL response). When the STALCLREN bit of the UDC Control Register (UDCC) is 0 This bit in not cleared to 0 by the Clear Feature command.This bit must be cleared by software. For the timing to clear this bit, see Stall response processed by software of 3.9 Stall r esponse/release of en dpoints 1 to 5. Bit Description 0 Release the STALL state 1 Sets the STALL state (STALL response) When the STALCLREN bit of the UDC Control Register (UDCC) is 1 This bit is cleared by hardware. It is cleared to 0 for the Endpoint specified by the Clear Feature command.For the timing to clear this bit, see Stall response processed by software of 3.9 Stall r esponse/release of en dpoints 1 to 5. Bit Description 0 Ignored 1 Sets the STALL state (STALL response) If th e ST ALCLREN bit of the UDC Control Register (UDCC) is 0, the STALL response remains operating to the ho st while the STAL bit is set to 1. Restoration from the STALL state is possible by the Clear Feature command after resetting the STAL bit. The value read by a read-modify-write instruction differs depending on the value set in STALCLREN. When STALCLREN = 0, the value at that time is read. When STALCLREN = 1,0 is read. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1117 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [EP2 to EP5: bit 8:7] EP2 to EP5 reserved bits In EP2 to EP5, these bits are reserved.Write value s hould always be 0. They are always read as 0. [(EP1: bit 8:7) bits 6:0] PKS: Packet Si ze Setting Bits (PacKet Size ep1 set) This bit specifies the maximum size transferred by one packet. The following shows the maximum packet size that can be specified for Endpoints 1 to 5. EndPoint Maximum transfer size Configurable range 1 256 bytes (Odd numbers allowed) 0x001 to 0x100 2 to 5 64 bytes (Odd numbers allowed) 0x01 to 0x40 A v alue exceeding the maximum number of transferable bytes (0x100 or 0x40), and 0x00 must not be written. For End p oints 2 to 5, write 00 to bit 8 to 7,Also when automatic buffer transfer mode (DMAE = 1) is used, 0 to 2 must not be written to the relevant Endpoint. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1118 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers 5.4. Time Stamp Register (TMSP) The Time Stamp Register (TMSP) indicates the frame number upon the receipt of SOF packets. The following figure shows the bit configuration of the Time Stamp Register (TMSP). bit 15 14 13 12 11 10 9 8 Field ReservedReserved Reserved TMSP Attribute - - - R R R Initial value X X XXX 0 0 0 RST reset 0 0 Irrelevant 0 0 0 bit 7 6 5 4 3 2 1 0 Field TMSP Attribute R R R R R R R R Initial value 0 0 0 0 0 0 0 0 RST reset 0 0 0 0 0 0 0 0 The following explains the function of each bit in the Time Stamp Register (TMSP). [bit 15:11] Reserved bits The written value has no effect. The read value is undefined. [bit 10:0] TMSP: Time Stamp Bits (TiMe StamP) These bits indicate the frame number of a received SO F packet. The frame number is updated upon the receipt of a SOF packet. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1119 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers 5.5. UDC Status Register (UDCS) The UDC Status Register (UDCS) indicates the bus status during USB communication or the reception of specific commands.Each bit except the SETP bit is an interrupt cause, and so can generate an interrupt to the CPU if the correspondent interrupt enable bit is enabled. The following figure shows the bit configuration of the UDC Status Register (UDCS). bit 7 6 5 4 3 2 1 0 Field - - SUSP SOF BRST WKUP SETP CONF Attribute - - R/W R/W R/W R/W R/W R/W Initial value X X 0 0 0 0 0 0 RST reset X X 0 0 0 0 0 0 The following explains the function of each bit in the UDC Status Register (UDCS). [bit 7:6] Undefined bits The written value has no effect. The read value is undefined. [bit 5] SUSP: Suspend detection bit (SUSPend) This bit indicates that the USB function makes transitio n to suspend state. The SUSP bit is an interrupt cause, and writing 1 is ignored. Clear it by writing 0. A read-modify-write access reads the bit as 1. Bit Description 0 Suspend undetected. Clears the interrupt cause. 1 Suspend detected [bit 4] SOF: SOF Detection Bit (Start Of Freame) This bit indicates that a SOF packet has been recei ved, and then the Time Stamp Register value is updated.The SOF bit is an interrupt cause, and writing 1 is ignored. Clear it by writing 0. A read-modify-write access r eads the bit as 1. Bit Description 0 SOF unreceived. Clears the interrupt cause. 1 SOF packet received FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1120 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [bit 3] BRST: Bus Reset Detection Bit (Bus ReSeT) This bit indicates the detection of a USB bus reset. The BRST bit is an interrupt cause, and writing 1 is ignored. Clear it by writing 0. A read-m odify-write access reads the bit as 1. Bit Description 0 USB bus reset undetected. Clears the interrupt cause. 1 USB bus reset detected When t his bit is detected, initialize the buffer by the BFINI bit in the EP0I Status Register (EP0IS), the BFINI bi t in the EP0O Status Register (EP0OS), an d the BFINI bit in the EP1 to EP5 Status Registers (EP1S to EP5S). [bit 2] WKUP: Wake-up Detection Bit (WaKe UP) This bit i ndicates that the USB function has resumed from suspend state. Remote wake-up caused by the RESUM bit setting, and wake-up caused by a request from the host are the resume sources, but the WKUP bit is automatically set only by a resume request by the host.The WKUP bit is an interrupt cause, and writing 1 is ignored.Clear it by writing 0.A read-modify-write access reads the bit as 1. Bit Description 0 Host caused resume undetect ed. Clears the interrupt cause. 1 Host caused resume detected Even when wake-up caused by a host request occurs, this bit is not set if t he RESUM bit in the UDCC register has been set. [bit 1] SETP: Setup Stage Detection Bit (SETuP) This bit ind i cates that the received data is the setup stage of USB control transfer. Writing 1 to this bit is ignored. Clear it by writing 0. A read-m odify-write access reads the bit as 1. Bit Description 0 SETUP stage unreceived. Clears the source. 1 Setup stage of control transfer received The SETP bit is not set during standard command automatic response. This bit is not an interrupt cause. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1121 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [bit 0] CONF: Configuration Detection Bit (CONFigration) This bit indicates that the USB function has been configured. The CONF bit is set when SetConfig of a USB command is received successfully. The CONF bit is an interrupt cause, and writing 1 is ignored. Clear it by writing 0.A read-modify-w rite access reads the bit as 1. Bit Description 0 SetConfig undetected. Clears the interrupt cause. 1 SetConfig detected FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1122 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers 5.6. UDC Interrupt Enable Register (UDCIE) The UDC Interrupt Enable Register (UDCIE) enables each bit (except the CONFN bit), interrupts generated by each interrupt cause of the UDC Status Register . The following figure shows the bit configuration of the UDC Interrupt Enable Register (UDCIE). bit 15 14 13 12 11 10 9 8 Field ReservedReserved SUSPIESOFIE BRSTIEWKUPIE CONFN CONFIE Attribute - - R/W R/W R/W R/W R R/W Initial value 0 0 0 0 0 0 0 0 RST reset 0 Irrelevant 0 0 0 0 0 0 The following explains the function of each bit in the UDC Interrupt Enable Register (UDCIE). [bit 15:14] Reserved bits These bits are reserved. Always write 0 to these bits. They are always read as 0. [bit 13] SUSPIE: Suspend Interrupt E nable Bit (SUSP Interrupt Enable) This bit enables interrupts generated by the SUS P interrupt cause of the UDC Status Register. Bit Description 0 Disables interrupts generated by the SUSP cause 1 Enables interrupts generated by the SUSP cause [bit 12] SOFIE: SOF Reception Interr upt Enable Bit (SOF Interrupt Enable) This bit enables interrupts generated by the SOF interrupt cause of the UDC Status Register. Bit Description 0 Disables interrupts generated by the SOF cause 1 Enables interrupts generated by the SOF cause [bit 11] BRSTIE: Bus Reset Enable Bit (BRST Interrupt Enable) This bit enables interrupts generated by the BRS T interrupt cause of the UDC Status Register. Bit Description 0 Disables interrupts generated by the BRST cause 1 Enables interrupts generated by the BRST cause FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1123 MB9Axxx/MB9Bxxx Series
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5. USB Function Registers [bit 10] WKUPIE: Wake-up Interrupt Enable Bit (WKUP Interrupt Enable) This bit enables interrupts generated by the WKU P interrupt cause of the UDC Status Register. Bit Description 0 Disables interrupts generated by the WKUP cause 1 Enables interrupts generated by the WKUP cause [bit 9] CONFN: Configuration Number Indication Bit (CONFigration Number) This bit indicates the configuration number. The information is updated when the CONF interrupt cause of the UDC Status Register is set. Bit Description 0 CONFIG number 0 1 CONFIG number 1 [bit 8] CONFIE: Configuration Interrupt Enable Bit (CONFigration) This bit enables interrupts generated by the CONF interrupt cause of the UDC Status Register. Bit Description 0 Disables interrupts generated by the CONF cause. 1 Enables interrupts generated by the CONF cause. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1124 MB9Axxx/MB9Bxxx Series