Fujitsu Series 3 Manual

							FUJITSU SEMICONDUCTOR LIMITED 
 Acknowledgement reception by first byte transmission 
When the data direction bit (R/W) is output, the I2C interface receives acknowledgement from a slave. The 
following lists operations to enable/disable FIFO. 
Table 2-2 Operations after acknowledgement reception with DMA mode disabled  (IBSR:RSA bit=0, SSR:DMA bit=0) 
Operation immediately after receiving acknowledgement Transmit 
FIFO  Receive 
FIFO  Transmit 
FIFO 
status Receive 
FIFO 
status  Data 
direction  bit 
(R/W) Acknowledgement: ACK 
Acknowledgement: 
NACK 
0 
Disable Disable  - - 
1 If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state.  Sets the IBCR:INT bit 
to 1 with the wait 
state. 
Without 
data  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state. 
With 
data  0 
Sets the IBCR:INT bit to 1 with the wait 
state. Disable Enable  - 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state.  Sets the IBCR:INT bit 
to 1 with the wait 
state. 
0 
Enable Disable 
- - 
1 If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state. 
Sets the IBCR:INT bit 
to 1 with the wait 
state. 
Without 
data  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state. 
With 
data  0 
Sets the IBCR:INT bit to 1 with the wait 
state. Enable Enable  - 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the IBCR:INT bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
IBCR:INT bit stays 0 without the wait 
state.  Sets the IBCR:INT bit 
to 1 with the wait 
state. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
975 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Table 2-3 Operations after acknowledgement reception with DMA mode enabled (IBSR:RSA bit=0, SSR:DMA bit=1) 
Operation immediately after receiving acknowledgement Transmit 
FIFO  Receive 
FIFO  Transmit 
FIFO 
status Receive 
FIFO 
status  Data 
direction  bit 
(R/W) Acknowledgement: ACK 
Acknowledgement: 
NACK 
0 
Disable Disable  - - 
1 If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. Sets the IBCR:INT bit 
to 1 with the wait 
state. 
Without 
data  If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. 
With 
data  0 
Sets the IBCR:INT bit to 1 with the wait 
state. Disable Enable  - 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. Sets the IBCR:INT bit 
to 1 with the wait 
state. 
0 
Enable Disable 
- - 
1 If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. Sets the IBCR:INT bit 
to 1 with the wait 
state. 
Without 
data  If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. 
With 
data  0 
Sets the IBCR:INT bit to 1 with the wait 
state. Enable Enable  - 
- 1  If the SSR:TDRE bit is set to 1, the 
interface sets the SSR:TBI bit to 1 and 
waits. If the SSR:TDRE bit is set to 0, 
SSR:TBI bit stays 0 wi
thout the wait state. Sets the IBCR:INT bit 
to 1 with the wait 
state. 
 
 
 When DMA mode is disabled (SSR:DMA=0) 
To disable FIFO (To disable both transmit FIFO and receive FIFO) 
  When the IBSR:RSA bit is set to 0, after receiving  acknowledgement, the interface sets the interrupt 
flag (IBCR:INT) to 1 if the SSR:TDRE bit is set  to 1 and waits while maintaining SCL at LOW. 
Writing 0 to the interrupt flag sets the interrupt flag to 0, which releases wait. If the SSR:TDRE bit is 
set to 0, the interface generates a clock on SCL  upon reception of ACK without setting the interrupt 
flag to 1. 
   When the IBSR:RSA bit is set to 1, after receivi ng a reserved address (before acknowledgement), the 
interface sets the interrupt flag (IBCR:INT) to 1  and waits while maintaining SCL at LOW. After 
reading from the RDR register, setting the IBCR:AC KE bit and transmit data and writing 0 to the 
interrupt flag causes the interrupt flag  to be set to 0, which releases wait. 
   The received acknowledgement is se t to the IBSR:RACK bit. The interface checks the IBSR:RACK bit 
during wait, and, in case of NA CK, it writes 0 to the IBCR:MSS bit or 1 to the IBCR:SCC bit to 
generate a stop condition or iteration start condition. At this time, the IBCR:INT bit is cleared to 0 
automatically. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
976 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
To enable FIFO   Before setting 1 to the IBCR:MSS bit, it is needed to set the following for FIFO. 
   When transmitting to a slave (the data direction bit=0), data including the slave address must be set 
to transmit FIFO. 
   When receiving data from a slave (the data direction  bit=1), the FIFO Byte Register must be set with 
the number of data sets to be received, and  dummy data must be written to the Transmit Data 
Register for the slave address, data direction bit an d the data volume for the number of bytes to be 
received. 
   When the IBSR:RSA bit is set to 0, after receiving acknowledgement and if  it is ACK, the interface 
transmits/receives data according to the data direc tion bit without setting the interrupt flag (IBCR:INT) 
to 1 (with no wait occurring). If it is NACK, the interfa ce sets the interrupt flag (IBCR:INT) to 1, and 
waits while maintaining SCL at LOW. 
   The received acknowledgement is stored in the IB SR:RACK bit. The interface checks the IBSR:RACK 
bit during wait, and, in case of NACK, it writes 0 to the IBCR:MSS bit or 1 to the IBCR:SCC bit to 
generate a stop condition or iteration start condition. At this time, the IBCR:INT bit is cleared to 0 
automatically. 
 When DMA mode is enabled (SSR:DMA=1) 
To disable FIFO (To disable both transmit FIFO and receive FIFO) 
  When the IBSR:RSA bit is set to 0, after receivi ng acknowledgement, the interface sets the transmit 
bus idle flag (SSR:TBI) to 1 if the SSR:TDRE bit is set to 1 and waits while maintaining SCL at 
LOW. Writing data to be transmitted to the TDR register  causes the transmit bus idle flag to be set to 0, 
which releases wait. If the SSR:TDRE bit is set to  0, the interface generates a clock on SCL upon 
reception of ACK without setting the tran smit bus idle flag (SSR:TBI) to 1. 
   When the IBSR:RSA bit is set to 1, after receivi ng a reserved address (before acknowledgement), the 
interface sets the interrupt flag (IBCR:INT) to 1  and waits while maintaining SCL at LOW. After 
reading from the RDR register, setting the IBCR:AC KE bit and transmit data and writing 0 to the 
interrupt flag causes the interrupt flag  to be set to 0, which releases wait. 
   The received acknowledgement is se t to the IBSR:RACK bit. The interface checks the IBSR:RACK bit 
during wait, and, in case of NA CK, it writes 0 to the IBCR:MSS bit or 1 to the IBCR:SCC bit to 
generate a stop condition or iteration start condition. At this time, the IBCR:INT bit is cleared to 0 
automatically. 
 
To enable FIFO    Before setting 1 to the IBCR:MSS bit, it is needed to set the following for FIFO. 
   When transmitting to a slave (the data direction bit=0), data including the slave address must be set 
to transmit FIFO. 
   When receiving data from a slave (the data direction  bit=1), the FIFO Byte Register must be set with 
the number of data sets to be received, and  dummy data must be written to the Transmit Data 
Register for the slave address, data direction bit an d the data volume for the number of bytes to be 
received. 
   When the IBSR:RSA bit is set to 0, after receiving acknowledgement and if  it is ACK, the interface 
transmits/receives data according to the data direc tion bit without setting the interrupt flag (IBCR:INT) 
to 1 (with no wait occurring). If it is NACK, the interfa ce sets the interrupt flag (IBCR:INT) to 1, and 
waits while maintaining SCL at LOW. 
   The received acknowledgement is stored in the IB SR:RACK bit. The interface checks the IBSR:RACK 
bit during wait, and, in case of NACK, it writes 0 to the IBCR:MSS bit or 1 to the IBCR:SCC bit to 
generate a stop condition or iteration start condition. At this time, the IBCR:INT bit is cleared to 0 
automatically. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
977 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-7 Acknowledgement   (when FIFO is disabled, IBSR:RSA=0, and ACK response is selected) 
                            Set to L by INT bit.                         Data 
SCL                                                                
SDA                  R/W           ACK                           
                                                Set to 0. 
INT bit 
 
RACK bit 
 
FBT  bit  
 
TDRE bit 
Write in the TDR register.
 
The following describes the wait timing for an address.   
 - After receiving acknowledgment  if the IBSR:RSA bit is 0. 
  - Before    receiving acknowledgment if the IBSR:RSA bit is 1. 
Not dependent on the setting of the IBCR:WSEL. 
Figure 2-8 Acknowledgement    (when FIFO is disabled, IBSR:RSA=0, and NACK response is selected) 
                           Set to L by INT bit. 
SCL                                                                
SDA                   R/W          NACK                           
                                               Set to 0. 
IN T bi t 
 
MSS bit 
 
RACK bit  
 
FB T b it  
Stop condition
 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
978 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-9 Acknowledgement   (when FIFO is disabled, IBSR:RSA=1, and ACK response is selected) 
                            Set to L by INT bit.                     Data 
SCL                                                                
SDA                   R/W                        ACK                          
                                               Set to 0. 
IN T bi t 
 
RA CK  bi t 
 
FB T b it  
 
RS A bit  
 
RD RF  bit  
The RDR  register is read. 
 
 
Figure 2-10 Acknowledgement    (when FIFO is disabled, IBSR:RSA=1, and NACK response is selected) 
                            Set to L by INT bit. 
SCL                                                                
SDA                   R/W                        NACK                            
                                               Set to 0. 
INT bit                        
 
MSS bit 
 
RA CK  bit  
 
FB T b it  
 
RS A bit  
 
RD RF  bit  
Stop condition
The RDR  register is read.
 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
979 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Figure 2-11 Acknowledgement (when FIFO is enabled, transmit FIFO has data, receive FIFO 
has no data, IBSR:RSA=0, and ACK response is selected) 
                                                         Data 
SCL                                                               
SDA                   R/W          ACK                         
                                                
IN T bit   
RA CK  bit  
 
FB T b it  
  TDRE bit 
 
 
 Data transmission by the master 
When the data direction bit (R/W) is set to 0, data are transmitted from the master. The slave gives 
response either with ACK or NACK for each one-byte transmission.   
The following shows the wait timing by IBCR:WSEL setting. 
Table 2-4 IBCR:WSEL bit status for master data transmission when DMA mode is disabled  (SSR:DMA=0) 
WSEL bit Operation 
0   
After the second byte, after 
acknowledgement with 1 set for the SSR:TDRE bit or upon 
detection of arbitration lost, the interrupt flag  (IBCR:INT) is set to 1 and SCL to LOW for the 
wait state. 
 
Starts the wait state by setting the interrupt flag  (IBCR:INT) to 1 after acknowledgement upon 
detection of arbitration lost or when no more valid data remain in the Transmit Data Register 
(SSR:TDRE=1). 
1   
After the second byte, after the master has transmitted one-byte data with 1 set for the 
SSR:TDRE bit or upon detection of arbitration lo
st, the interrupt flag (IBCR:INT) is set to 1 
and SCL to LOW for the wait state. 
 
Starts the wait state by setting the interrupt flag (IBCR:INT) to 1 when data transmission has 
taken place after detection of arbitration lost or no  more valid data in the Transmit Data Register 
(SSR:TDRE=1). 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
980 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Table 2-5 IBCR:WSEL bit status for master data transmission when DMA mode is enabled (SSR:DMA=1) 
WSEL bit Operation 
0   
After the second byte, after acknowledgement with 1 set for 
the SSR:TDRE bit, the transmit 
bus idle flag (SSR:TBI) is set to 1 and SCL  to LOW for the wait state after acknowledgement 
with 1 set for the SSR:TDRE bit. 
 
Starts the wait state by setting the transmit bus idle flag (SSR:TBI) to 1 after acknowledgment 
when no more valid data remain in the Transmit Data Register (SSR:TDRE=1). 
1   
After the second byte, after the master has transmitted one-byte data with 1 set for the 
SSR:TDRE bit, the transmit bus idle flag (SSR:TBI) is set to 1 and SCL to LOW for the wait 
state. 
 
Starts the wait state by setting the transmit bus idle flag (SSR:TBI) to 1 after the master has 
transmitted one-byte data when no more valid data remain in the Transmit Data Register 
(SSR:TDRE=1). 
 
In the following case, however, the interrupt flag (I
BCR:INT) is set after acknowledgement, regardless of 
the IBCR:WSEL setting: 

 If NACK is received when the stop condition (IBCR:MSS=0, ACT=1) is not set. 
 
The following shows an ex ample procedure for transmitting data to a slave. 
 Data Transmission to slave when DMA mode is disabl ed (SSR:DMA=0) 
1.  To transmit data to an address other than the reserved: 

 When transmit FIFO is disabled: 
1.
 Sets Slave Address (including the data direction  bit) to the TDR register and writes 1 to the 
IBCR:MSS bit.   
2.
 ACK is received after the Slave Address setting is  transmitted, and then the interrupt flag 
(IBCR:INT) is set to 1. 
3.
 Writes transmit data to the TDR register. 
4.
 Writes 0 to the interrupt flag (IBCR:INT) upon updating of the IBCR:WSEL bit and releases the 
wait state of the I2C bus. 
5.
 After transmitting one byte, the interrupt flag is set to 1, which puts the I2C bus in the wait state 
after receiving acknowledgment in case of IBCR:WSEL=0, and directly after transmitting one 
byte in case IBCR:WSEL=1. Repeats steps 3 to 5 until all the specified number of data sets have 
been transmitted. However, if NACK is recei ved after the wait state is released when 
IBCR:WSEL=1, another interrupt is generated afte r receiving acknowledgement and the bus enters 
the wait state. 
6.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1 to generate the stop condition or 
iteration start condition. 
 

 When transmit FIFO is enabled: 
1.
 Writes an address for Slave Address (including the  data direction bit) and transmit data to the TDR 
register. 
2.
 Writes 1 to the IBCR:MSS bit upon setting of the IBCR:WSEL bit. 
3.
 If NACK is received during transmission, sets  the interrupt flag (IBCR:INT) to 1 immediately 
after that to put the I2C bus in the wait state. If ACK responses  are received for all bytes, sets the 
interrupt flag to 1 according to the setting of IBCR:WSEL after the last byte is transmitted to put 
the I2C bus in the wait state. 
4.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1 to generate the stop condition or 
iteration start condition. 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
981 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
2. To transmit data to a reserved address: 

 When transmit FIFO is disabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit. 
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes transmit data to the TDR register. 
5.
 Writes 0 to the interrupt flag (IBCR:INT) upon updating of the IBCR:WSEL bit and releases the 
wait state of the I2C bus. 
6.
 After transmitting one byte, the interrupt flag is set to 1, which puts the I2C bus in the wait state 
after receiving acknowledgment in case of IBCR:WSEL=0, and directly after transmitting one 
byte in case IBCR:WSEL=1. Repeats steps 4 to 6 until all the specified number of data sets have 
been transmitted. However, if NACK is recei ved after the wait state is released when 
IBCR:WSEL=1, another interrupt is generated afte r receiving acknowledgement and the bus enters 
the wait state. 
7.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1 to generate the stop condition or 
iteration start condition. 
 

 When transmit FIFO is enabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit.  
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes all transmit data to the TDR register (un til transmit FIFO becomes full if it is the case). 
5.
 If NACK is received during transmission, the inte rrupt flag (IBCR:INT) is set to 1 immediately 
after that to put the I2C bus in the wait state. 
If ACK responses are received for all bytes, sets th e interrupt flag to 1 according to the setting of 
IBCR:WSEL after the last byte is transmitted to put the I
2C bus in the wait state. 
6.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1 to generate the stop condition or 
iteration start condition. 
  *1 :  When any one of the following conditions is met, the IBCR:ACKE and IBCR:WSEL bits must  be set to 1 and to check which is needed for the next data, operation as a master or operation 
as a slave. 

 Multi-master mode is activated and the reserved address is a general call. 

 Arbitration lost has been detected and the interface may operate as a slave. 
 Data Transmission to slave when DMA mode is enabled (SSR:DMA=1) 
1.   To transmit data to an address other than the reserved: 

 When transmit FIFO is disabled: 
1.
 Sets Slave Address (including the data direction  bit) to the TDR register and writes 1 to the 
IBCR:MSS bit.   
2.
 ACK is received after the Slave Ad dress setting is transmitted, and then the transmit bus idle flag 
(SSR:TBI) is set to 1. 
3.
 Writes data to be transmitted to the TDR re gister to release the wait state of the I2C bus. 
4.
 After transmitting one byte, sets the transmit  bus idle flag (SSR:TBI) to 1 to put the I2C bus in 
the wait state after receiving acknowledgment in case of IBCR:WSEL=0, and directly after 
transmitting one byte in case of IBCR:WSEL=1. 
5.
 Writes data to be transmitted to the TDR re gister to release the wait state of the I2C bus. 
6.
 After transmitting one byte, sets the transmit bus idle flag to 1 to put the I2C bus in the wait state 
after receiving acknowledgment in case of IBCR:WSEL=0, and directly after transmitting one 
byte in case of IBCR:WSEL=1. Repeats steps 6 to 7 until all the specified number of data sets have 
been transmitted. However, if NACK is recei ved after the wait state is released when 
IBCR:WSEL=1, the interrupt flag (IBCR:INT) is  set to 1 after receiving acknowledgement and 
the bus enters the wait state. 
7.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1*2 to generate the stop condition or 
iteration start condition. 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
982 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
 When transmit FIFO is enabled: 
1.
 Writes an address for Slave Address (including the  data direction bit) and transmit data to the TDR 
register.  
2.
 Writes 1 to the IBCR:MSS bit upon setting of the IBCR:WSEL bit. 
3.
 If NACK is received during transmission, sets  the interrupt flag (IBCR:INT) to 1 immediately 
after that to put the I2C bus in the wait state. If ACK responses  are received for all bytes, sets the 
transmit bus idle flag (SSR:TBI) to 1 according to the setting of IBCR:WSEL after the last byte 
is transmitted to put the I
2C bus in the wait state. 
4.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1*2 to generate the stop condition or 
iteration start condition. 
 
2.   To transmit data to a reserved address: 

 When transmit FIFO is disabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit.  
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes transmit data to the TDR register. 
5.
 Writes 0 to the interrupt flag (IBCR:INT) upon updating of the IBCR:WSEL bit and releases the 
wait state of the I2C bus. 
6.
 After transmitting one byte, the interrupt flag is set to 1, which puts the I2C bus in the wait state 
after receiving acknowledgment in case of IBCR:WSEL=0, and directly after transmitting one 
byte in case IBCR:WSEL=1. 
7.
 Writes data to be transmitted to the TDR re gister to release the wait state of the I2C bus. 
8.
 After transmitting one byte, sets the transmit bus idle flag to 1 to put the I2C bus in the wait state 
after receiving acknowledgment in case of IBCR:WSEL=0, and directly after transmitting one 
byte in case of IBCR:WSEL=1. Repeats steps 7 to 8 until all the specified number of data sets have 
been transmitted. However, if NACK is recei ved after the wait state is released when 
IBCR:WSEL=1, the interrupt flag (IBCR:INT) is  set to 1 after receiving acknowledgement and 
the bus enters the wait state. 
9.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1*2 to generate the stop condition or 
iteration start condition. 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
983 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
 When transmit FIFO is enabled: 
1.
 Sets the reserved address for Sl ave Address in the TDR register and writes 1 to the IBCR:MSS 
bit.  
2.
 After the Slave Address setting is transmitted, th e interrupt flag (IBCR:INT) is set to 1. 
3.
 Reads from the RDR register and c onfirms the reserved address.(*1) 
4.
 Writes all transmit data to the TDR register (un til transmit FIFO becomes full if it is the case). 
5.
 If NACK is received during transmission, sets  the interrupt flag (IBCR:INT) to 1 immediately 
after that to put the I2C bus in the wait state. If ACK responses  are received for all bytes, sets the 
interrupt flag (IBCR:INT) to 1 according to  the setting of IBCR:WSEL after the last byte is 
transmitted, which puts the I
2C bus in the wait state. 
6.
 Sets the IBCR:MSS bit to 0 or sets the IBCR:SCC bit to 1*2 to generate the stop condition or 
iteration start condition. 
  *1 :  When any one of the following conditions is met, the IBCR:ACKE and IBCR:WSEL bits must  be set to 1 and to check which is needed for the next data, operation as a master or operation 
as a slave. 

 Multi-master mode is activated and the reserved address is a general call. 

 Arbitration lost has been detected and the interface may operate as a slave. 
 
*2 :  When DMA is enabled (SSR:DMA=1), the SSR :TBI bit is 1 and the IBCR:INT bit is 0, 
follow the steps below to issue the iteration start condition. 
1.
 Set the IBCR:INT bit to 1. 
2.
 Check that the IBCR:INT bit is set to 1. 
3.
 Write the slave address in the TDR. 
4.
 Set the IBCR:SCC bit to 1. 
 
 

 When seven-bit slave address detection is enabled (ISBA:SAEN=1), it is prohibited to specify a 
seven-bit slave address in master mode. 

 To change the IBCR register during transmission/reception, do so when the interrupt flag (IBCR:INT) is 
1. 

 If the IBCR:WSEL bit is changed, the update is used as a condition for generating the transmit bus idle 
flag (SSR:TBI) when the interrupt flag (IBCR:INT) is enabled and DMA mode is also enabled 
(SSR:DMA=1) for the next data.   

 The master operates as follows when transmit data are written to the TDR register during data 
transmission with SSR:TDRE set to 1 and an ACK response is detected. 

 When DMA mode is disabled (SSR:DMA=0), the in terrupt flag (IBCR:INT) does not attain 1, and 
the written data are transmitted. 

 When DMA mode is enabled (SSR:DMA=1), the transm it bus idle flag (SSR:TBI) does not attain 1, 
and the written data are transmitted. 

 The master operates as follows when transmit data ar e written to the TDR register during data reception 
with SSR:TDRE set to 1 and an ACK response is detected. 

 When DMA mode is disabled (SSR:DMA=0), the in terrupt flag (IBCR:INT) does not attain 1 and 
only SSR:RDRF attains 1 (when receive FIFO is enabled, and the number of bytes set in the 
FBYTE register have been received). 

 When DMA mode is enabled (SSR:DMA=1), the transmit bus idle flag (SSR:TBI) does not attain 1  and only SSR:RDRF attains 1 (whe n receive FIFO is enabled, and the number of bytes set in the 
FBYTE register have been received). 
 
CHAPTER  19-5: I2C Interface  \050I2C Communications  Control Interface\051 
MN706-00002-1v0-E 
984 
MB9Axxx/MB9Bxxx  Series