Fujitsu Series 3 Manual
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4. Registers
[bit 5] HWDG: Hardware watchdog reset flag Indicates a reset from the hardware watchdog timer.
If the timer underflows, a reset is issu ed and HWDT is enabled (HWDT = 1).
bit Description
0 A hardware watchdog reset has not been issued.
1 A hardware watchdog reset has been issued.
[bit 4] SWDG: Software watchdog reset flag Indicates a reset from the software watchdog timer.
If the timer overflows, a reset is issu ed and SWDT is enabled (SWDT = 1).
bit Description
0 A software...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-115.png "Page 116
4. Registers
[bit 5] HWDG: Hardware watchdog reset flag Indicates a reset from the hardware watchdog timer.
If the timer underflows, a reset is issu ed and HWDT is enabled (HWDT = 1).
bit Description
0 A hardware watchdog reset has not been issued.
1 A hardware watchdog reset has been issued.
[bit 4] SWDG: Software watchdog reset flag Indicates a reset from the software watchdog timer.
If the timer overflows, a reset is issu ed and SWDT is enabled (SWDT = 1).
bit Description
0 A software...")
2. Configuration 2. Configuration This section shows the block diagram of the Low-voltage Detection Circuit. Block diagram of Low-vo ltage Detection Circuit Low-voltage Detection Voltage Control Register This register controls whether to enable monitoring the power supply voltage for a low-voltage detection interrupt and specifies the detection volta ge for a low-voltage detection interrupt. Low-voltage Detection Voltage Protection Register This register write-protects the Low-voltage Detection Voltage Control Register. Low-voltage Detection Interrupt Register This register holds a low-voltage detection interrupt cause. Low-voltage Detection Interrupt Clear Register This register clears a low-voltage detection interrupt cause. Low-voltage Detection Ci rcuit Status Register This register checks the operation status of a low-voltage detection interrupt circuit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 85 MB9Axxx/MB9Bxxx Series
2. Configuration Pins of Low-voltage Detection Circuit The following shows the pins used in the Low-voltage Detection Circuit. VCC pin The Low-voltage Detection Circuit monitors the power supply voltage of this pin. VSS pin This pin is a GND pin used as a basis to detect the power supply voltage. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 86 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3. Explanation of Operations This section explains the operations of the Low-Voltage Detection Reset Circuit and the Low-voltage Detection Interrupt Circuit. Operations of Low-Voltage Detection Reset Circuit Operations The Low-Voltage Detection Reset Circuit always enters a monitoring state after power-on. This circuit generates a reset signal when the power supply voltage (VCC) falls below the detection voltage. A reset is released when the power supply voltage exceeds the release voltage. This circuit is available in standby modes: SLEEP, TIMER, and STOP modes. Detection or release voltage Power supply voltage (VCC)Lower limit voltage A : Low-voltage detection reset detection delay time B : Low-voltage Detection Circuit stabilization wait time Low-voltage detection reset enable signal (LVDRE) Operation state of the Low-voltage Detection CircuitPower-on Monitoring Reset Reset Monitoring AALow-voltage Detection Circuit reset signal (L active) A FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 87 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations Operations of Low-voltage Detection Interrupt Circuit Operations The Low-voltage Detection Interrupt Circuit monitors the power supply voltage (VCC) and generates an interrupt signal when the power supply voltage falls below the specified value. An interrupt request is enabled when 1 is set to the LVDIE bit of the Low-voltage Detection Voltage Control Register. The initial value is set to Not Enable (0). The interrupt detection voltage can be set by the SVHI bit of the Low-voltage Det ection Voltage Control Register. When an interrupt request is enabled and the interrupt detection voltage is specified, the status flag LVDIRDY bit is set to 1 and this circuit starts monitoring the power supply voltage after th e stabilization wait time of the Low-voltage Detection Circuit has lapsed. This circuit is available in standby modes: SLEEP, TIME R, and STOP modes. It is also applicable when the CPU returns from standby mode. Low-voltage detection interrupt request When the power supply voltage (VCC) falls below th e specified voltage while a low-voltage detection interrupt is effective, 1 is set to the LVDIR bit of the Low-voltage Detection Interrupt Register to generate an interrupt request signal. An interrupt request can be checked by reading the LVDIR bit. Canceling a low-voltage detection interrupt request To cancel a low-voltage detection interrupt request, write 0 to the LVDCL bit of the Low-voltage Detection Interrupt Clear Register. This clears a low-voltage detection interrupt cause and cancels a low-voltage detection interrupt request. Even when the power supply voltage is below the specified detection voltage, an interrupt request is canceled when 0 is written to the Low-vo ltage Detection Interrupt Clear Register. Detection or release voltage Power supply voltage (VCC) Lower limit voltage A : Low-voltage detection interrupt detection delay time B : Low Voltage Detection Circuit stabilization wait time Low-voltage detection interrupt enable signal (LVDIE) Operation state of the Low-voltage Detection CircuitPower-on Monitoring stopStabilization wait (Monitoring stopped) Monitoring B ALow-voltage detection interrupt request signal Detection voltage setting (SVHI)Specified voltage 1 Specified voltage 2 Monitoring stopStabilization wait (Monitoring stopped) B Write 0 to the LVDCL bit. Low-voltage detection interrupt status flag (LVDIRDY) FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 88 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations This circuit does not conduct monitoring the power supply vol tage if PCLK2 is gated by TIMER mode, STOP mode, or PBC2_PSR Register while waiting for the stabilization of the Low-voltage Detection Circuit. After checking that the status flag LVDIRDY is set to 1, change to the desired mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 89 MB9Axxx/MB9Bxxx Series
4. Setup Procedure Examples 4. Setup Procedure Examples This section explains the procedures to set up the Low-voltage Detection Circuit, giving examples. Figure 4-1 Low-voltage detection interrupt setting FUJITSU SEMICONDUCTOR LIMITED Write 0x1ACCE553 to the LVD_RLR Register. Sta r t Clearing a low-voltage detection interrupt cause. Release write protection mode of the LVD_CTL Register. Set the detection interrupt voltage to the LVD_CTL Register, and also set the operation state to Enable. Set the LVD_CTL Register to write protection mode. Write 0x00000000 to the LVD_RLR Register. (Write other than 0x1ACCE553.) No LVDIRDY=1 ? Ye s End CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 90 MB9Axxx/MB9Bxxx Series
5. Registers 5. Registers This section explains the configuration and functions of the registers used in the Low-voltage Detection Circuit. List of Low-voltage Det ection Circuit Registers Abbreviation Register name See LVD_CTL Low-voltage Detection Voltage Control Register 5.1 LVD_STR Low-voltage Detection Interrupt Register 5.2 LVD_CLR Low-voltage Detection Interrupt Clear Register 5.3 LVD_RLR Low-voltage Detection Voltage Protection Register 5.4 LVD_STR2 Low-voltage Detection Circuit Status Register 5.5 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 91 MB9Axxx/MB9Bxxx Series
5. Registers 5.1. Low-voltage Detection Voltage Control Register (LVD_CTL) The Low-voltage Detection Voltage Control Register (LVD_CTL) controls whether to enable monitoring the power supply voltage for a low-voltage detection interrupt and specifies the detection voltage for a low-voltage detection interrupt. Bit 7 6 5 4 3 2 1 0 Field LVDIE Reserved SVHI Reserved Attribute R/W - R/W R/W R/W R/W - - Initial value 0 1 0 0 0 0 0 0 [bit 7] LVDIE: Low-voltage detection interrupt enable bit This bit is used to enable monitoring the power supply voltage of a low-voltage detection interrupt. When not enabling monitoring the power supply voltage, the Low-voltage Detection Interrupt Circuit is stopped. Bit Description 0 Does not enable the generation of a low-voltage detection interrupt. [Initial value] 1 Enables the generation of a low-voltage detection interrupt. [bit 6] Reserved: Reserved bit Read value has no meaning. Set 1 to this bit. [bit 5:2] SVHI: Low-voltage detection interrupt voltage setting bit This bit is used to specify the detection voltage of a low-voltage detection interrupt. bit5:2 Description 0000 Set the low-voltage detection interrupt voltage in the vicinity of 2.8V. [Initial value] 0001 Set the low-voltage detection interrupt voltage in the vicinity of 3.0V. 0010 Set the low-voltage detection interrupt voltage in the vicinity of 3.2V. 0011 Set the low-voltage detection interrupt voltage in the vicinity of 3.6V. 0100 Set the low-voltage detection interrupt voltage in the vicinity of 3.7V. 0101 Setting disabled 0110 Setting disabled 0111 Set the low-voltage detection interrupt voltage in the vicinity of 4.0V. 1000 Set the low-voltage detection interrupt voltage in the vicinity of 4.1V. 1001 Set the low-voltage detection interrupt voltage in the vicinity of 4.2V. Others Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 92 MB9Axxx/MB9Bxxx Series
5. Registers [bit 1:0] Reserved: Reserved bits 0 is always set in read mode. This bit has no effect in write mode. The l o w-voltage detection interrupt enable bit (LVD IE) must be en abled after 0 was written to the LVDCL bit of the Low-voltage Detection Interrupt Clear Register (LVD_CLR) to clear the interrupt request. When the low-voltage detection interrupt enable bit (LVDIE) is not enabled, the Low-voltage Detection Circuit for detecting a low-voltage interrupt is stopped. Therefore, the low-voltage detection interrupt flag is not set. The Low-voltage Detection Voltage Control Register (LVD_CTL) is write-protected in the initial state, which makes writing invalid unless write protection mode is released. To write the LVD_CTL Register, set 0x1ACCE553 to the Low-voltage Detection Voltage Protection Register (LVD_RLR) to release write protection mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 93 MB9Axxx/MB9Bxxx Series
5. Registers 5.2. Low-voltage Detection Interrupt Register (LVD_STR) The Low-voltage Detection Interrupt Register (LVD_STR) holds a low-voltage detection interrupt cause. Bit 7 6 5 4 3 2 1 0 Field LVDIR Reserved Attribute R - - - - - - - Initial value 0 0 0 0 0 0 0 0 [bit 7] LVDIR: Low-voltage detection interrupt bit Bit Description 0 A low-voltage detection interrupt request is not detected. [Initial value] 1 A low-voltage detection interrupt request has been detected. [bit 6:0] Reserved: Reserved bits 0 is always set in read mode. This bit has no effect in write mode. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 4: Low-voltage Detection MN706-00002-1v0-E 94 MB9Axxx/MB9Bxxx Series