Fujitsu Series 3 Manual
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9. Descriptions of base timer functions
[bit 11] RTGEN: Restart enable bit This bit enables restart by a software trigger or trigger input.
Bit Description
0 Restart disabled
1 Restart enabled
[bit 10] PMSK: Pulse output mask bit This bit controls the output level of PWM output waveforms.
When this bit is set to 0, PWM waveforms are output as they are.
When this bit is set to 1, the PWM output is masked with LOW output regardless of the cycle and duty
set values.
When...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-472.png "Page 473
9. Descriptions of base timer functions
[bit 11] RTGEN: Restart enable bit This bit enables restart by a software trigger or trigger input.
Bit Description
0 Restart disabled
1 Restart enabled
[bit 10] PMSK: Pulse output mask bit This bit controls the output level of PWM output waveforms.
When this bit is set to 0, PWM waveforms are output as they are.
When this bit is set to 1, the PWM output is masked with LOW output regardless of the cycle and duty
set values.
When...")
![Page 474
9. Descriptions of base timer functions
Timer Control Register (L ow-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field res FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit 6:4] FMD2 to FMD0: Timer function selection bits These bits select the timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b001, the PWM function is selected.
...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-473.png "Page 474
9. Descriptions of base timer functions
Timer Control Register (L ow-order bytes of TMCR)
bit 7 6 5 4 3 2 1 0
Field res FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 0 0 0 0 0 0
[bit 7] res: Reserved bit The read value is 0.
Set 0 to this bit.
[bit 6:4] FMD2 to FMD0: Timer function selection bits These bits select the timer function.
When the FMD2, FMD1, and FMD0 bits are set to 0b001, the PWM function is selected.
...")
![Page 475
9. Descriptions of base timer functions
[bit 2] MDSE: Mode selection bit This bit selects continuous pulse output or one-shot pulse output.
Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make
changes at the same time you set 1 to the CTEN bit.
Bit Description
0 Continuous operation
1 One-shot operation
[bit 1] CTEN: Count operation enable bit This bit enables the operation of the down counter.
When the counter is in operation en abled...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-474.png "Page 475
9. Descriptions of base timer functions
[bit 2] MDSE: Mode selection bit This bit selects continuous pulse output or one-shot pulse output.
Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make
changes at the same time you set 1 to the CTEN bit.
Bit Description
0 Continuous operation
1 One-shot operation
[bit 1] CTEN: Count operation enable bit This bit enables the operation of the down counter.
When the counter is in operation en abled...")
![Page 476
9. Descriptions of base timer functions
Timer Control Register 2 (TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.1.6 Timer Control Register (TMCR).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2: Base Timer
MN706-00002-1v0-E
440...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-475.png "Page 476
9. Descriptions of base timer functions
Timer Control Register 2 (TMCR2)
bit 15 14 13 12 11 10 9 8
Field res CKS3
Attribute R/W R/W
Initial value 0b0000000 0
Note: This register is placed above the STC register.
[bit 15:9] res: Reserved bits The read value is 0.
Set 0 to this bit.
[bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.1.6 Timer Control Register (TMCR).
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 14-2: Base Timer
MN706-00002-1v0-E
440...")
9. Descriptions of base timer functions 9.1.5. PWM timer operation flowchart This section provides an operation flowchart of the PWM timer. PWM timer operation flowchart PWM mode selection Count clock selection Operation mode selection Interrupt flag clear Interrupt enableSettings Start by the CTEN bit One-shot operation Continuous operation Trigger detection TGIR flag setting Start of decrement Occurrence of an underflow UDIR flag setting MDSE=0 ? No Match in duty DTIR flag setting Yes Stop of count operation Stop of operation FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 435 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.6. Timer Control Registers (TMCR and TMCR2) and Status Control Register (STC) used when the PWM timer is selected The Timer Control Register (TMCR) controls the PWM timer. Note that some bits cannot be rewritten while the PWM timer is in operation. Timer Control Register (H igh-order bytes of TMCR) bit 15 14 13 12 11 10 9 8 Field res CKS2 CKS1 CKS0 RTGENPMSK EGS1 EGS0 Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 15] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 14:12, TMCR2: bit 8] CKS3 to CKS0: Count clock selection bit Select the count clock for the 16-bit down counter. Changes to the count clock setting are applied immediately. For this reason, changes to CKS3 through CKS0 must be made when the counting is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. CKS3 CKS2 CKS1 CKS0 Description 0 0 0 0 0 0 0 1 /4 0 0 1 0 /16 0 0 1 1 /128 0 1 0 0 /256 0 1 0 1 External clock (rising edge event) 0 1 1 0 External clock (falling edge event) 0 1 1 1 External clock (both edge event) 1 0 0 0 /512 1 0 0 1 /1024 1 0 1 0 /2048 Others Setting disabled FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 436 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 11] RTGEN: Restart enable bit This bit enables restart by a software trigger or trigger input. Bit Description 0 Restart disabled 1 Restart enabled [bit 10] PMSK: Pulse output mask bit This bit controls the output level of PWM output waveforms. When this bit is set to 0, PWM waveforms are output as they are. When this bit is set to 1, the PWM output is masked with LOW output regardless of the cycle and duty set values. When OSEL in bit 3 is set to inverted output, setting PMSK to 1 masks the output with HIGH. Bit Description 0 Normal output 1 Fixed to LOW output [bit 9:8] EGS1, EGS0: Trigger input edge selection bits These bits select a valid edge for input waveforms as an external start cause and set the trigger condition. When the initial value or 0b00 is set, the timer is not started by external waveforms because the setting means that no valid edge is selected for input waveforms. If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings. Changes to EGS1 or EGS0 must be made when the counting is stopped (CTEN = 0). However, it is possibl e to make changes at the same time you set 1 to the CTEN bit. Bit 9 Bit 8 Description 0 0 Trigger input disabled 0 1 Rising edge 1 0 Falling edge 1 1 Both edges FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 437 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register (L ow-order bytes of TMCR) bit 7 6 5 4 3 2 1 0 Field res FMD2 FMD1 FMD0 OSEL MDSE CTEN STRG Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 [bit 7] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 6:4] FMD2 to FMD0: Timer function selection bits These bits select the timer function. When the FMD2, FMD1, and FMD0 bits are set to 0b001, the PWM function is selected. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit 6 Bit 5Bit 4 Description 0 0 0 Reset mode 0 0 1 Selection of the PWM function 0 1 0 Selection of the PPG function 0 1 1 Selection of the reload timer function 1 0 0 Selection of the PWC function 1 0 1 1 1 0 1 1 1 Setting disabled [bit 3] OSEL: Output polarity specification bit This bit sets the polarity of the PWM output. Polarity After reset Match in duty Underflow Normal LOW output Inverted HIGH output Bit Description 0 Normal polarity 1 Inverted polarity FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 438 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 2] MDSE: Mode selection bit This bit selects continuous pulse output or one-shot pulse output. Changes must be made while the timer is stopped (CTEN = 0). However, it is possible to make changes at the same time you set 1 to the CTEN bit. Bit Description 0 Continuous operation 1 One-shot operation [bit 1] CTEN: Count operation enable bit This bit enables the operation of the down counter. When the counter is in operation en abled status (the CTEN bit is 1), writing 0 to this bit stops the counter. Bit Description 0 Stop 1 Operation enabled [bit 0] STRG: Software trigger bit When the CTEN bit is 1, writing 1 to the STRG bit enables software triggering. The read value of the STRG bit is always 0. Soft ware triggering is also enabled when 1 is written to the CTEN and STRG bits simultaneously. If the STRG bit is set to 1, software triggering is enabled regardless of the EGS1 and EGS0 settings. Bit Description 0 Invalid 1 Start triggered by software FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 439 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Timer Control Register 2 (TMCR2) bit 15 14 13 12 11 10 9 8 Field res CKS3 Attribute R/W R/W Initial value 0b0000000 0 Note: This register is placed above the STC register. [bit 15:9] res: Reserved bits The read value is 0. Set 0 to this bit. [bit 8] CKS3: Count clock selection bit See Count clock selection bit in 9.1.6 Timer Control Register (TMCR). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 440 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions Status Control Register (STC) bit 7 6 5 4 3 2 1 0 Field res TGIE DTIE UDIE res TGIR DTIR UDIR Attribute R/W R/W R/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 Note: The TMCR2 register is placed in the upper bytes of this register. [bit 7] res: Reserved bit The read value is 0. Set 0 to this bit. [bit 6] TGIE: Trigger interrupt request enable bit This bit controls interrupt requests of bit 2 TGIR. When the TGIE bit is enabled, setting bit 2 TGIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 5] DTIE: Duty match interrupt request enable bit This bit controls interrupt requests of bit 1 DTIR. When the DTIE bit is enabled, setting bit 1 DTIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 4] UDIE: Underflow interrupt request enable bit This bit controls interrupt requests of bit 0 UDIR. When the UDIE bit is enabled, setting bit 0 UDIR generates an interrupt request to the CPU. Bit Description 0 Disables interrupt requests. 1 Enables interrupt requests. [bit 3] res: Reserved bit The read value is 0. Set 0 to this bit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 441 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions [bit 2] TGIR: Trigger interrupt request bit When a software trigger or trigger input is detected, the TGIR bit is set to 1. The TGIR bit is cleared by writing 0. Even if 1 is written to the TGIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. [bit 1] DTIR: Duty match interrupt request bit When the count value matches the duty set value, the DTIR bit is set to 1. The DTIR bit is cleared by writing 0. Even if 1 is written to the DTIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. [bit 0] UDIR: Underflow interrupt request bit When a count value underflow from 0x0000 to 0xFFFF occurs, the UDIR bit is set to 1. The UDIR bit is cleared by writing 0. Even if 1 is written to the UDIR bit, the bit value is not affected. The read value of read-modify-write instructions is 1 regardless of the bit value. Bit Description 0 Clears an interrupt cause. 1 Detects an interrupt cause. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 442 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.7. PWM Cycle Set Register (PCSR) The PWM Cycle Set Register (PCSR) is a buffered register for setting the cycle. Transfer to the Timer Register is performed at startup and underflow. bit 15 0 Field PCSR [15:0] Attribute R/W Initial value 0xXXXX This is a buffered register for setti ng the cycle. Transfer to the Timer Re gister is performed at startup and underflow. When initializing or rewriting the PWM Cycle Set Regist er, be sure to perform writing to the PWM Duty Set Register after performing writing to the PWM Cycle Set Register. Access the PCSR register with 16-bit data. Set the cycle for the PCSR register after setti ng the PWM function using the FMD2, FMD1, and FMD0 bits in the TMCR register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 443 MB9Axxx/MB9Bxxx Series
9. Descriptions of base timer functions 9.1.8. PWM Duty Set Register (PDUT) The PWM Duty Set Register (PDUT) is a buffered register for setting the duty. Transfer from the buffer is performed at an underflow. bit 15 0 Field PDUT [15:0] Attribute R/W Initial value 0xXXXX This is a buffered register for setting the duty. Transfer from the buffer is performed at an underflow. When the cycle set register value is set equal to the du ty set register value, an all-HIGH pulse is output under normal polarity and an all-LOW pulse is output under inverted polarity. Do not set a value that makes BTPSCR < PDUT. The PWM output becomes undefined. Access the PDUT register with 16-bit data. Set the duty for the PDUT register after setting the PWM function using the FMD2, FMD1, and FMD0 bits in the TMCR register. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 14-2: Base Timer MN706-00002-1v0-E 444 MB9Axxx/MB9Bxxx Series