Fujitsu Series 3 Manual
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3. Operations of USB Function 3.8. STALL response/release of endpoint 0 The STAL bit in the EP0 Control Register (EP0C) controls the STALL response and release of Endpoint 0. STAL bit set timing To perform the STALL response, interpret the command at the setup stage (SETP bit = 1 detection) of control transfer. If the STALL response is required, set the STAL bit. (See Figure 3-18) After setting the STAL bit, clear th e in terrupt cause (DRQO bit). Figure 3-18 STAL bit set timing Token packetData packetHandshake packet Setup stage Token packetData packetHandshake packet Data stage DRQO bit SETP bit Idle period STAL bit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1095 MB9Axxx/MB9Bxxx Series
3. Operations of USB Function STAL bit clear timing Upon the detection of SETP bit = 1, pointing to the setup stage of control transfer, the STAL bit is automatically cleared and the STALL state is released. (See Figure 3-19) Figure 3-19 STAL bit clear timing Token packetData packetHandshake packet Setup stage Token packetData packetHandshake packet Data stage DRQO bit SETP bit Idle period STAL bit Upon th e d etection of SETP bit = 1 (DRQO bit = 1 interru pt), the STAL bit is cleared to 0. To enable the STALL response again, set the STAL bit to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1096 MB9Axxx/MB9Bxxx Series
3. Operations of USB Function 3.9. Stall response/release of endpoints 1 to 5 The STAL bit and the internal status bit in the EP1 to 5 Control Registers (EP1C to EP5C) controls the STALL response and release of Endpoints 1 to 5. Stall response processed by software Figure 3-20 and Figure 3-21 shows the procedure to process the STALL response by software. To perform the STALL respon se, configure the STAL bit of relevant Endpoint by software. The internal status bit does not change then. When a transaction occurs from the host to the Endpoint to which the STAL bit is set, the hardware automatically sets the internal status bit of the relevant Endpoint to perform the STALL response to the host. Once the internal status bit is set, it remains set even when the STAL bit cleared. As the internal state bit remains set until the host issues the Clear Feature command, the STALL response remains running. While the STALCLREN bit of the UDC Control Register (UDCC) is set to 0, the STALL response also remains running in the following condition: The STAL bit remains set even after the internal st atus bit is cleared by the Clear Feature command. This is because the internal status bit is set each time a transaction occurs to the relevant Endpoint. To release the STALL response, therefore, the STAL bit mu st be cleared, and the internal status bit must be cleared by the Clear Feature command.If the STALCLREN bit in the UDC Control Register (UDCC) is set to 1, the STAL bit is cleared at the same time th e internal status bit is cleared by the Clear Feature command, and the STALL response is not performed for the next transaction. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1097 MB9Axxx/MB9Bxxx Series
3. Operations of USB Function Figure 3-20 To process the STALL response by software (the STAL bit is cleared by software) UDCC.STALCLREN=0 Host or hub Internal status bitSTAL bit 0 Function macro EPn (Endpoint n) Software Set the STAL bit to 1 0 IN/OUT token Function 10 11 Stall handshake Data (for OUT) IN/OUT token Stall handshake Data (for OUT) Clear the STAL bit to 0 01 When a transaction occurs while the STAL bit is 1, the internal status bit is set to 1. When the internal status bit is 1, the STALL response to the transaction continues. IN/OUT token Stall handshake Data (for OUT) When the internal status bit is 1, the STALL response to the transaction continues. Even if the STAL bit is 0, it does not affect the internal status bit. The Clear Feature command to EP0 (Specify EPn) Setup token 00 Data ACK handshake If EPn is specified by the Clear Feature command, The internal status bit is cleared to 0. Transaction to EPn Internal status bit STAL bit Internal status bit STAL bit Internal status bit STAL bit Internal status bit STAL bit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1098 MB9Axxx/MB9Bxxx Series
3. Operations of USB Function Figure 3-21 To process the STALL response by software (the STAL bit is cleared by hardware) UDCC.STALCLREN=1 Host or hub Internal status bitSTAL bit 0 Function macro EPn (Endpoint n) Software Set the STAL bit to 1 0 IN/OUT token Function 10 11 Stall handshake Data (for OUT) IN/OUT token Stall handshake Data (for OUT) 11 When a transaction occurs while the STAL bit is 1, the internal status bit is set to 1. When the internal status bit is 1, the STALL response to the transaction continues.IN/OUT token Stall handshake Data (for OUT) When the internal status bit is 1, the STALL response to the transaction continues. The Clear Feature command to EP0 (Specify EPn) Setup token 00 Data ACK handshake If EPn is specified by the Clear Feature command, the internal status bit and the STAL bit are cleared to 0. Transaction to EPn Internal status bit STAL bit Internal status bit STAL bit Internal status bit STAL bit Internal status bit STAL bit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1099 MB9Axxx/MB9Bxxx Series
3. Operations of USB Function Automatic STALL response by hardware Figure 3-22 shows the procedure for the automatic STALL response by hardware. When the STALL response is set by the Set Feature command, the hardware automatically set the internal status bit of the relevant Endpoint, irrespective of the STAL bit setting, and perform the STALL response.Once the internal bit is set, the value is retained until cleared by the Clear Feature command from the host irrespective of the STAL bit setting. The STAL bit is referred to even after the internal status bit is cleared by the Clear Feature command.To release the STALL response, therefore, the internal status bit must be cleared by the Clear Feature command. Figure 3-22 Automatic Stall Response by Hardware Host or hub Internal status bitSTAL bit 0 Function macro EPn (Endpoint n) Software 0 Function Setup token ACK handshake Data (for OUT) 01 IN/OUT token Stall handshake Data (for OUT) When the internal status bit is 1, the STALL response to the transaction continues. Even if the STAL bit is 0, it does not affect the internal status bit. Clear Feature command for EPn (Specify EPn) Setup token00 Data ACK handshake If EPn is specified by the Clear Feature command, the internal status bit is cleared to 0. Transaction to EPn Set Feature command for EPn (Specify EPn) If EPn is specified by the Set Feature command, the internal status bit is set to 1. Internal status bit STAL bit Internal status bit STAL bit FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1100 MB9Axxx/MB9Bxxx Series
4. Examples of USB Function Setting Procedures 4. Examples of USB Function Setting Procedures This section provides flowcharts for initialization, bus reset, CPU transfer, packet transfer (IN/OUT) and automatic data size transfer (IN/OUT). Initialization Start USBSet clock USBEN.USBEN=1 UDCC.RST=1 D+Set pull-up disconnection End Set EP0C Set EP1C to EP5C UDCC.RST=0 EP0IS,EP0OS,EP1S to EP5S BFINI=0 UDCC.HCONX=0 D+Set pull-up connection Set UDCC.PWC VBUS detected?NO YES // Buffer clear // Endpoint setting // Endpoint setting // Ext. interrupt detect // Device connection FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1101 MB9Axxx/MB9Bxxx Series
4. Examples of USB Function Setting Procedures Bus reset USB interrupt End UDCS.BRST=1? EP0IS,EP0OS,EP1S to EP5S BFINI=1 NOUDCS.BRST=0 // Buffer clear YES EP0IS,EP0OS,EP1S to EP5S BFINI=0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1102 MB9Axxx/MB9Bxxx Series
4. Examples of USB Function Setting Procedures Example control for CPU transfer Start USB interrupt Check source Write data to FIFO Read out data to FIFO - USB data request bit (DRQ: bit 10 of the Epx Status Register (EPxS)) = 0Clear USB interrupt flag - Dummy read of the releva nt USB interrupt control registerDummy read End interrupt OUT direction IN direction FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1103 MB9Axxx/MB9Bxxx Series
4. Examples of USB Function Setting Procedures Example control for packet transfer in IN direction [Initial settings] [DMA transfer end interrupt] Set interrupt level (Resume the correlation between the USB interrupt level and the DMAC interrupt level used by packet transfer to that before the interrupt.)Set the next DMA transfer YES NO Start the next DMA transfer? Disable USB interrupts to relevant Endpoint Clear DMA transfer end interrupt Clear USB interrupt flag + Dummy read - USB data request bit (DRQ: bit 10 of the Epx Status Register (EPxS)) = 0 - Dummy read of the relevant USB interrupt control register End interrupt - EP Control Register (EPxC) setting Start DMA transfer end interrupt Initial settings Notes: Set USB interrupt level to the lowest - DRQIE:bit 14 of the EP Status Register (EPxS) = 1 Set DMAC Set USB Endpoints Set interrupt level (Set USB interrupt level to the lowest) Enable USB interrupts End initial settings FUJITSU SEMICONDUCTOR LIMITED CHAPTER 20-2: USB Function MN706-00002-1v0-E 1104 MB9Axxx/MB9Bxxx Series