Fujitsu Series 3 Manual
Have a look at the manual Fujitsu Series 3 Manual online for free. It’s possible to download the document as PDF or print. UserManuals.tech offer 86 Fujitsu manuals and user’s guides for free. Share the user manual or guide on Facebook, Twitter or Google+.
![Page 767
5. Registers
5.12. A/D Comparison Control Register (CMPCR)
The A/D Comparison Control Register (CMPCR) controls the A/D comparison function. When
the converted value is compared with the value in the A/D Comparison Value Setup Register
(CMPD) and the comparison condition in this register is satisfied, the conversion result
comparison interrupt request bit (CMPIF) in the A/D Control Register (ADCR) is set.
bit 7 6 5 4 3 2 1 0
Field CMPENCMD1 CMD0 CCH [4:0]
Attribute R/W R/W R/W R/W R/W R/W...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-766.png "Page 767
5. Registers
5.12. A/D Comparison Control Register (CMPCR)
The A/D Comparison Control Register (CMPCR) controls the A/D comparison function. When
the converted value is compared with the value in the A/D Comparison Value Setup Register
(CMPD) and the comparison condition in this register is satisfied, the conversion result
comparison interrupt request bit (CMPIF) in the A/D Control Register (ADCR) is set.
bit 7 6 5 4 3 2 1 0
Field CMPENCMD1 CMD0 CCH [4:0]
Attribute R/W R/W R/W R/W R/W R/W...")
![Page 769
5. Registers
5.14. Sampling Time Setup Register (ADST)
Sampling Time Setup Registers 0 and 1 (ADST0 and 1) set the sampling times for A/D
conversion. ADST0 and 1 are provided for setting two sampling times, and which one is used
is selected in the Sampling Time Selection Register (ADSS3 to 0).
ADST0 (most significant byte)
bit 15 14 13 12 11 10 9 8
Field STX01 STX00 ST05 ST04 ST03 ST02 ST01 ST00
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
[bit 15:14]...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-768.png "Page 769
5. Registers
5.14. Sampling Time Setup Register (ADST)
Sampling Time Setup Registers 0 and 1 (ADST0 and 1) set the sampling times for A/D
conversion. ADST0 and 1 are provided for setting two sampling times, and which one is used
is selected in the Sampling Time Selection Register (ADSS3 to 0).
ADST0 (most significant byte)
bit 15 14 13 12 11 10 9 8
Field STX01 STX00 ST05 ST04 ST03 ST02 ST01 ST00
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
[bit 15:14]...")
![Page 770
5. Registers
ADST1 (least significant byte)
bit 7 6 5 4 3 2 1 0
Field STX11 STX10 ST15 ST14 ST13 ST12 ST11 ST10
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
[bit 7:6] STX11:STX10: Sampling time N times setting bits These bits multiply the sampling time set values in the ST15 to ST10 bits by N.
Bit 7 Bit 6 Description
0 0 Set value x 1
0 1 Set value x 4
1 0 Set value x 8
1 1 Set value x 16
[bit 5:0] ST15:ST10: Sampling time setting bits These...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-769.png "Page 770
5. Registers
ADST1 (least significant byte)
bit 7 6 5 4 3 2 1 0
Field STX11 STX10 ST15 ST14 ST13 ST12 ST11 ST10
Attribute R/W R/W R/W R/W R/W R/W R/W R/W
Initial value 0 0 1 0 0 0 0 0
[bit 7:6] STX11:STX10: Sampling time N times setting bits These bits multiply the sampling time set values in the ST15 to ST10 bits by N.
Bit 7 Bit 6 Description
0 0 Set value x 1
0 1 Set value x 4
1 0 Set value x 8
1 1 Set value x 16
[bit 5:0] ST15:ST10: Sampling time setting bits These...")
![Page 771
5. Registers
FUJITSU SEMICONDUCTOR LIMITED
Chapter: 10-bit A/D Converter
FUJITSU SEMICONDUCTOR CONFIDENTIAL 46
5.15. Comparison Time Setup Register (ADCT)
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the
A/D conversion time.
bit 15 14 13 12 11 10 9 8
Field Reserved CT2 CT1 CT0
Attribute - - - - - R/W R/W R/W
Initial value X X X X X 1 1 1
[bit 15:11] Reserved: Reserved bits
Write Has no effect on operation.
Read The value is undefined....](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-770.png "Page 771
5. Registers
FUJITSU SEMICONDUCTOR LIMITED
Chapter: 10-bit A/D Converter
FUJITSU SEMICONDUCTOR CONFIDENTIAL 46
5.15. Comparison Time Setup Register (ADCT)
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the
A/D conversion time.
bit 15 14 13 12 11 10 9 8
Field Reserved CT2 CT1 CT0
Attribute - - - - - R/W R/W R/W
Initial value X X X X X 1 1 1
[bit 15:11] Reserved: Reserved bits
Write Has no effect on operation.
Read The value is undefined....")
5. Registers
FUJITSU SEMICONDUCTOR LIMITED
Chapter: 10-bit A/D Converter
FUJITSU SEMICONDUCTOR CONFIDENTIAL 46
5.15. Comparison Time Setup Register (ADCT)
The Comparison Time Setup Register (ADCT) sets the comparison time, which is part of the
A/D conversion time.
bit 15 14 13 12 11 10 9 8
Field Reserved CT2 CT1 CT0
Attribute - - - - - R/W R/W R/W
Initial value X X X X X 1 1 1
[bit 15:11] Reserved: Reserved bits
Write Has no effect on operation.
Read The value is undefined.
[bit 10:8] CT2:CT0: Comparison time setting bits These bits set the comparison time of the A/D conversion time.
The comparison time setting is common to Sampling Setup Registers 0 and 1.
Comparison time = {(CT set value (N ) + 1) × 10 + 4} × PCLK cycle
Example: When the CT set value = 1 and PCLK = 20 MHz (50 ns), Comparison time = {(1 + 1) × 10 + 4} × 50 = 1.2 s
It is not possible to write to the ADCT register during A/D conversion.
CHAPTER 18-2: 10-bit A/D Converter
MN706-00002-1v0-E
735
MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 736 MB9Axxx/MB9Bxxx Series
1. Overview Chapter: 12-bit A/D Converter This chapter explains the functions and operations of the 12-bit A/D converter. 1. Overview 2. Configuration 3. Explanation of Operations 4. Setup procedure examples 5. Registers CODE: 9BFBAD12M3-E01.2 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 737 MB9Axxx/MB9Bxxx Series
1. Overview 1. Overview The 12-bit A/D converter is a function that converts analog input voltages into 12-bit digital values using a type of the RC Successive Approximation Register. Features of the 12-bit A/D converter 12-bit resolution Converter using a type of RC Successive Approximation Register with sample and hold circuits Conversion time of 1.0 s (at a base clock (HCLK) frequency of 72 MHz) Two sampling times selectable for each input channel Scan conversion operation: Multiple analog inputs can be selected from multiple channels. Start factors are software and timers. Repeat mode is available. Priority conversion operation: Even during scan operation, if a start factor of priority conversion o ccurs, it is possible to interrupt the ongoing scan conversion and perform conversion with high priority (There are two priority levels: 1 and 2. Priority level 1 is higher than priority level 2.). Start factors are software and timers (priority le vel 2), and external triggers (priority level 1). FIFO function: Sixteen FIFO stages for scan conver sion and four FIFO stages for priority conversion are incorporated. An interrupt is generated when data is wr itten in the specified count of FIFO stages. Changeable A/D conversion data placement (selectable between shift to the MSB side and shift to LSB side) The A/D conversion result comparison function is available. There are four interrupt sources as follows: 1. Scan conversion FIFO stage count interrupt 2. Priority conversion FIFO stage count interrupt 3. FIFO overrun interrupt (for both scan and priority conversion processes) 4. A/D conversion result comparison interrupt DMA transfer triggered by an interrupt request FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 738 MB9Axxx/MB9Bxxx Series
2. Configuration 2. Configuration This section provides the configuration of the 12-bit A/D converter. 12-bit A/D converter block diagram Figure 2-1 12-bit A/D converter block diagram Control unit A/D converter Channel & status control unit Peripheral buses Buffer Scan conversion FIFO, 16 stages Priority conversion FIFO, 4 stages D/A converter Comparator Sample & holdAnalog input n Analog input n-1 ･ ･ ･ ･ Analog input 3 Analog input 2 Analog input 1 Analog input 0 A/D conversion result comparison interrupt FIFO overrun interrupt Scan FIFO interrupt Priority FIFO interruptTimer trigger External trigger pin Ｍ Ｐ Ｘ Input impedance The sampling circuit of the A/D converter is shown as an equivalent circuit in Figure 2-2. Refer to the Electrical Characteristics in the data sheet to make su re that the external impedance Rext should be selected not to exceed the sampling time. Figure 2-2 Input impedance equivalence circuit diagram Analog signal source Rext Analog SWRin Cin ADC LSI FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 739 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3. Explanation of Operations This chapter explains the operations of the 12-bit A/D converter. 3.1 Enabling operations of the A/D converter 3.2 A/D conversion operation 3.3 FIFO operations 3.4 A/D comparison function 3.5 Starting DMA FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 740 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.1. Enabling operations of the A/D converter This section explains enabling operations of the A/D converter The A/D converter must be in the operation enable state prior to A/D conversion. Writing 1 to the ENBL bit of the ADCEN register turns the A/D converter from the operation stop state to the operation enable state after the period of operation enable state transitions. On the other hand, writing 0 to the ENBL bit of the ADCEN register turns the A/D converter imme diately to the operation stop state. A/D conversion can be performed only in the operation enable state. An A/D conversion request in the operation stop state is ignored. If the A/D converter enters the operation stop state during A/D conversion, A/D conversion stops immediately. Reading the READY bit of the ADCEN register allows you to check whether the A/D converter is in the operation enable state or not. When setting the CPU to the timer mode or the stop mode, set the ENBL bit to 0 and turn the A/D converter to the operation stop state. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 741 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2. A/D conversion operation The A/D converter can perform two types of conversion processes: scan conversion and priority conversion. 3.2.1 Scan conversion operation 3.2.2 Priority conversion operation 3.2.3 Priority levels and state transitions FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 742 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3.2.1. Scan conversion operation This section explains the scan conversion operation. The input channels are selected in the Scan Conversion Input Selection Register (SCIS). By setting the corresponding bit in the SCIS to 1, any necessary channel can be selected from among multiple analog input channels. The A/D converter can be started by software or a timer. To start the converter by software, set the SSTR bit in the SCCR register to 1. Then conversion starts. To start the converter by timers, set the SHEN bit in the SCCR register to 1 to enable timer start. Conversion starts when the timers rising edge is detected. When conversion starts, the SCS bit in the ADSR register is set to 1. When the conversion is completed, the SCS bit is reset to 0. When the SSTR bit in the SCCR register is set to 1 again during A/D conversion or the timers rising edge is detected again while timer start is enabled, the ongoing conversion operation is immediately stopped and initialized and the A/D conversion is performed again (the operation is restarted). The available scan conver sion modes are as follows: 1. One-shot mode for a single channel This mode is selected when only one analog priority conversion is specified for scan conversion and RPT = 0 in the SCCR register. When the selected priority conversion is completed, the operation stops. Figure 3-1 Stop of operation in one-shot mode for a single channel (SCIS3 = 0x00, SCIS2 = 0x00, SCIS1 = 0x00, SCIS0 = 0x08) RPT SSTR Conversion channelch3 Stop Stop 2. Continuous mode for a single channel This mode is selected when only one analog priority conversion proce ss is specified for scan conversion and RPT = 1 in the SCCR register. When the selected priority conversion is completed, the same priority conversion is st arted again. To stop A/D conversi on, set RPT to 0. The operation stops when the ongoing A/D conversion is completed. Figure 3-2 Stop of operation in continuous mode for a single channel (SCIS3 = 0x00, SCIS2 = 0x00, SCIS1 = 0x00, SCIS0 = 0x08) RPT SSTR Conversion channelch3 ch3 ch3 ch3 ch3 ch3 Stop Stop FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 743 MB9Axxx/MB9Bxxx Series
3. Explanation of Operations 3. One-shot mode for multiple channels This mode is selected when mul tiple analog channels are specified for scan conversion and RPT = 0 in the SCCR register. When the conversion starts, the existence of each channel is automatically checked. While the channels are sw itched from one to another, A/D conversion is started and the conversion result is written to FIFO when the conversion is completed. The conversion channels are selected in descending order of channel number (starting from ch.0). Channels not selected in the SCIS register are skipped and the conversion operation targets the next selected channel. When the A/D conversion of the last one of the selected channels is completed, the A/D conversion is stopped. Figure 3-3 Stop of operation in one-shot mode for multiple channels (SCIS3 = 0x00, SCIS2 = 0x01, SCIS1 = 0x01, SCIS0 = 0x11) RPT SSTR Conversion channelch0 ch4 ch8 ch16 Stop Stop 4. Continuous mode for multiple channels This mode is selected when mul tiple analog channels are specified for scan conversion and RPT = 1 in the SCCR register. When the conversion starts, the existence of each channel is automatically checked. While the channels are sw itched from one to another, A/D conversion is started and the conversion result is written to FIFO when the conversion is completed. The conversion channels are selected in descending order of channel number (starting from ch.0). Channels not selected in the SCIS register are skipped and the conversion operation targets the next selected channel. When the A/D conversion of the last one of the selected channels is completed, the conversion operation starts again from ch.0. To end A/D conversion, set RPT 0. The operation stops when the A/D conversion of the last one of the selected channels is completed. Figure 3-4 Stop of operation in continuous mode for multiple channels (SCIS3 = 0x00, SCIS2 = 0x01, SCIS1 = 0x01, SCIS0 = 0x11) RPT SSTR Conversion channelch0 ch4 ch8 ch16 ch0 ch4 ch8 ch16 Stop Stop FUJITSU SEMICONDUCTOR LIMITED CHAPTER 18-3: 12-bit A/D Converter MN706-00002-1v0-E 744 MB9Axxx/MB9Bxxx Series