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5. USB host registers 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: USB Host 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  52 
[bit 6:4] TKNEN (ToKeN ENable) 
These are token enable bits. 
These bits send a token according to the settings. Afte r operation has been ended, the TKNEN bit is set to 
000, and the CMPIRQ bit of the Host Interrupt Register  (HIRQ) is set to 1. If the CMPIRE bit of Host 
Control Register 0 (HCNT0) is 1, an interrupt occurs. 
The settings of the TGGL and ENDPT bits  are ignored when sending a SOF token. 
Table 5-3 Token setting 
Bit 6 Bit 5 Bit 4 Operation 
0  0 0 Sends no data. 
0 0  1 Sends SETUP token. 
0 1  0 Sends IN token. 
0 1  1 Sends OUT token. 
1  0 0 Sends SOF token. 
1 0  1 Sends Isochronous IN. 
1 1  0 Sends Isochronous OUT. 
1 1  1 Reserved (Setting disabled) 
 
 
 This bit is set to the initial value when 1 is set to the RST bit of the UDC Control Register (UDCC). 

 The PRE packet is not supported. 

 Do not set 100 to the TKNEN bit when the SOFBUS Y bit of the Host Status Register (HSTATE) is 
1. 

 Change the USB to the host mode before writing data to this bit. 

 When issuing a token again after the token interrupt flag (CMPIRQ) has been set to 1, wait for 3 cycles 
or more after a USB transfer clock (12 MHz in the full-speed mode, 1.5 MHz in the low-speed mode) 
was output, then write data to this bit. 

 When the device is disconnected (CSTAT of HSTATE = 0), token sending is not performed even if data 
is written to this bit. 
 
[bit 3:0] ENDPT (ENDPoinT) 
These are endpoint bits. 
These bits are used to specify an endpoint to  send or receive data to or from the device. 
 
 
This bit is initialized when 1 is set to the RST bit of the UDC Control Register (UDCC). 
 
CHAPTER  20-3: USB Host 
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1. Overview and configuration 
 
Chapter: CAN Prescaler 
This chapter describes the CAN prescaler. 
 
1. Overview and configuration 
2. CAN Prescaler Register 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 CODE: 9BFCANPRE-E01.2 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-1: CAN Prescaler 
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1. Overview and configuration 
 
1.  Overview and configuration 
The CAN prescaler generates a CAN system clock (fsys) and supplies it to the CAN. 
The CAN prescaler divides a CAN prescaler clock by 1 to 12 frequency, and supplies it to the CAN as a 
CAN system clock (fsys). 
Figure 1-1  shows the block diagram of the CAN prescaler. 
 CAN block diagram 
Figure 1-1 Generating a CAN system clock (fsys) 
PLL oscillation enable (SCM_CTL.PLLE)
Standby
STOP mode
TIMER mode
Sub clock mode
Low-speed CR mode
PLL output
1
Base clock (HCLK)0CAN prescaler clock CAN system clock
CAN prescaler 
(set in CANPRE[3:0])/ (1 - 12) CAN
Controller
 
  Explanation of Operations 
The CAN prescaler selects the follo wing as a CAN prescaler clock, and supplies it to the CAN after 
dividing cycles. 
   For PLL: PLL output 
   For others (including Standby in  Figure 1-1): Base clock (HCLK) 
 
FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER  21-1: CAN Prescaler 
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2. CAN Prescaler Register 
 
2.  CAN Prescaler Register 
This chapter describes the CAN Prescaler Register. 
Abbreviation Register name See 
CANPRE CAN Prescaler Register  2.1 
 
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CHAPTER  21-1: CAN Prescaler 
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2. CAN Prescaler Register 
 
2.1.  CAN Prescaler Register (CANPRE) 
The CAN Prescaler Register is used to configure the CAN system clock (fsys) generation 
prescaler. 
 Register configuration 
bit  7 6 5  4 3 2 1 0 
Field Reserved Reserved  CANPRE 
Attribute R/W0 - -  - R/W R/W  R/W R/W 
Initial value 0 0 0  0 1 0 1 1 
 
  Register functions 
[Bit7] Reserved bit 
Be sure to write 0. 
[Bit6:4] Reserved bits  Logical 0 is always read. In the write mode, set 0. 
[Bit3:0] CANPRE:    CAN prescaler setting bits 
CAN system clock frequency 
Bit 3:0  Function  At input of   
80 MHz 
prescaler clock  At input of   
60 MHz 
prescaler clock
0000  The 1/1 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock. 
(Initial value: CANPRE[3:0]=0000)  80 MHz 60 MHz 
0001 
The 1/2 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  40 MHz 30 MHz 
001x The 1/4 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  20 MHz 15 MHz 
01xx The 1/8 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  10 MHz 7.5 MHz 
1000 The 2/3 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock. 
The clock duty is 67%.  53.3 MHz 40 MHz 
1001 
The 1/3 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  26.7 MHz 20 MHz 
1010 The 1/6 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  13.3 MHz 10 MHz 
1011 The 1/12 cycle of the CAN prescaler clock is 
selected as a CAN system clock.  6.7 MHz 5 MHz 
110x The 1/5 cycle of the CAN pr
escaler clock is selected 
as a CAN system clock.  16 MHz 12 MHz 
111x The 1/10 cycle of the CAN prescaler clock is 
selected as a CAN system clock.  8 MHz 6 MHz 
 
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CHAPTER  21-1: CAN Prescaler 
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2. CAN Prescaler Register 
 FUJITSU SEMICONDUCTOR LIMITED 
Chapter: CAN Prescaler 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  6 
 
   Before changing the value of the CAN prescaler setting bit, set the initialization bit of the CAN Control 
Register (CTRLR) to 1, and stop all bus operations. 
   To use the PLL output as a CAN prescaler clock, se t the initialization bit of the CAN Control Register 
(CTRLR) to 0 after PLL oscillation has been stabilized. 
   Make sure that the CAN system clock output  by the CAN prescaler is 16 MHz or less. 
 
 
CHAPTER  21-1: CAN Prescaler 
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1. Overview 
 
CHAPTER: CAN Controller 
This chapter explains CAN. 
 1.
 Overview 
2. Configuration 
3. CAN Controller Operations 
4. CAN Registers  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: FC42-E02.1 
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CHAPTER  21-2: CAN Controller 
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1. Overview 
 
1. Overview 
The CAN controller complies with CAN protocol version 2.0A/B, a standard protocol for serial 
communication.CAN is widely used in various industrial fields such as automobile and factory 
automation. 
The CAN controller has the following features: 
  Supports CAN protocol version 2.0A/B 
   Supports a bit rate up to 1 Mbits/s 
   Identifier mask for each message object 
   Supports programmable FIFO mode 
   Maskable interrupt 
   Supports 32 message buffers 
   Supports programmable loop-back mode for self-test operation 
   Read and write from/to the message  buffer using interface registers 
 
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CHAPTER  21-2: CAN Controller 
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