Fujitsu Series 3 Manual
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3. CAN Controller Operations
Table 3-3 CAN bit time parameters Parameter Range Function
BRP [1-32] Defines the length of time quantum tq.
Sync_Seg 1 tq Fixed length. Synchronization to system clock.
Prop_Seg [1-8] tq Compensates for the physical delay times.
Phase_Seg1 [1-8] tq Assures edge phase errors before the sampling point.
May be prolonged temporarily by synchronization.
Phase_Seg2 [1-8] tq Assures edge phase errors after the sampling point.
May be shortened temporarily by...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-1244.png "Page 1245
3. CAN Controller Operations
Table 3-3 CAN bit time parameters Parameter Range Function
BRP [1-32] Defines the length of time quantum tq.
Sync_Seg 1 tq Fixed length. Synchronization to system clock.
Prop_Seg [1-8] tq Compensates for the physical delay times.
Phase_Seg1 [1-8] tq Assures edge phase errors before the sampling point.
May be prolonged temporarily by synchronization.
Phase_Seg2 [1-8] tq Assures edge phase errors after the sampling point.
May be shortened temporarily by...")
3. CAN Controller Operations 3.4. FIFO buffer function The following explains the configuration of a FIFO buffer of the message object and its operations in handling received messages. Configuration of a FIFO buffer The configuration of the receive message object belonging to a FIFO buffer is the same as that of a receive message object except the EoB bit. (See Co nfiguring a Receive Message Object in 3.3 Message reception .) A FIFO buffer is use d by concatenating two or more receive message objects. To store received messages into this FIFO buffer, the ID and the mask settings of the receive message objects must be matched when they are used. The first receive message object of the FIFO buffer ha s the lowest message number, i.e., the highest priority. In the last receive message object of the FIFO buffer, se t 1 to the EoB bit to indicate that the object is the end of the FIFO buffer block. (Except in the last me ssage object, the EoB bit in each message object that uses the FIFO buffer configuration must be set to 0.) Be sure to con f ig ure the sam e settings for the ID and the masks of message objects used in the FIFO buffer. When the FIFO buffer is not used, be sure to set the EoB bit to 1. Receiving messages using FIFO buffers A received message, when it matches the FIFO buffer ID, is stored into the receive message object in the FIFO buffer with the lowest message number. When a message is stored into the receive message object in the FIFO buffer, the NewDat bit of this receive message object is set to 1. When the NewDat bit is set in receive message object while the EoB bit is set to 0, the receive message object is protected until the last receive messa ge object (with EoB bit = 1) is reached.Meanwhile, the CAN controller does not write to the FIFO buffer. When both of the following conditions are met, the next incoming message is written to the last message object and therefore overwrites the previous message. Valid data is stored into the last FIFO buffer The NewDat bit of the receive message object is not written by 0 (to release the write protect) If 0 is not written to the NewDat bit (to release the write protect) of the receive message object while valid data is stored into the last FIFO buffer, the next incoming message is written to the last message object and overwrites the previous message. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1205 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations Reading from a FIFO buffer To read the contents of a receive message object, th e CPU transfers the object to the Message Interface Register by writing the received message number to the IFx Command Request Register. Then, set WR/RD in the IFx Command Mask Register to 0 (read), set TxRqst/NewDat = 1, ClrIntPnd = 1, and set the NewDat bit and IntPnd bit to 0. To assure the correct FIFO buffer function, be sure to first read a receive message object in the FIFO buffer with the lowest message number, and then other objects in ascending order. Figure 3-2 shows how the CPU handles the message objects the FIFO buff er concatenate s. Figure 3-2 CPU handling of FIFO buffer Start Read the CAN Interrupt Register Message interrupt Status interrupt handling CAN Interrupt Register value End (Normal handling) 0x0000 Message number = CAN Interrupt Register value Other than 0x8000, 0x0000 Write (message number) to the IFx Command Request Register Read the Message Interface Register (Reset: NewDat=0, IntPnd=0) Read the IFx Message Control Register NewDat = 1 Read the IFx Message Data Registers A and B EoB = 1 Message number = Message number + 1 No Yes Yes No 0x8000 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1206 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations 3.5. Interrupt function The following explains the interrupt handing using the status interrupt (IntId = 0x8000) and message interrupt (IntId = Message number). If two or more interrupts are pending, the CAN Interrupt Register points to a pending interrupt code with the highest priority. The chronological order of the interrupt codes are neglected, and the interrupt code with the highest priority is always shown. The interrupt code is retained until the CPU clears it. The status interrupt (0x8000 of the IntId bit) has the highest priority. Priority of message interrupts is determined by the message number. A smaller number has a higher priority while the larger the lower. A message interrupt is cleared by clearing the IntPnd b it of the message object. A status interrupt is cleared by reading the CAN Status Register. The IntPnd bit in the CAN interrupt Pending Register indicates whether an interrupt has been caused. When no interrupts are pending, the IntPnd bit retains 0. While the IE bit in the CAN Control Register, and th e TxIE bit and RxIE bit in the IFx Message Control Register are set to 1, if the IntPnd bit turns to 1 , then the interrupt line to the CPU becomes active. The interrupt line remains active until the CAN Interrupt Pending Register is cleared to 0 (the interrupt cause is reset) or the IE bit in the CAN Control Register is reset to 0. The 0x8000 value of the CAN Interrupt Register indicat es that the CAN Status Register has been updated by the CAN controller. This interrupt has the highest priority. The interrupt by updating the CAN Status Register can enable or disable the setting of the CAN In terrupt Register using the EIE bit and SIE bit in the CAN Control Register.The interrupt line to the CPU can be controlled by the IE bit in the CAN Control Register. A write access from the CPU can update (reset) the RxOk bit, TxOk bit, and LEC bit in the CAN Status Register. However, the write access canno t generate or reset an interrupt. Except the 0x8000 and 0x0000 values, the CAN Interr upt Register indicates that a message interrupt is pending, and that the interrupt has the highest priority. The CAN Interrupt Register is u pdated even when IE is reset. The source of a message interrupt to the CPU can be checked from the CAN Interrupt Register or CAN Interrupt Pending Register. (See 4.5 Message handler registers ) When clearing a message interrupt, the m essage data c an be read concurrently. If a message interrupt indicated by the CAN Interrupt Register is cleared, the CAN Interrupt Register sets another interrupt with the next higher priority. This waits for the next interrupt handling. If no interrupts are pending, the CAN Interrupt Register shows the 0x0000 value. A status interrupt (Int Id = 0 x8000) is cleared by a read acces s to the CAN Status Register. A write access to the CAN Status Register will not generate a status interrupt (IntId = 0x8000). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1207 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations 3.6. Bit timing The following provides the overview of the bit timing and explains about the bit timing in the CAN controller. Each CAN node in the CAN network has its own clock generator (usually a quartz oscillator). The time parameter of the bit time can be configured indivi dually for each CAN node. Even if each CAN nodes oscillator has a different period (fosc), a common bit rate can be generated. The oscillator frequencies vary slightly because of changes in temperature or voltage, or deterioration of components. As long as the frequencies vary only within the tolerance range (df) of the oscillators, the CAN nodes can compensate for the different bit rates by resynchronizing to the bit stream. The bit time can be divided into four segm ents according to the CAN specifications (see Figure 3-3), into t he synchro nization segment (Sync_Seg), the propag ation time segment (Prop_Seg), the phase buffer segment 1 (Phase_Seg1), and the phase buffer segment 2 (Phase_Seg2). Each segment consists of the programmable number of time quanta (See Ta b l e 3 - 3). The basic unit of the time quantum (tq) is defined by C AN contr o llers system clock fsys and the baud rate prescaler (BRP). tq = BRP / fsys CANs system clock fsys is the frequency of its clock input (See Figure 2-1). Synchronization segment Sy nc_Seg i s a timing in the bit time where edges of the CAN bus level are expected to occur. Propagation time segment Prop_Seg compensates for the physical delay times within the CAN network. Phase buffer segments Phase_Seg1 and Phase_Seg2 must specify the sampling points. Resynchronization jump width (SJW) must define the width within which resynchronization can move the sampling point to compensate for edge phase errors. Figure 3-3 Bit timing A bit time (BT) Sync _Seg Prop_Seg Phase_Seg1 Phase_Seg2 A time quantum (tg)Sampling point FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1208 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations Table 3-3 CAN bit time parameters Parameter Range Function BRP [1-32] Defines the length of time quantum tq. Sync_Seg 1 tq Fixed length. Synchronization to system clock. Prop_Seg [1-8] tq Compensates for the physical delay times. Phase_Seg1 [1-8] tq Assures edge phase errors before the sampling point. May be prolonged temporarily by synchronization. Phase_Seg2 [1-8] tq Assures edge phase errors after the sampling point. May be shortened temporarily by synchronization. SJW [1-4] tq Resynchronization jump width. Will not be longer than either of the phase buffer segments. The following shows the bit timing in the CAN controller. Figure 3-4 The bit timing in the CAN controller Sync _Seg TEG1 TEG2 Sampling point A bit time (BT) A time quantum (tg) Table 3-4 CAN controller parameters Parameter Range Function BRPE, BRP [0-1023] Defines the length of time quantum tq. Can extend the prescaler by up to 1024 by the Bit Timing Register and the Prescaler Extension Register. Sync_Seg 1 tq Synchronization to system clock. Fixed length. TSeg1 [1-15] tq A time segment before the sampling point. Equivalent to Prop_Seg and Phase_Seg1. Can be controlled by the Bit Timing Register. TSeg2 [0-7] tq A time segment after the sampling point. Equivalent to Phase_Seg2. Can be controlled by the Bit Timing Register. SJW [0-3] tq Resynchronization jump width. Can be controlled by the Bit Timing Register. The following shows the relations among the parameters: tq = ([BRPE, BRP]+1) / fsys BT = SYNC_SEG + TEG1 + TEG2 = (1 + (TSeg1 + 1) + (TSeg2 + 1)) x tq = (3 + TSeg1 + TSeg2) x tq FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1209 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations 3.7. Test mode The following explains how to configure test mode, and about its operations. Test mode setting Test mode is entered by setting the Test bit in the CAN Control Register to 1. In test mode, the Tx1, Tx0, LBack, Silent, and Basic bits in th e CAN Test Register are enabled. When the Test bit in the CAN Control Register is set to 0, all test register functions are disabled. Silent mode The CAN controller can be set in silent mode by programming the Silent bit in the CAN Test Register to 1. In silent mode, the CAN controller can receive data frames and remote frames, but only outputs recessive bits onto the CAN bus and does not send messages and ACK. When the CAN controller is required to send dominant bits (ACK bits, overload flags, active error flags), the CAN controller uses the internal rerouting circuit to send them to the RX side. In this operation, the RX side can receive dominant bits rerouted inside th e CAN controller even when the CAN bus remains in a recessive state. In silent mode, the analysis of CAN bus traffic is possible without being affected by transmission of the dominant bits (ACK bits, error flags). Figure 3-5 shows the connection of the CAN_TX and CAN_RX signals to the CAN controller in silent m ode. Figure 3-5 CAN controller in silent mode CAN_TX CAN_RX = 1 Tx Rx CAN Core CAN controller FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1210 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations Loop back mode The CAN controller can be set in loop back mode by programming the LBack bit in the CAN Test Register to 1. Loop back mode can be used for self-diagnostic functions. In loop back mode, TX is connected with RX inside the CAN controller. The CAN controller treats the transmitted messages as messages received by RX, and stores the messages passed acceptance filtering into the receive buffer. Figure 3-6 shows the connection of the CAN_TX and CAN_RX signals to the CAN controller in loop back m ode. Figure 3-6 CAN controller in loop back mode CAN_TX CAN_RX Tx Rx CAN Core CAN controller Bei ng independent of external signals, the CAN controller does not sample dominant bits in the acknowledgement slot of a data/remote frame. This usually causes the CAN controller to generate acknowledgement errors. In this test mode , however, the errors are not cased. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1211 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations Combination of silent mode and loop back mode Loop back mode and silent mode can be combined by setting the LBack bit and Silent bit in the CAN Test Register to 1 at the same time. This mode can be used for Hot self-test. The Hot self-test means that the CAN controller can be tested in loop back mode without affec ting operation of the CAN system, becau se a constant recessive value is output from the CAN_TX pin and the input to the CAN_RX pin is ignored. Figure 3-7 shows the connection of the CAN_TX and CAN_RX signals to the CAN controller when silent m ode and loop bac k mode are combined. Figure 3-7 CAN controller in combined silent and loop back modes CAN_TX CAN_RX = 1 Tx Rx CAN Core CAN controller Basic mode The CAN controller can be set in basic mode by programming the Basic bit in the CAN Test Register to 1. In basic mode the CAN controller runs without using the message RAM. The IF1 Message Interface Register is used to control transmission. First when sending a message, the contents of transm ission are configured in the IF1 Message Register. Then the Busy bit in the IF1 Command Request Register is set to 1 to request transmission. While the Busy bit is set to 1, the IF1 Message Interface Register is locked or the transmission is pending. When the Busy bit is set to 1, the CAN controller performs the following operation: Immediately when the CAN bus becomes idle, the CAN controller loads the contents of the IF1 Message Interface Register to the send shif t register to start transmission. When the transmission has finished successfully, the Busy bit is reset to 0, and the locked IF1 Message Interface Register is released. While pending, the transmission can be aborted by resetting the Busy bit in the IF1 Command Request Register to 0. If the Busy bit is reset to 0 during the transmission, a possible retransmission in case of lost arbitration or error detection is disabled. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1212 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations The IF2 Message Interface Register is used to control reception. All contents of the message are received without using acceptance filteri ng. The contents of the received message can be read by setting the Busy bit in the IF2 Command Request Register to 1. When the Busy bit is set to 1, the CAN controller performs the following operation: Stores the received message (the contents of the receive shift register) into the IF2 Message Interface Register without any acceptance filtering. If a new message is stored into the IF2 Message Inte rface Register, the CAN controller sets the NewDat bit to 1. When an additional message is received while the NewDat bit is 1, then CAN controller sets MsgLst to 1. In ba sic m ode, all the message objects related to control and status bits are ignored as well as the control mode setti ng of the IFx Command Mask Register. The message number of the command request register is ignored. The NewDat bit and MsgLst bit in the IF2 Message Cont rol Register retain their usual function, DLC3-0 indicates the received DLC, and other control bits are read as 0. Software control of the CAN_TX pin CAN_TX is a CAN send pin and has four output functions: Outputs serial data (Usual output) Outputs CAN sampling point signals to monitor the bit timing of the CAN controller Outputs a constant dominant value Outputs a constant recessive value The output of constant dominant and recessive values, combined with CAN_RX monitoring function of the CAN receive pin, can be used to check the CAN bus physical layer. The output mode of the CAN_TX pin can be controlled by the Tx1 and Tx0 bits in the CAN Test Register. When using CAN message transmission or any of the loop back, silent, or basic modes, the CAN_TX must be set to the serial data output. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1213 MB9Axxx/MB9Bxxx Series
3. CAN Controller Operations 3.8. Software initialization The following explains about initialization using software. The sources of software initialization are as follows: Hardware reset Setting the Init bit in the CAN Control Register Shift to a busoff state A hardware reset resets all other than the message RAM (excluding the MsgVal, NewDat, IntPnd, and TxRqst bits). The message RAM must be initialized, afte r the hardware reset, by the CPU or by setting the MsgVal in the message RAM to 0. The Bit Timing Regi ster must be configured before clearing the Init bit in the CAN Control Register to 0. The Init bit in the CAN Control Register is set to 1 in the following conditions: Writing 1 from the CPU Hardware reset In a busoff state When the Init bit is set to 1, all message transfer from/to the CAN bus is stopped, and the CAN_TX pin in the CAN bus output is in a recessive state (excluding CAN_TX test mode). Setting the Init bit to 1 does not change the error counter and any register. When the Init bit and CCE bit in the CAN Control Register are set to 1, the Bit Timing Register for baud rate control and Prescaler Extension Register can be configured. The software initialization is completed by resetting the Init bit to 0. By waiting for the occurrence of a consec utive 11 recessive bits (i.e., bus idle) after the Init bit is reset to 0, the message is transferred after synchron ization with data transfer on the CAN bus. Before changing message object masks ID, XTD, EoB, and RmtEn during normal operation, the MsgVal must be disabled. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 21-2: CAN Controller MN706-00002-1v0-E 1214 MB9Axxx/MB9Bxxx Series