Fujitsu Series 3 Manual

							 
 
 
CHAPTER 20-2: USB Function ........................................................................\
................1073 
1. Overview of USB Function........................................................................\
..................1074 
1.1. Features of USB func tion ........................................................................\
.................. 1074 
2. Configuration of USB Function........................................................................\
............1075 
3. Operations of  USB Function........................................................................\
................1076 
3.1. USB functi on operation ........................................................................\
..................... 1077 
3.2. Detection of connec tion and disconnection .............................................................. 1080 
3.3. Operation of each register  in response to a command ............................................. 1083 
3.4. Suspend  function ........................................................................\
.............................. 1086 
3.5. Wake-up  function ........................................................................\
.............................. 1087 
3.6. DMA transf er function ........................................................................\
....................... 1089 
3.7. NULL transf er function ........................................................................\
...................... 1094 
3.8. STALL response/rel ease of endpoint 0 ..................................................................... 1095 
3.9. Stall response/release of endpo ints 1 to 5 ................................................................ 1097 
4. Examples of USB Func tion Setting Procedures.......................................................... 1101 
5. USB Function  Registers ........................................................................\
...................... 1108 
5.1. UDC Control Re gister (UDCC) ........................................................................\
......... 1110 
5.2. EP0 Control R egister (EP0C) ........................................................................\
........... 1113 
5.3. EP1 to 5 Control Regi sters (EP1C to EP5C) ............................................................ 1115 
5.4. Time Stamp R egister (TMSP) ........................................................................\
........... 1119 
5.5. UDC Status Regi ster (UDCS) ........................................................................\
........... 1120 
5.6. UDC Interrupt Enable  Register (UDCIE)................................................................... 1123 
5.7. EP0I Status Regi ster (EP0IS) ........................................................................\
........... 1125 
5.8. EP0O Status Regi ster (EP0OS)........................................................................\
........ 1127 
5.9. EP1 to 5 Status Regi sters (EP1S to EP5S) .............................................................. 1129 
5.10. EP0 to 5 Data Registers (EP0DT H to EP5DTH/EP0DTL to EP5DTL) ................... 1133 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05019\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 20-3: USB Host ........................................................................\
...................... 1135 
1. Overview of USB host ........................................................................\
......................... 1136 
2. USB host conf iguration ........................................................................\
........................ 1138 
3. USB host oper ations........................................................................\
........................... 1139 
3.1. Device c onnection ........................................................................\
............................. 1140  
3.2. USB bus  resetting ........................................................................\
............................. 1142  
3.3. Token  packet ........................................................................\
..................................... 1 143 
3.4. Data  packet ........................................................................\
....................................... 11 4 6  
3.5. Handshake packet ........................................................................\
............................ 1147 
3.6. Retry  function ........................................................................\
.................................... 11 4 8  
3.7. SOF interru pt........................................................................\
..................................... 11 4 9  
3.8. Error stat us........................................................................\
...................................... .. 1151 
3.9. End of  packet ........................................................................\
.................................... 1 152 
3.10. Suspend and resu me operations ........................................................................\
.... 1153 
3.11. Device disconnection ........................................................................\
...................... 1156 
4. USB host setting pr ocedure examples ........................................................................\
 1157 
5. USB host r egisters........................................................................\
.............................. 1162  
5.1. Host Control Registers 0 and 1 (HCNT0 and HCNT1) ............................................. 1164 
5.2. Host Interrupt R egister (HIRQ) ........................................................................\
......... 1169 
5.3. Host Error Status  Register (HERR)........................................................................\
... 1173 
5.4. Host Status Regi ster (HSTATE) ........................................................................\
........ 1176 
5.5. SOF Interrupt Frame Comp are Register (HFCOMP) ............................................... 1179 
5.6. Retry Timer Setup Register (HRTIMER) ................................................................... 1180 
5.7. Host Address R egister (HADR)........................................................................\
......... 1181 
5.8. EOF Setup Register (HEOF) ........................................................................\
............ 1182 
5.9. Frame Setup Register (HFRAME) ........................................................................\
.... 1183 
5.10. Host Token Endpoint  Register (HTOKEN) .............................................................. 1184 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\05020\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 21-1: CAN Prescaler ........................................................................\
.............. 1187 
1. Overview and configuration ........................................................................\
................. 1188 
2. CAN Prescaler Register ........................................................................\
...................... 1189 
2.1. CAN Prescaler Regi ster (CANPRE) ........................................................................\
. 1190 
CHAPTER 21-2: CAN Controller ........................................................................\
.............. 1193 
1. Overview ........................................................................\
............................................ . 1194 
2. Confi guration ........................................................................\
....................................... 1195 
3. CAN Controller  Operations ........................................................................\
.................. 1196 
3.1. Message objects ........................................................................\
............................... 1197  
3.2. Message transmission ........................................................................\
...................... 1199 
3.3. Message  reception ........................................................................\
............................ 1202 
3.4. FIFO buffe r function ........................................................................\
.......................... 1205  
3.5. Interrupt function ........................................................................\
............................... 1 207 
3.6. Bit  timing ........................................................................\
........................................ ... 1208 
3.7. Test mode ........................................................................\
......................................... . 1210 
3.8. Software in itialization ........................................................................\
........................ 121 4 
4. CAN Registers........................................................................\
.....................................12 15 
4.1. CAN register functions ........................................................................\
...................... 1218 
4.2. Total control registers ........................................................................\
........................ 121 9 
4.2.1. CAN Control Register (CTRLR) ........................................................................\
.......1220 
4.2.2. CAN Status Register (STATR)........................................................................\
..........1224 
4.2.3. CAN Error Counter (ERRCNT) ........................................................................\
........1227 
4.2.4. CAN Bit Timing Register (BTR) ........................................................................\
........1229 
4.2.5. CAN Interrupt Register (INTR) ........................................................................\
.........1230 
4.2.6. CAN Test Register (TESTR) ........................................................................\
............1231 
4.2.7. CAN Prescaler Extension Register (BRPER) ..........................................................1233 
4.3. Message interface registers ........................................................................\
.............. 1234 
4.3.1. IFx Command Request Register (IFxCREQ) ...........................................................1235 
4.3.2. IFx Command Mask Register (IFxCMSK) ................................................................1237 
4.3.3. IFx Mask Registers 1, 2 (IFxMSK1 ,IFxMSK2) ........................................................1242 
4.3.4. IFx Arbitration Registers 1, 2 (IFxARB1, IFxARB2)..................................................1243 
4.3.5. IFx Message Control Register (IFxMCTR) ...............................................................1244 
4.3.6. IFx Data Registers A1, A2, B1, and B2   
(IFxDTA1, IFxDTA2, IFxDTB1, and IFxDTB2) ......................................................1245 
4.4. Message  objects ........................................................................\
............................... 1246  
4.5. Message handler  registers........................................................................\
................ 1252 
4.5.1. CAN Transmit Request Registers 1, 2 (TREQR1, TREQR2) ...................................1253 
4.5.2. CAN New Data Registers 1, 2 (NEWDT1, NEWDT2) ..............................................1255 
4.5.3. CAN Interrupt Pending Registers 1, 2 (INTPND1, INTPND2)..................................1257 
4.5.4. CAN Message Valid Registers 1, 2 (MSGVAL1, MSGVAL2) ...................................1259 
FUJITSU SEMICONDUCT OR LIMITED 
MN706-00002-1v0-E 
\05021\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 FUJITSU SEMICONDUCTOR LIMITED 
  
FUJITSU SEMICONDUCTOR CONFIDENTIAL  18 
CHAPTER 22: CRC (Cyclic Redundancy Check) ............................................................1261 
1. CRC Overview ........................................................................\
.....................................126 2 
2. CRC Oper ations........................................................................\
..................................1263  
2.1. CRC calculation sequence........................................................................\
................ 1264 
2.2. CRC use  examples ........................................................................\
........................... 1265 
3. CRC Registers........................................................................\
....................................126 9 
3.1. CRC Control Register (CRCCR) ........................................................................\
....... 1270 
3.2. Initial Value Re gister (CRCINIT) ........................................................................\
....... 1273 
3.3. Input Data R egister (CRCIN)........................................................................\
............ 1274 
3.4. CRC Regist er (CRCR) ........................................................................\
...................... 1275 
CHAPTER 23: External Bus Interface ........................................................................\
......1277 
1. External Bus In terface Features........................................................................\
..........1278 
2. Block  Diagram ........................................................................\
.....................................12 79 
3. Oper ation........................................................................\
........................................... ..1280 
3.1. Fundamental SRAM and flash memory accesses .................................................... 1281 
3.2. NAND flash memory access ........................................................................\
............. 1282 
3.2.1. Read access to NAND flash memory.......................................................................1283 
3.2.2. Write (auto program) access ........................................................................\
............1284 
3.2.3. Auto block erase access ........................................................................\
..................1285 
3.2.4. Error reply ........................................................................\
..................................... ...1286 
4. Example waveforms of external memory access ........................................................1287 
4.1. Word read access  to 8-bit wide SRAM..................................................................... 1288 
4.2. Serial word write/read  access to 16-bit wide SRAM ................................................. 1289 
4.3. Issue of an 8-bit NAND flas h memory read/write command..................................... 1290 
4.4. 8-bit NAND flash me mory status read...................................................................... 1291 
4.5. 8-bit NAND flash  memory data write........................................................................\
. 1292 
4.6. 16-bit NOR flash memory pa ge read........................................................................\
 1293 
5. Endianness and Va lid Byte Lanes........................................................................\
.......1294 
6. Connection  Examples ........................................................................\
......................... 1297 
7. Registers ........................................................................\
........................................... ..1299 
7.1. Mode Register 0 to Mode Register 7 ........................................................................\
 1300 
7.2. Timing Register 0 to  Timing Register 7 ..................................................................... 1302 
7.3. Area Register 0 to  Area  Register 7 ........................................................................\
... 1306 
CHAPTER 24: Debug Interface........................................................................\
................1309 
1. Overview ........................................................................\
............................................ .1310 
2. Pin Descr iption ........................................................................\
.................................... 1 311 
2.1. Pins for Debug Purposes ........................................................................\
.................. 1312 
2.2. ET M Pins........................................................................\
.......................................... . 1313 
2.3. Functions Initially Assigned  to Pins ........................................................................\
... 1314 
2.4. Internal Pull-Up s of JTAG Pins........................................................................\
.......... 1315 
APPENDIXES ....................................................................\
............................................1317  
1. Register Map ........................................................................\
.......................................1 318 
MN706-00002-1v0-E 
\05022\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
MAJOR CHANGES IN THIS EDITION 
Page Section Change Results 
- - 
MB9BFxxx Series, MB9BF500 Series   this Series 
9 3.  Cortex-M3 Architecture 
   Corrected the description of   Cortex-M3 Core Version of   
   Cortex-M3 Core. 
11  CHAPTER 1 
System Overview 
4. Mode 
  external reset   INITX pin input reset 
17  2. Clock Generation Unit Configuration/Block Diagram 
   Corrected Figure 2-1. (D eleted USB-PLL block.) 
21  3.3. PLL clock control 
   Corrected Table 3-2. 
   Added . 
22  3.4. Oscillation stabilization wait time 
  Corrected . 
24, 25  4. Clock Setup Procedure Examples 
   Corrected Figure 4-1 and Figure 4-2. 
   Main CR   High-speed CR 
   Sub CR   Low-speed CR 
   Corrected . 
28  5.1. System Clock Mode Control Register (SCM_CTL) 
   Corrected . 
29, 30  5.2. System Clock Mode Status Register (SCM_STR) 
   Corrected the description of [bit2] and [bit0]. 
(Deleted Set this bit to 0 when writing..) 
37  5.9. Clock Stabilization Wait Time Register (CSW_TMR) 
   Corrected the description of [bit6:4].   
47, 48  CHAPTER 2-1 
Clock 
6. Clock Generation Unit Usage Precautions 
  Corrected   Switching clock modes. 
   Corrected the description of   Correlation between the clock 
mode switching and the oscillation stable bit. (Main CR   
High-speed CR, Sub CR   Low-speed CR) 
   If the standby mode is released by an interrupt, the clock mode is 
switched to that indicated by the RCM bit in the SCM_CTL. 
    
If the standby mode is released by  an interrupt, the device restarts 
in the clock mode that indicated by the RCM bit in the 
SCM_CTL. 
 
FUJITSU SEMICONDUCTOR LIMITED 
MB9Axxx/MB9Bxxx  Series 
MN706-00002-1v0-E 
\05023\051  
						

							 
 
 
 
Page Section Change Results 
All Separated from the Clock chapter. 
51 2. High-Speed CR Trimming Function Configuration and Block 
Diagram 
   Corrected Figure 2-1. (CRTRIM   CLKHC_div) 
53 to 58  4. High-Speed CR Trimming Function Setup Procedure Example 
   Corrected Figure  4-1. (TRD[7:0]  TRD) 
   Corrected the description of   Frequency trimming setup. 
(...the register.   ...the MCR_FTRM Register.) 
   Corrected the whole description in   How to calculate the 
frequency trimming data. 
   Corrected the whole description in   Example trimming data 
acquisition using input capture. 
   Added   Frequency trimming procedure example. 
   Added   Xtrm calculation procedure example. 
   Added   Procedure example of using CR trimming area 
storage data inside flash memory. 
60  5.1. High-speed CR oscillation Frequency Division Setup Register 
(MCR_PSR) 
  Added the explanation to the summaries. 
61  5.2. High-speed CR oscillation Frequency Trimming Register 
(MCR_FTRM) 
  Changed the whole description. 
62  CHAPTER 2-2 
High-Speed CR 
Trimming 
5.3. High-Speed CR Oscillator Re gister Write-Protect Register 
(MCR_RLR) 
   Corrected the summaries. 
   Corrected the description of [bit31:0]. 
67 2.  Configuration 
   Corrected the figures of   Block Diagram of Resets. 
69  3.1. Reset Causes 
  Corrected the table of   Low-voltage Detection Reset, External 
Voltage Monitoring (LVDH). 
(Deleted Note: of Initialization target.) 
(bit3(LVDH)   bit0(PONR)) 
73  3.2.1. Resets to Cortex-M3 
  Power initialization reset   Power-on reset 
74  3.2.2. Resets to Peripheral Circuit 
  Power initialization reset   Power-on reset 
   Corrected . (APVC1  APBC1) 
79 to 81  CHAPTER 3 
Resets 
4.1. Reset Cause Register (RST_STR: ReSeT STatus Register) 
  Corrected b it3. (LVDH   Reserved) 
   Corrected the description of [bit0]. (Added low-voltage detection 
reset.) 
   Corrected . (Added low-voltage detection reset.) 
 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05024\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
 
Page Section Change Results 
84 1. Overview 
   Corrected the description of   Operations of Low-voltage Reset 
Circuit. 
   Corrected . 
85 2.  Configuration 
   Corrected the figures of   Block diagram of Low-voltage 
Detection Circuit. 
   Corrected the description of   Low-voltage Detection Voltage 
Control Register. 
   Added   Low-voltage Detection Circuit Status Register. 
87  3. Explanation of Operations 
    Operations of Low-Voltage Detection Reset Circuit 
  Corrected the description. 
  Corrected the figure. 
  Deleted . 
88, 89 
    Operations of Low-voltage Detection Interrupt Circuit 
  Corrected the description of   Operations. 
  Corrected the figures of   Canceling a low-voltage detection   
 interrupt request. 
  Corrected . 
90  4. Setup Procedure Examples 
   Deleted Stopping a low-voltage detection reset. 
   Deleted Restarting a low-voltage detection reset . 
   Corrected Figure 4-1. 
92, 93  5.1. Low-voltage Detection Voltage Control Register (LVD_CTL) 
   Corrected the summaries. 
   Corrected b it6. (LVDRE   Reserved) 
   Corrected . 
97  CHAPTER 4: 
Low-voltage Detection 
Added 5.5. Low-voltage Detection Circuit Status Register (LVD_STR2).
116  3.2. Operations of TIMER modes (high speed CR timer, main 
timer, PLL timer, low speed CR timer, and sub timer modes) 
   Added . 
119  3.3. Operations of STOP mode 
   Added . 
121  CHAPTER 5 
Low Power 
Consumption Mode 
4. Standby Mode Setting Procedure Examples 
  Added . 
 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05025\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
 
Page Section Change Results 
Whole 
chapter Corrected register name. 

  Interrupt Request Batch Read Register 00 (IRQMON00)    
EXC02 Batch Read Register (EXC02MON) 
   Interrupt Request Batch Read Register 01 to 48 (IRQMON01 to 48)
    
IRQ00 Batch Read Register to IRQ47 Batch Read Register 
(IRQ00MON to IRQ47MON) 
128 to 130  3. Exception and Interrupt Vectors 
   Corrected the header of  Table 3-1. (Interrupt No.   IRQ No.) 
133  4.1. DMA Request Selection Register (DRQSEL) 
   Corrected the summaries. 
(IRQMONxx, xx=00 to 48   IRQxxMON, xx=00 to 47) 
158  4.19. IRQ34 Batch Read Register (IRQ34MON) 
   Corrected the description of [bit4:0]. (IRQ2 to 6   DRQ) 
159  CHAPTER 6: 
Interrupts 
4.20. IRQ35 Batch Read Register (IRQ35MON) 
  Corrected the description of [bit5:0].   
(IRQ7 to 10   USB Interrupt Source, IRQ1   DRQO,   
IRQ0   DRQI) 
176 CHAPTER 7 
External Interrupt and 
NMI Control Sections  4.2. External Interrupt Request Register [EIRR] 

  Corrected the initial value of   Register configuration. (0   X)
   Added . 
191 3.2.  Software-Burst Transfer 
   Corrected the description of   Transfer data size.   
(TW=00   TW=10) 
225  CHAPTER 8 
DMAC 
5.4. Configuration B Register (DMACB) 
  Corrected bit15:8. (SP[3:0], DP[3:0]   Reserved) 
 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05026\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
 
Page Section Change Results 
Whole 
chapter The descriptions have been changed by sharing USB pin/sub 
oscillation pin and the ports. 

  Added the description of USB pin and sub oscillation pin. 
   The following registers are added. 
Port function setting register 8 (PFR8) 
Port input/output direction setting register 8 (DDR8) 
Port input data register 8 (PDIR8) 
Port output data register 8 (PDOR8) 
Special Port Setti ng Register (SPSR) 
235  2. Configuration, Block Diagram, and Operation 
   Corrected Figure 2-1.   
(Deleted a signal line that extends from the PDOR to EPFR register.)
244  4.1. Port Function Setting Register (PFRx) 
   Corrected . 
245  4.2. Pull-up Setting Register (PCRx) 
   Added . 
246  4.3. Port input/output Direction Setting Register (DDRx) 
  Added . 
247  4.4. Port Input Data Register (PDIRx) 
   Added . 
248  4.5. Port Output Data Register x (PDORx) 
   Added . 
250  4.7. Extended Pin Function Setting Register (EPFRx) 
   Corrected the initial value. 
252  4.8. Extended Pin Function Setting Register 00 (EPFR00) 
   Corrected the descri ption of [bit1].   
(Internal CR   Internal high-speed CR) 
260  4.10. Extended Pin Function Setting Register 02 (EPFR02) 
   Corrected the error in description. (RTO02   RTO 1 2 )  
264  4.11. Extended Pin Function Setting Register 04 (EPFR04) 
   Added . 
268  4.12. Extended Pin Function Setting Register 05 (EPFR05) 
   Added . 
295  CHAPTER 9 
I/O PORT 
5. Usage Precautions 
  Corrected the description of   Product Specifications and 
Peripheral Function Assignment. 
315 CHAPTER 10  Clock supervisor  7. Usage Precautions 

  Added   The settings for CSV OFF and external reset.. 
 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05027\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
 
Page Section Change Results 
321 to 325 3. Operations 
   Corrected Table 3-1. 
   Deleted the following descriptions from   Value register 
(WdogValue). 
 However, during tool break, the value can be read only when 
the watchdog timer is stopped. 
   Corrected the description of   Reload and lock of the register of 
the software watchdog timer. 
   Corrected the description of   Value register (WDG_VLR). 
   Corrected Table 3-6. 
326, 327  4. Setting Procedure Example 
   Corrected Figure 4-1 and Figure 4-2. 
332  6.1. Software Watchdog Timer Load Register (WdogLoad) 
   Corrected the description of [bit31:0]. 
In case of writing 
    When 0 is written, an interrupt will be generated right away. 
    When 0 is written, an interrupt will be generated. 
In case of reading 
    Added A set value can be read.. 
   Corrected . (Del eted right away.) 
333  6.2. Software Watchdog Timer Value Register (WdogValue) 
   Deleted the following description from . 
Reading of this register is possible only if the watchdog timer is 
set as it stops at tool break. Other read value is not guaranteed. 
336  6.5. Software Watchdog Timer Interrupt Status Register (WdogRIS)
   Corrected the attribute of   Register configuration.   
(bit0 : R/W   R) 
   Corrected the descri ption of [bit0]. 
337  6.6. Software Watchdog Timer Lock Register (WdogLock) 
   Corrected the initial value of   Register configuration.   
(0x00000001   0x00000000) 
   Corrected the description of In case of writing of [bit31:0]. 
   Corrected . 
338  6.7. Hardware Watchdog Timer Load Register (WDG_LDR) 
   Corrected the description of [bit31:0]. 
In case of writing 
    An interrupt is generated immediately after 0 is written.    
    An interrupt is generated after 0 is written. 
In case of reading 
    Added A set value can be read.   
   Corrected . 
339  6.8. Hardware Watchdog Timer Value Register (WDG_VLR) 
   Corrected . 
344  CHAPTER 11 
Watchdog timer 
7. Notes 
  Added   Hardware watchdog and interrupt handler. 
   See the section for Interrupt Source Register in the chapter 
Clock for an interrupt source. 
    
See the section for Interrupt Source Register in the chapter 
Interrupt for an interrupt source. 
 
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\05028\051 
MB9Axxx/MB9Bxxx  Series