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Fujitsu Series 3 Manual

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4. Registers 
 
4.17.  IRQ31 Batch Read Register (IRQ31MON) 
IRQ31MON indicates all of the interrupt requests allocated to interrupt vector no. 47. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field BTINT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:16] Reserved: Reserved bits  Reads out 0. 
 
[bit15:0] BTINT: 
bit no.  bit  Description 
0 No IRQ1 interrupt request on the base timer ch. 7 15 
1 IRQ1 interrupt request on the base timer ch. 7 
0 No IRQ0 interrupt request on the base timer ch. 7 14 
1 IRQ0 interrupt request on the base timer ch. 7 
0 No IRQ1 interrupt request on the base timer ch. 6 13 
1 IRQ1 interrupt request on the base timer ch. 6 
0 No IRQ0 interrupt request on the base timer ch. 6 12 
1 IRQ0 interrupt request on the base timer ch. 6 
0 No IRQ1 interrupt request on the base timer ch. 5 11 
1 IRQ1 interrupt request on the base timer ch. 5 
0 No IRQ0 interrupt request on the base timer ch. 5 10 
1 IRQ0 interrupt request on the base timer ch. 5 
0 No IRQ1 interrupt request on the base timer ch. 4 9 
1 IRQ1 interrupt request on the base timer ch. 4 
0 No IRQ0 interrupt request on the base timer ch. 4 8 
1 IRQ0 interrupt request on the base timer ch. 4 
0 No IRQ1 interrupt request on the base timer ch. 3 7 
1 IRQ1 interrupt request on the base timer ch. 3 
0 No IRQ0 interrupt request on the base timer ch. 3 6 
1 IRQ0 interrupt request on the base timer ch. 3 
0 No IRQ1 interrupt request on the base timer ch. 2 5 
1 IRQ1 interrupt request on the base timer ch. 2 
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4. Registers 
 
bit no.  bit Description 
0 No IRQ0 interrupt request on the base timer ch. 2 4 
1 IRQ0 interrupt request on the base timer ch. 2 
0 No IRQ1 interrupt request on the base timer ch. 1 3 
1 IRQ1 interrupt request on the base timer ch. 1 
0 No IRQ0 interrupt request on the base timer ch. 1 2 
1 IRQ0 interrupt request on the base timer ch. 1 
0 No IRQ1 interrupt request on the base timer ch. 0 1 
1 IRQ1 interrupt request on the base timer ch. 0 
0 No IRQ0 interrupt request on the base timer ch. 0 0 
1 IRQ0 interrupt request on the base timer ch. 0 
If DMA transfer requests are selected by the DRQS EL register, the corresponding BTINT bit is 0. 
  As shown in the Table 4-1 , base timer interrupt sources IRQ0 and IRQ1 differ depending on the base timer 
fu nction to
 be

 used. 
Table 4-1 Interrupt sources for each function of the base timer 
Function Interrupt Source IRQ0 Interrupt Source IRQ1 
16-bit PWM timer  Underflow detection/ 
duty match detection  Timer start trigger detection 
16-bit PPG timer 
Underflow detection Timer start trigger detection 
16/32-bit reload timer  Underflow detection Timer start trigger detection 
16/32-bit PWC timer  Overflow detection Measurement finished detection 
 
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4. Registers 
 
4.18.  IRQ32/33 Batch Read Register (IRQxxMON) 
IRQ32MON indicates all of the interrupt requests allocated to interrupt vector no. 48. 
IRQ33MON indicates all of the interrupt requests allocated to interrupt vector no. 49. 
IRQ32MON shows the status of  the interrupt request on the CAN ch. 0. 
IRQ33MON shows the status of  the interrupt request on the CAN ch. 1. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved CANINT
Attribute  R R R R R R  R R R R R R  R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:1] Reserved: Reserved bits  Reads out 0. 
 
[bit0] CANINT: 
bit Description 
0  No interrupt request on the corresponding CAN channel. 
1  Interrupt request on the corresponding CAN channel. 
 
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4. Registers 
 
4.19.  IRQ34 Batch Read Register (IRQ34MON) 
IRQ34MON indicates all of the interrupt requests allocated to interrupt vector no. 50. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved USB0INT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:5] Reserved: Reserved bits  Reads out 0. 
 
[bit4:0] USB0INT: 
bit no.  bit  Description 
0 No Endpoint 5 DRQ interrupt request on the USB ch. 0 4 
1 Endpoint 5 DRQ interrupt request on the USB ch. 0 
0 No Endpoint 4 DRQ interrupt request on the USB ch. 0 3 
1 Endpoint 4 DRQ interrupt request on the USB ch. 0 
0 No Endpoint 3 DRQ interrupt request on the USB ch. 0 2 
1 Endpoint 3 DRQ interrupt request on the USB ch. 0 
0 No Endpoint 2 DRQ interrupt request on the USB ch. 0 1 
1 Endpoint 2 DRQ interrupt request on the USB ch. 0 
0 No Endpoint 1 DRQ interrupt request on the USB ch. 0 0 
1 Endpoint 1 DRQ interrupt request on the USB ch. 0 
If DMA transfer requests are selected by the DR QSEL register, the corresponding USB0INT bit is 
0. 
 
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4. Registers 
 
4.20.  IRQ35 Batch Read Register (IRQ35MON) 
IRQ35MON indicates all of the interrupt requests allocated to interrupt vector no. 51. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved USB0INT 
Attribute  R R R R R R R R R R R R R R R R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:6] Reserved: Reserved bits  Reads out 0. 
 
[bit5:0] USB0INT: 
bit no.  bit  Description 
0 No status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0 5 
1 Status (SOFIRQ, CMPIRO) interrupt request on the USB ch. 0 
0 No status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on 
the USB ch. 0 
4 
1 Status (DIRQ, URIRQ, RWKIRQ, CNNIRQ) interrupt request on the 
USB ch. 0 
0 
No status (SPK) interrupt request on the USB ch. 0 3 
1 Status (SPK) interrupt request on the USB ch. 0 
0 No status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the 
USB ch. 0 
2 
1 Status (SUSP, SOF, BRST, CONF, WKUP) interrupt request on the 
USB ch. 0 
0 
No Endpoint 0 DRQO interrupt request on the USB ch. 0 1 
1 Endpoint 0 DRQO interrupt request on the USB ch. 0 
0 No Endpoint 0 DRQI interrupt request on the USB ch. 0 0 
1 Endpoint 0 DRQI interrupt request on the USB ch. 0 
 
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4. Registers 
 
4.21.  IRQ36/37 Batch Read Register (IRQxxMON) 
IRQ36MON indicates all of the interrupt requests allocated to interrupt vector no. 52. 
IRQ37MON indicates all of the interrupt requests allocated to interrupt vector no. 53. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15  0 
Field Reserved 
Attribute R 
Initial  value  0x0000 
 
[bit31:0] Reserved: Reserved bits  Reads out 0. 
 
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4. Registers 
 
4.22.  IRQ38/39/40/41/42/43/44/45 Batch Read Register (IRQxxMON) 
IRQ38MON indicates all of the interrupt requests allocated to interrupt vector no. 54. 
IRQ39MON indicates all of the interrupt requests allocated to interrupt vector no. 55. 
IRQ40MON indicates all of the interrupt requests allocated to interrupt vector no. 56. 
IRQ41MON indicates all of the interrupt requests allocated to interrupt vector no. 57. 
IRQ42MON indicates all of the interrupt requests allocated to interrupt vector no. 58. 
IRQ43MON indicates all of the interrupt requests allocated to interrupt vector no. 59. 
IRQ44MON indicates all of the interrupt requests allocated to interrupt vector no. 60. 
IRQ45MON indicates all of the interrupt requests allocated to interrupt vector no. 61. 
IRQ38MON shows the status of the interrupt request on the DMA controller ch.0. 
IRQ39MON shows the status of the interrupt request on the DMA controller ch.1. 
IRQ40MON shows the status of the interrupt request on the DMA controller ch.2. 
IRQ41MON shows the status of the interrupt request on the DMA controller ch.3. 
IRQ42MON shows the status of the interrupt request on the DMA controller ch.4. 
IRQ43MON shows the status of the interrupt request on the DMA controller ch.5. 
IRQ44MON shows the status of the interrupt request on the DMA controller ch.6. 
IRQ45MON shows the status of the interrupt request on the DMA controller ch.7. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved DMAINT
Attribute  R R R R R R RRR RRR R R R  R 
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
[bit31:1] Reserved: Reserved bits  Reads out 0. 
 
[bit0] DMAINT: 
bit Description 
0  No interrupt request on  the corresponding DMA controller channel. 
1 Interrupt request on  the corresponding DMA controller channel. 
 
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4. Registers 
 
4.23.  IRQ46/47 Batch Read Register (IRQxxMON) 
IRQ46MON indicates all of the interrupt requests allocated to interrupt vector no. 62. 
IRQ47MON indicates all of the interrupt requests allocated to interrupt vector no. 63. 
 
bit 31  16
Field Reserved 
Attribute R 
Initial  value  0x0000 
  bit 15  0 
Field Reserved 
Attribute R 
Initial  value  0x0000 
 
[bit31:0] Reserved: Reserved bits  Reads out 0. 
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5. Usage Warnings 
 FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: Interrupts 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  40  
5. Usage Warnings 
Be careful with the following points when using the interrupt controller. 
  The interrupt request signals from each of the peripheral resources ar e notified by level. When exiting 
from interrupt processing, always clear the interrupt request. 
 
   The NMIX pin is allocated shared with a general-purpo se port. The initial value after reset is released is 
configured as a general-purpose port, and the NMI input is masked. In order to use the NMI, enable NMI 
by configuring the port setting. See the chapter of  External Interrupt and NMI Control Unit for details. 
 
   See the chapters for each of the macros for the corre lation between the specific event detection registers 
and interrupt enable registers  in each peripheral resource. 
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