Fujitsu Series 3 Manual
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2. LIN Interface (Ver. 2.1) Interrupts Figure 2-3 ORE (Overrun Error) flag bit set timing Receive data RDRF ORE SP Precautions: If the next data is transferred before the receive data is read (RDRF=1), an overrun error occurs. ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 LIN break field detection flag (LBD) set timing If 0 is input for a width of 11 bits or more as Serial Input (SIN), the LBD bit is set to 1. If LIN break field interrupts are enabled (ESCR:LBIE = 1) then, a receive interrupt occurs. Figure 2-4 LBD (LIN Break field Detection) flag set timing Receive data (SIN) Sampling clock LBD The LBD is cleared by the CPU. LIN Break Sampling point... ... After 11 LOW state bits of the receive data ar e detected at falling edge of the sampling clock, an LIN Break is detected at a rising edge of the sampling clock. When an LIN Break is detected, the LBD bit is set to 1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 915 MB9Axxx/MB9Bxxx Series
2. LIN Interface (Ver. 2.1) Interrupts 2.2. Interrupt and flag set timi ng when receive FIFO is used If receive FIFO is used, an interrupt occurs when the FBYTE data (preset for the FBYTE register (FBYTE)) is received. Interrupt and flag set timing when receive FIFO is used If the receive FIFO is used, an interrupt occurs depending on the value set for the FBYTE register. When full FBYTE data is received, the receive data full flag (SSR:RDRF) of the Se rial Status register is set to 1. If receive interrupts are enabled (SCR:RI E) during this time, a receive interrupt occurs. If both of the following conditions are satisfied and if the receive idle state continues for more than 8 baud rate clocks, the interrupt flag (SSR:RDRF) is set to 1. The receive FIFO idle detection enable bit (FCR:FRIIE) is 1. The number of data sets stored in the recei ve FIFO does not reach the transfer count. If the RDR data is read during counting of 8 clocks, this counter is reset to 0 and counting for 8 clocks is restarted. If receive FIFO is disabl ed, this counter is reset to 0.If data remains in the receive FIFO and if receive FIFO is enabled, th e data counting is restarted. When the Receive Data Register (RDR) data is all read and receive FIFO is emptied, the receive data full flag (SSR:RDRF) is cleared. If the valid receive data amount is the same as the FI FO capacity and if the next data is received, an overrun error (SSR:ORE = 1) occurs. Figure 2-5 Receive interrupt occurrence timing when receive FIFO is used Receive data FIFOBYTE (Receive) RDRF 7th byte 9 An interrupt occurs when the FBYTE (receive data) count matches the receive data count. Data reading from RDR 8th byteCheck SumSTSPST SP STSP All receive data are read. Valid byte display 6 DATA FieldCheck Sum FieldSynch Break 78 0 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 916 MB9Axxx/MB9Bxxx Series
2. LIN Interface (Ver. 2.1) Interrupts Figure 2-6 ORE (Overrun Error) flag bit set timing Receive data FIFOBYTE (Receive) RDRF 62th byte 62 Precautions: If the FIFO capacity is displayed by the FBYTE and if the next data is received, an overrun error occurs. This figure shows that the 64 bytes of FIFO capacity are used. 63th byte 64th byte 65th byte STSPST SP ST SP ST SP ST66th byteSP 61 Valid byte display ORE An overrun error occurred. 62 63 64 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 917 MB9Axxx/MB9Bxxx Series
2. LIN Interface (Ver. 2.1) Interrupts 2.3. Transmit interrupt and flag set timing A transmit interrupt occurs when outgoing data is transferred from the Transmit Data Register (TDR) to the transmit shift register (SSR:TDRE = 1) and transmission starts and when no transmission is performed (SSR:TBI = 1). Transmit interrupt and flag set timing Transmit data empty flag (TDRE) set timing After data has been transferred from the Transmit Data Register (TDR) to the transmit shift register, the next data can be written in the TDR (SSR:TDRE=1). If transmit interrupts are enabled (SCR:TIE=1) during this time, a transmit interrupt occurs. As the TDRE b it is read only, the SSR:TDRE bit is cleared to 0 when data is written to the Transmit Data Register (TDR). Figure 2-7 Transmit data empty flag (SSR:TDRE) set timing Transmit data (Mode 0 or 1) TDRE Data writing in TDR ST D0 D1 D2 D3 A transmit interrupt occurred.A transmit interrupt occurred. D4 D5 D6 D7 SP ST D0 D1 D2 ST: Start bit D0 - D7: Da ta bits SP: Stop bit Transmit bus idle flag (TBI) set timing If the Transmit Data Register is empty (TDRE=1) and no data is transmitted, the SSR:TBI bit is set to 1. If transmit bus idle interrupts are enabled (SCR:TBIE=1) during this time, a transmit interrupt occurs. When outgoing data is written to the Transmit Data Register (TDR), both the TBI bit and the transmit interrupt request are cleared. Figure 2-8 Transmit bus idle flag (TBI) set timing Transmit data TBI Data writing in TDR ST ST: Start bit D0 - D7: Data bits SP: Stop bit A transmit interrupt by the TBI bit occurred. TDRE D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 918 MB9Axxx/MB9Bxxx Series
2. LIN Interface (Ver. 2.1) Interrupts 2.4. Interrupt and flag set timi ng when transmit FIFO is used When the transmit FIFO is used, an interrupt occurs if the FIFO contains no data. Transmit interrupt and flag set ti ming when transmit FIFO is used If the transmit FIFO contains no data, the FIFO tran smit data request bit (FCR1:FDRQ) is set to 1. If FIFO transmit interrupts are enabled (FCR1:FTIE=1), a transmit interrupt occurs. If a transmit interrupt has occurred and you have written the required data in transmit FIFO, clear the interrupt request by setting the FIFO transmit data request bit (FCR1:FDRQ) to 0. When transmit FIFO is filled with data, the FIFO transmit data request bit (FCR1:FDRQ) is set to 0. To check to see if transmit FIFO contains any da ta, read from the FIFO Byte Register (FBYTE). If FBYTE=0x00, no data exists in the transmit FIFO. Figure 2-9 Transmit interrupt occurrence timing when transmit FIFO is used Transmit data FIFOBYTE FDRQ 2 A transmit interrupt occurred. (*1) Data writing in transmit FIFO 1st byte 2nd byte 3rd byteST SP ST SP ST SP ST4th byteSPSP 0 11021 Cleared if set to 0. TDRE 5th byte 10 The Transmit Data Register is empty. *2 Cleared if set to 0. *1) The FDRQ bit is set to 1 as transmit FIFO is empty. *2) The TDRE bit is set to 1 as transmit FIFO and the Transmit Buffer Register contain no data. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 919 MB9Axxx/MB9Bxxx Series
3. Dedicated Baud Rate Generator 3. Dedicated Baud Rate Generator For the LIN interface (ver. 2.1) transmitting/receiving clock source, either of the following can be selected. - Dedicated baud rate generator (reload counter) - An external clock input to the baud rate generator (reload counter) LIN interface (ver. 2.1) baud rate Select one of the following two baud rates. Baud rate obtained by dividing an internal clock using the dedicated baud rate generator (reload counter) This generator provides two internal reload counters, which support transmitting and receiving serial clocks respectively. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). Each reload counter divides an internal clock by the set value. To set the clock source, select an internal clock (SMR:EXT = 0). Baud rate obtained by dividing an ext ernal clock using the dedicated baud rate generator (reload counter) Use an external clock for the clock source of the reload counter. To select the baud rate, specify the 15-bit reload value using Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). Each reload counter divides an external clock by the set value. To set the clock source, select use of an external clock and the baud rate generator clock (SMR:EXT = 1). This mode is designed for cases where an oscillato r with a divided non-standard frequency is used. Set t h e external clock (EXT = 1) while the reload counter is stopped (BGR1/0 = 15h00). If an ex t ernal clock is selected (EXT = 1), its HIGH and LOW signals must have a width at least of two bus clocks. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 920 MB9Axxx/MB9Bxxx Series
3. Dedicated Baud Rate Generator 3.1. Baud rate settings The following explains how to set the baud rate, and also a result of serial clock frequency calculation. Calculating the baud rate Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0). The baud rate is obtained in the following formulas. (1) Reload value (2) Calculation example To set the 16 MHz bus clock, to use the internal clock, and to set the 19200-bps baud rate, set the reload value as follows. Reload value: V =(16x1000000)/19200 - 1=832 Therefore, the baud rate is: b =(16x1000000)/(832 + 1) =19208bps (3) Baud rate error The baud rate error can be obta ined from the following equation. Error (%) = (Calculated value - Target value)/Target value x 100 Example: To set the 20 MHz bus clock and 153600-bps target baud rate: Reload value = (20 x 1000000)/153600 - 1 = 129 Baud rate (Calculated value) = (20 x 1000000)/(129 + 1) = 153846 (bps) Error (%) = (153846 - 153600)/153600 x 100 = 0.16 (%) V = / b - 1 V : Reload value b: Baud rate : Bus clock frequency or external clock frequency If th e reload value is set to 0, the reload counter is stopped. If the rel o ad value is even, the LOW signal width of serial clock is longer than the HIGH signal width for a single cycle of bus clock. If the valu e is odd, the serial clock has the same HIGH and LOW signal width. Set the reload value to 3 or more. Note that data may not be received normally due to the baud rate error and reload value setting. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 921 MB9Axxx/MB9Bxxx Series
3. Dedicated Baud Rate Generator Reload value and baud rate for each bus clock frequency Table 3-1 Reload values and baud rates 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32MHz Baud rate (bps) Value ERRValue ERR ValueERRValueERRValueERR Value ERR 8M - - - - - - - - - - - 0 6M - - - - - - - - - - - - 5M - - - - - - - - - - - - 4M - - - - - - 4 0 5 0 7 0 2.5M - - 3 0 - - - - - - - - 2M 3 0 4 0 7 0 9 0 11 0 15 0 1M 7 0 9 0 15 0 19 0 23 0 31 0 500000 15 0 19 0 31 0 39 0 47 0 63 0 460800 - - - - - - - - 51 -0.16 - - 250000 31 0 39 0 63 0 79 0 95 0 127 0 230400 - - - - - - - - 103 -0.16 - - 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 207 -0.16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 68 -0.64 86 0.22 138 0.08173 0.22 207 -0.16 277 0.08 76800 103 -0.16 129 -0.16 207 -0.16 259 -0.16 311 -0.16 416 0.08 57600 138 0.08 173 0.22 277 0.08 346 -0.16 416 0.08 555 0.08 38400 207 -0.16259 -0.16 416 0.08 520 0.03 624 0 832 -0.04 28800 277 0.08 346
3. Dedicated Baud Rate Generator Allowable baud rate range for data reception The following shows the ra nge of baud rate error allowed fo r the destination to receive data. Set the reception baud rate error by using the following formulas to ensure that the value falls within the allowable range. Figure 3-1 Allowable baud rate range for data reception FUJITSU SEMICONDUCTOR LIMITED LIN trans fer rate Start Sampling Allowable minimum transfer rate FL Single data frame (10xFL ) bit7 bit 6 bit 0bit 1 Start FLmin Allowable maximum transfer rate bit7 bit 6 bit 1 bit 0 Start Stop Stop Stopbit7 bit 6 bit 1 bit 0 Flmax As shown in the figu re, after detection of the start b it, the sampling timing of incoming data is determined by the counter set in the BGR1/0 register. Data can be received successfully if the bit sequence including the stop bit matches the sampling timing. If this applies to a reception of 10 bits, a theoretical explanation can be given in the following. Assuming that the sampling timing margin is one bus clock ( ), the minimum allowable transfer rate (FLmin) is determined as follows: FLmin = (10bit x (V+1) – (V+1)/2 + 2)/ = (19V + 23)/2 (s) V: Reload value, : Bus clock Thus, the maximum baud rate that allows the destination to receive data (BGmax) is determined as follows. BGmax = 10/FLmin = 20 /(19V+23) (bps) V: Reload value, : Bus clock When data is received at the maximum allowable transfer rate (FLmax), the starting point of the incoming 10th bit is sampled. Thus, the maximum allowable transfer rate (FLmax) is determined as follows: 9/10×Flmax = (10bit x (V+1) – (V+1)/2 )/ V: Reload value, : Bus clock Flmax = (19/18 x 10 x (V+1)/ Assuming that the sampling timing margin ( ) is two clocks, the maximum allowable transfer rate (Flmax) is determined as follows: 9/10×Flmax = (10bit x (V+1) – (V+1)/2 – 2)/ V: Reload value, : Bus clock Flmax = (19/18 x 10 x (V+1) – 40/18)/ = (190V + 150)/20 (s) V: Reload value, : Bus clock Accordingly, the minimum baud rate that allows the de stination to receive data (BGmin) is determined as follows: BGmin = 10/FLmax = 18 /(19V+15) (bps) V: Reload value, : Bus clock CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 923 MB9Axxx/MB9Bxxx Series
3. Dedicated Baud Rate Generator From the above formulas that yields the minimum/maximum baud rates, the allowable baud rate errors between the LIN interface (ver. 2.1) an d the destination can be obtained as shown in the following table. Reload value (V)Maximum allowable baud rate error Minimum allowable baud rate error 3 0% 0 10 +3.28% -3.41% 50 +4.83% -4.87% 100 +5.04% -5.07% 200 +5.15% -5.16% 32767 +5.26% -5.26% Receive accura cy depends on the number of bits per fra me, bus clock, and reloa d value. The higher the bus clock and frequency division ratio are, the higher the accuracy becomes. External clock Writing 1 to the EXT bit of the Baud Rate Generator Register (BGR) causes the baud rate generator to divide the external clocks frequency. The ex ternal cl ock signal is synchr onized with the internal cl ock on the LIN interface (ver. 2.1). Therefore, an external clock that does not allow sy nchronization causes unstable operation. Functions of reload counter There are two types of reload counte rs: The transmit reload counter and the receive reload counter, both functioning as a dedicated baud rate generator. Each reload counter consists of a 15-bit register for the reload value, and generates transmitting and receiving clocks from the external or internal clock. Starting counting When the reload value is written to the Baud Rate Ge nerator Register (BGR1 or BGR0), the reload counter starts counting. Restarting The reload counter restarts counting in the following conditions. Common to transmit and receive reload counters A programmable reset (SCR:UPCL bit) Receive reload counter Detection of the start bits falling edge in asynchronous mode FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-4: LIN Interface \050Ver. 2.1\051 \050LIN Communication Control Interface Ver. 2.1\051 MN706-00002-1v0-E 924 MB9Axxx/MB9Bxxx Series