Fujitsu Series 3 Manual
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5. Register
5.1. Load Register (TimerXLoad) X=1 or 2
Load Register (TimerXLoad) has a start value to decrement the counter in 32-bit Register.
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXLoad[31:16]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial
value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field TimerXLoad[15:0]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/W R/W
Initial
value 0 0 0...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-393.png "Page 394
5. Register
5.1. Load Register (TimerXLoad) X=1 or 2
Load Register (TimerXLoad) has a start value to decrement the counter in 32-bit Register.
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXLoad[31:16]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial
value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field TimerXLoad[15:0]
Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/W R/W
Initial
value 0 0 0...")
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5. Register
5.2. Value Register (TimerXValue) X=1 or 2
Value Register (TimerXValue) indicates the current value of the decrement counter in 32-bit
Read Only Register.
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXValue[31:16]
Attribute R R R R R R R R R R R R R R R R
Initial
value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field TimerXValue[15:0]
Attribute R R R R R R R R R R R R R R R R
Initial
value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-394.png "Page 395
5. Register
5.2. Value Register (TimerXValue) X=1 or 2
Value Register (TimerXValue) indicates the current value of the decrement counter in 32-bit
Read Only Register.
bit 31 30 29 28 27 2625242322212019 18 1716
Field TimerXValue[31:16]
Attribute R R R R R R R R R R R R R R R R
Initial
value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field TimerXValue[15:0]
Attribute R R R R R R R R R R R R R R R R
Initial
value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...")
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5. Register
5.3. Control Register (TimerXControl) X=1 or 2
Control Register (TimerXControl) controls the Timer.
bit 31 30 29 28 27 2625242322212019 18 1716
Field Reserved
Attribute - - - - - - - - - - - - - - - -
Initial
value X X X X X X X X X X X X X X X X
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field Reserved Timer
En Timer
Mode
Int
EnableReser ved TimerPre Timer
Size One
Shot
Attribute - - - - - - - - R/W
Initial
value X X X X X X X X 0 0 1 0 0 0 0 0
[bit31:8]...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-395.png "Page 396
5. Register
5.3. Control Register (TimerXControl) X=1 or 2
Control Register (TimerXControl) controls the Timer.
bit 31 30 29 28 27 2625242322212019 18 1716
Field Reserved
Attribute - - - - - - - - - - - - - - - -
Initial
value X X X X X X X X X X X X X X X X
bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0
Field Reserved Timer
En Timer
Mode
Int
EnableReser ved TimerPre Timer
Size One
Shot
Attribute - - - - - - - - R/W
Initial
value X X X X X X X X 0 0 1 0 0 0 0 0
[bit31:8]...")
4. Setting Procedure Example 4. Setting Procedure Example This chapter describes an example of the Dual Timer setting procedure. Dual Timer Setting Procedure Flow Figure 4-1 Periodic Mode Setting Procedure Example FUJITSU SEMICONDUCTOR LIMITED Start setting // Register setting example Interrupt source clear // TimerXIntClr =0xF FFF FFFF Timer mode setting Counter size setting Prescaler setting Interrupt enable // Mode: Periodic Mod e // Size: 32bit counter // Prescaler: divided by 1 // Interrupt enable TimerXControl =0x0000 0062 End Timer interval setting // 1ms interval setting@TIMCLK=40MHz TimerXLoad=0x00009C40 Enable setting // TimerXCont rol:TimerEn=1 Start the down count from the timer interval setting value CHAPTER 12: Dual Timer MN706-00002-1v0-E 355 MB9Axxx/MB9Bxxx Series
4. Setting Procedure Example Timer Interval Setting Expressions of the timer interval calcula tions in respective modes are shown in Table 4-1: Table 4-1 Expression for Timer Interval Calculation Mode Timer Interval 32-bit Free-running (PRESCALEDIV / TIMCLKFREQ) 232 16-bit Free-running (PRESCALEDIV / TIMCLKFREQ) 216 Periodic & One-shot (PRESCALEDIV / TIMCLKFREQ) TimerXLoad TIMCLK FREQ is the timer clock (TIMCLK) frequency. PRESCALE DIV is the prescaler division factor of 1, 16, or 256 configured by bit [3:2] of the Control Register (TimerXControl). TimerXLoad is the value of the Load Register (TimerXLoad). For example, in the case of TIMCLK=40MHz and PRESCALE DIV=1, the value of the Load Register (TimerXLoad) to configure 1ms timer interval can be calculated as follows: TimerXLoad = Timer interval TIMCLK FREQ / PRESCALEDIV = 1ms 40MHz / 1 = 4 10 4 = 0x00009C40 The mi nim um valid value of the Load Register (TimerXLoad) is 1. If the Load Reg ister is set to 0, an interrupt will be immediately generated. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 356 MB9Axxx/MB9Bxxx Series
5. Register 5. Register This chapter describes the structures and functions of the registers used in Dual Timer. Dual Timer Register List Abbreviation Register Name See Timer1Load Timer1 Load Register 5.1 Timer1Value Timer1 Value Register 5.2 Timer1Control Timer1 Control Register 5.3 Timer1IntClr Timer1 Interrupt Clear Register 5.4 Timer1RIS Timer1 Interrupt Status Register 5.5 Timer1MIS Timer1 Masked Interrupt Status Register 5.6 Timer1BGLoad Timer1 Background Load Register 5.7 Timer2Load Timer2 Load Register 5.1 Timer2Value Timer2 Value Register 5.2 Timer2Control Timer2 Control Register 5.3 Timer2IntClr Timer2 Interrupt Clear Register 5.4 Timer2RIS Timer2 Interrupt Status Register 5.5 Timer2MIS Timer2 Masked Interrupt Status Register 5.6 Timer2BGLoad Timer2 Background Load Register 5.7 FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 357 MB9Axxx/MB9Bxxx Series
5. Register 5.1. Load Register (TimerXLoad) X=1 or 2 Load Register (TimerXLoad) has a start value to decrement the counter in 32-bit Register. bit 31 30 29 28 27 2625242322212019 18 1716 Field TimerXLoad[31:16] Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field TimerXLoad[15:0] Attribute R/W R/W R/W R/W R/W R/W R/WR/W R/WR/WR/W R/W R/W R/W R/W R/W Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 [bit31:0] TimerXLoad : Timer X Load bit When a value is directly written to this register, the current count is immediately set to a new value at the next timer clock. Also, in Periodic Mode setting, this value is used for reloading the counter when the current count reaches zero. In addition, the value in this register is also overw ritten when the Background Register (TimerXBGLoad) is written. However, in this case, the curre nt count is not immediately affected. After either the Load Register or the Background Re gister is written, the register value written last is returned at any reading. In other words, the same value is read from both of the Load Register and the Background Register, and the value is always reloaded after the counter reaches zero in Periodic Mode. The mi nim um valid value of the Load Register (TimerXLoad) is 1. If the Load Reg ister is set to 0, an interrupt will be immediately generated. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 358 MB9Axxx/MB9Bxxx Series
5. Register 5.2. Value Register (TimerXValue) X=1 or 2 Value Register (TimerXValue) indicates the current value of the decrement counter in 32-bit Read Only Register. bit 31 30 29 28 27 2625242322212019 18 1716 Field TimerXValue[31:16] Attribute R R R R R R R R R R R R R R R R Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field TimerXValue[15:0] Attribute R R R R R R R R R R R R R R R R Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 [bit31:0] TimerXValue : Timer X Value bit After a load operation which a new load value is writte n to the Load Register (TimerXLoad), the new load value is reflected immediately to th is Value Register (TimerXValue). In 16-b it tim er mode, the most significant 16 bits of 32-bit Value Register (Tim erXV alue) are not automatically set to 0. For example, when no writing to the Load Register (TimerXLoad) has occurred yet since the change in the Timer from 32-bit mode to 16-bit mode, the most significant 16 bits of the Value Register have non-zero values. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 359 MB9Axxx/MB9Bxxx Series
5. Register 5.3. Control Register (TimerXControl) X=1 or 2 Control Register (TimerXControl) controls the Timer. bit 31 30 29 28 27 2625242322212019 18 1716 Field Reserved Attribute - - - - - - - - - - - - - - - - Initial value X X X X X X X X X X X X X X X X bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field Reserved Timer En Timer Mode Int EnableReser ved TimerPre Timer Size One Shot Attribute - - - - - - - - R/W Initial value X X X X X X X X 0 0 1 0 0 0 0 0 [bit31:8] Reserved : Reserved bit Writing No effect on operation Reading Value not determined [bit7] TimerEn : Enable bit bit Description 0 Timer disabled [Initial value] 1 Timer enabled [bit6] TimerMode : Mode bit bit Description 0 Free-running Mode [Initial value] 1 Periodic Mode [bit5] IntEnable : Interrupt enable bit bit Description 0 Interrupt disabled 1 Interrupt enabled [Initial value] [bit4] Reserved : Reserved bit Writing No effect on operation Reading Value not determined FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 360 MB9Axxx/MB9Bxxx Series
5. Register [bit3:2] TimerPre : Prescale bit bit3 bit2 Description 0 0 Clock divided by 1 [Initial value] 0 1 Clock divided by 16 1 0 Clock divided by 256 1 1 Undefined, do not use [bit1] TimerSize : Counter size bit Select 16/32-bit counter operation. bit Description 0 16-bit counter [Initial value] 1 32-bit counter [bit0] OneShot : One-shot mode bit Select One-shot Mode or Counter Wrapping Mode (Free-running Mode/Periodic Mode). Based on Mode bit (TimerMode) settings, Free-running Mode or Periodic Mode is selected. bit Description 0 Wrapping Mode (Free-running Mo de/Periodic Mode) [Initial value] 1 One-shot Mode The co unt er mode, size, or prescale settings must not be changed while the Timer is running. To configure a new setting, the T i mer needs to be disabled first and that a new setting value needs to be written to respective registers. Then, after the setting is changed, the Timer needs to be enabled again. Failure to follow this setting procedure can result in unpredictable behaviors of the device. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 361 MB9Axxx/MB9Bxxx Series
5. Register 5.4. Interrupt Clear Register (TimerXIntClr) X=1 or 2 Interrupt Clear Register (TimerXIntClr) clears an interrupt. bit 31 30 29 28 27 2625242322212019 18 1716 Field TimerXIntClr[31:16] Attribute W W W W W WWWWWWWW W WW Initial value X X X X X X X X X X X X X X X X bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field TimerXIntClr[15:0] Attribute W W W W W WWWWWWWW W WW Initial value X X X X X X X X X X X X X X X X [bit31:0] TimerXIntClr : Interrupt clear bit Writing any value to this register clears an interrupt output from the counter. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 362 MB9Axxx/MB9Bxxx Series
5. Register 5.5. Interrupt Status Register (TimerXRIS) X=1 or 2 Interrupt Status Register (TimerXRIS) indicates an unmasked and raw interrupt status. bit 31 30 29 28 27 2625242322212019 18 1716 Field Reserved Attribute - - - - - - - - - - - - - - - - Initial value X X X X X X X X X X X X X X X X bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field Reserved Timer XRIS Attribute - - - - - - - - - - - - - - - R Initial value X X X X X X X X X X X X X X X 0 [bit31:1] Reserved : Reserved bit Writing No effect on operation Reading Value not determined [bit0] TimerXRIS :Interrupt Status Register bit bit Description 0 No interrupt generated from the counter [Initial value] 1 Interrupt generated from the counter FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 363 MB9Axxx/MB9Bxxx Series
5. Register 5.6. Masked Interrupt Status Register (TimerXMIS) X=1 or 2 Masked Interrupt Status Register (TimerXMIS) indicates the masked interrupt status. bit 31 30 29 28 27 2625242322212019 18 1716 Field Reserved Attribute - - - - - - - - - - - - - - - - Initial value X X X X X X X X X X X X X X X X bit 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 Field Reserved Timer XMIS Attribute - - - - - - - - - - - - - - - R Initial value X X X X X X X X X X X X X X X 0 [bit31:1] Reserved : Reserved bit Writing No effect on operation Reading Value not determined [bit0] TimerXMIS : Masked Interrupt Status bit This bit is a logical AND value of the Raw Interrupt Status and the Timer Interrupt Enable bit of the Control Register (TimerXControl). The same value as this bit is connected to the interrupt output signal. bit Description 0 No interrupt generated from the counter 1 Interrupt generated from the counter [Initial value] FUJITSU SEMICONDUCTOR LIMITED CHAPTER 12: Dual Timer MN706-00002-1v0-E 364 MB9Axxx/MB9Bxxx Series