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    							FUJITSU SEMICONDUCTOR LIMITED 
4.1.  Enable Interrupt Request Register [ENIR] 
The ENIR is used to control masking an external interrupt request output. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field EN15 EN14 EN13 EN12 EN11 EN10 EN9EN8EN7EN6EN5EN4EN3 EN2 EN1EN0
Attribute R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Register functions 
[bit15:0] EN15 to EN0: External interrupt enable bit 
Bits EN15 to EN0 correspond to pins INT15 to INT00. 
It is not possible to set the bit corresponding to a pin that is not defined in the model specifications. 
Bit15:0 Description 
0  Disables the output of an external interrupt request. 
1 Enables the output of an external interrupt request. 
 
This function enables the interrupt request output corresp onding to the bit that is set to 1 in this register, 
and outputs a request to the interrupt controller. The pin corresponding to the bit that is set to 0 holds an 
interrupt cause, but outputs no request to the interrupt controller. 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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    							FUJITSU SEMICONDUCTOR LIMITED 
4.2.  External Interrupt Request Register [EIRR] 
The EIRR indicates that an external interrupt request is detected. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field ER15 ER14 ER13 ER12 ER11 ER10 ER9ER8ER7ER6ER5ER4ER3 ER2 ER1ER0
Attribute R R R R R R  R R R R R R  R R R R 
Initial 
value  X X X X X X X X X X X X X X X X 
 
  Register functions 
[bit15:0] ER15 to ER0: External interrupt request detection bit 
Bits ER15 to ER0 correspond to pins INT15 to INT00. 
The bit corresponding to a pin that is not defined in the model specifications is indefinite. 
Bit15:0 Function 
0  Detects no external interrupt request. 
1 Detects an external interrupt request. 
During writing No effect 
 
 
  When  lev

el detection is set with ELVR and while valid level is input from INTxx pin, clearing applicable 
bit (write 0) with  th

e External Interrupt Clear register (EICL) will  reset 1 to applicable bit in the 
External Interrupt Request Register (EIRR). 
   As the initial values of GPIO are set to general pur pose ports, applicable bit in the External Interrupt 
Request Register (EIRR) may be set to 1. After  set the GPIO to external interrupt pin, clear the 
External Interrupt Request Register (EIRR). 
 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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    							FUJITSU SEMICONDUCTOR LIMITED 
4.3.  External Interrupt Clear Register [EICL] 
The EICL is used to clear the held interrupt cause. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field  ECL 
15  ECL 
14  ECL
13 ECL 
12  ECL 
11  ECL
10 ECL
9  ECL
8  ECL
7  ECL
6  ECL
5  ECL
4  ECL 
3  ECL 
2  ECL
1  ECL
0 
Attribute  R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 
 
  Register functions 
[bit15:0] ECL15 to ECL0: Exter nal interrupt cause clear bit 
Bits ECL15 to ECL0 correspond  to pins INT15 to INT00. 
It is not possible to write 0 to the bit corresponding to a pin that is not defined in the model specifications. 
Bit15:0 Function 
When 0 is written  Clears an external interrupt cause. 
When 1 is written  No effect 
During reading Always reads 1. 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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4.4.  External Interrupt Level Register [ELVR] 
The ELVR is used to select the level or edge of the signal detected as an external interrupt 
request. 
 Register configuration 
 
bit 31 30 2928 27 2625242322212019 18 17 16
Field LB15 LA15 LB14 LA14 LB13 LA13LB12LA12LB11LA11LB10LA10LB9 LA9 LB8LA8
Attribute  R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
  bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field LB7 LA7 LB6LA6 LB5 LA5LB4 LA4LB3LA3LB2LA2LB1 LA1 LB0LA0
Attribute R/W R/W R/WR/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/W R/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
  Register functions 
[bit31:0] LA15 to LA0 or LB15 to LB0: External  interrupt request detection level selection bit 
Bits LA15 to LA0 or LB15 to LB0 correspond to pins INT15 to INT00 on a 2-bit (LA and LB) basis. 
It is not possible to set the bit corresponding to a pin that is not defined in the model specifications. 
If the edge or level selected with this bit is detected , it is recognized as an external interrupt request. 
LBx LAx Description 
0 0 Detects the L level. 
0  1 Detects the H level. 
1  0 Detects the rising edge. 
1  1 Detects the falling edge. 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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4.5.  Non Maskable Interrupt Request Register [NMIRR] 
The NMIRR Register indicates that a non maskable interrupt (NMI) request is detected. 
 Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved NR0
Attribute -  R 
Initial 
value  - 0 
 
  Register functions 
[bit15:1] Reserved: Reserved bits 
Bits 7 to 1 are indefinite in read mode. 
They have no effect in write mode. 
[bit0] NR: NMI request detection bit  The NR bit corresponds to pin NMIX. 
Bit Function 
0  Detects no NMI request. 
1 Detects an NMI request. 
During writing No effect 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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4. Registers 
 
FUJITSU SEMICONDUCTOR LIMITED 
Chapter: External Interrupt and NMI Control Sections 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  17 
4.6.  Non Maskable Interrupt Clear Register [NMICL] 
The NMICL Register is used to clear the held interrupt cause. 
  Register configuration 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field Reserved NCL0
Attribute -  R/W
Initial 
value  - 1 
 
  Register functions 
[bit15:1] Reserved: Reserved bits 
Bits 7 to 1 are indefinite in read mode. 
They have no effect in write mode. 
[bit0] NCL: NMI interrupt cause clear bit  The NCL bit corresponds to pin NMIX. 
Bit Function 
When 0 is written  Clears an NMI interrupt cause. 
When 1 is written No effect 
During reading Always reads 1. 
 
 
   If ELVR is rewritten to change the detection condition, an invalid interrupt cause may occur. 
To avoid an invalid interrupt cause from occurring, keep the procedure shown in  Figure 3-1 when 
changing the detection condition. 
   To  

detect the edge or level specified in ELVR, at leas t 3T (T: PCLK cycle) is required as the pulse width. 
If a signal that does not satisfy the pulse width is input,  it is not guaranteed that correct operations will be 
carried out. 
   When level detection is specified in ELVR, the corresponding bit in the External Interrupt Request 
Register (EIRR) is set to 1 again while the eff ective level is input from pin INTxx even if the 
corresponding bit is cleared (set  to 0) with the External Interrupt Clear Register (EICL). 
   The NMI detection level setting register is not provide d. In normal mode, the falling edge is detected. 
This register is used to return from stop mode when the L level is detected. 
   NMI is targeted for non maskable interrupt, so an NMI Enable Interrupt Request Register is not 
provided. 
 
 
CHAPTER  7: External  Interrupt  and NMI  Control  Sections 
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    							    1. Overview of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHA PTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   2 
CHAPTER: DMAC 
This chapter describes DMAC.  
 
1.
 Overview of DMAC 
2. Configuration of DMAC 
3. Functions and Operations of DMAC 
4. DMAC Control 
5. Registers of DMAC 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
CODE: 9BFDMAC -E01. 2_MHDMAC -E01.0 
CHAPTER  8: DMAC 
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    							    1. Overview of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   3 
1. Overview of DMAC   
DMAC (Direct  Memory Access  Controller)  is a  function block that transfers data  at high speed  
without CPU.  Using DMAC improves the system performance.  
 Overview of DMAC  
⋅  DMAC has its own bus which is independent from the CPU bus; therefore, it allows for transfer 
operati on even when the CPU bus is accessed.  
⋅   It consists of 8 channels enabled to execute 8 types of different DMA transfers independently from one 
another.  
⋅   It can set the address of the transfer destination, the address of the transfer source, the size of transf er 
data, the source of transfer request, and control the start of transfer operation, the forced termination of 
transfer and the pause of transfer for each channel.  
⋅   It can control the batch start of transfers, the forced batch termination of transfers and the batch pause of 
transfers for all of the channels.  
⋅   When multiple channels are operating simultaneously, it can select the priority of such channel 
operations from the fixed method or the rotated method.  
⋅   It supports hardware DMA transfer using an interru pt signal from Peripherals. 
⋅   It complies with the system bus (AHB) , supporting 32-bit address space (4Gbyte).  
 Overview of Functions of Each Channel  
⋅  The addresses of the transfer source and transfer destination can be incremented or fixed.  
⋅   Reload function fo r the addresses of the transfer source and transfer destination (i.e. function to return 
the values to the original settings upon completion of the transfer) is available.  
⋅   The size of data to be transferred can be selected from the following three specifications:  
Transfer data width   : (Select from byte/half -word/word)  
Setting the number of blocks   : (Select from 1 to 16)  
Setting the number of transfers  : (Select from 1 to 65536 ) 
(For information about the difference between the number of blocks and the numbe r of transfers, see 
"3  Functions and Operations of DMAC ".)  
⋅   Whether or not to give notification of the successful completion of transfer and unsuccessful completion 
of transfer can be specified. 
⋅   Transfe r mode can be selected from the following five types:  
Software -Block transfer  
Software -Burst transfer  
Hardware- Demand transfer  
Hardware- Block transfer  
Hardware- Burst transfer  
 Transfer Modes  
Software transfer is a method used to start DMAC by direct instruction from CPU.  
Hardware transfer is a method using an interrupt signal from a Peripheral as the DMAC transfer request 
signal to start DMAC directly when the Peripheral issues a transfer request.  
Multifunction serial unit, USB unit and ADC unit directly instruct DMAC to start data transfer, when 
sending/receiving data or AD conversion data needs to be transferred. External interrupt unit and B ase timer 
unit directly instruct DMAC to start data transfer at a transfer timing. In either of the cases, data can b e 
transferred without CPU by making such setting beforehand.  
 Abbreviations  
This chapter contains the following terms: DE , DS,  DH,  PR,  EB,  PB,  ST,  IS,  BC,  TC,  MS,  T W,  FS,  FD,  RC,  
RS,  RD,  EI,  CI, SS,  EM . All of these terms refer to each bit of DMAC control r egisters (DMACR, 
DMACSA,  DMACDA,  DMACA,  DMACB ). See "5  Registers of DMAC". 
CHAPTER  8: DMAC 
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    							    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   4 
2. Configuration of DMAC  
This chapter describes the system configuration of DMAC and the I/O pins of DMAC.  
 
2.1 DMAC and System Configuration  
2.2  I/O Signals of DMAC  
 
CHAPTER  8: DMAC 
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    							    2. Configuration of DMAC  FUJITSU SEMICONDUCTOR LIMITED 
CHAPTER: DMAC  
FUJITSU SEMICONDUCTOR CONFIDENTIAL   5 
2.1. DMAC and System Configuration 
This section describes DMAC and its system configuration.  
 Block Diagram  
Figure 2-1 shows a diagram of DMAC and its system configuration.  
Figure 2-1 Block Diagram of DMAC and System Configuration  
 
DMAC and System block diagram 
DRQSEL
IDREQ[31:0]
DMAC
ch0
ch1
ch2
ch3
ch4
ch5
ch6
ch7
Channel priority control
DMAC system bus (AHB/Peripheral)
Peripheral
( Hardware DMA available )
CPU
Peripheral
( Hardware DMA unavailable )
Flash
NVIC
Interrupt　sig.
DMA transfer request sig.
CPU system bus (AHB/Peripheral)
RAM
  
 
CHAPTER  8: DMAC 
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