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7. UART (Async Serial Interface) Registers 
 
[bit 9] TDRE: Transmit data empty flag bit   This flag shows the state of  Transmit Data Register (TDR). 
   If transmit data is written in the TDR, this bit is set to 0 to indicate that the TDR contains valid data. 
When data is loaded to the transmit shift register and  when the transmission is started, this bit is set to 
1 to indicate that the TDR does not have the valid data. 
   If the TDRE bit and SCR:TIE bit are 1,  a transmit interrupt request is output. 
   When the UPCL bit of the Serial Control Register (S CR) is set to 1, the TDRE bit is set to 1. 
   For the TDRE bit set/reset timing wh en transmit FIFO is used, see 2.4 Interrupt and flag set timing when 
trans mit FIFO is used
. 
 
Bit Description 
0  The Transmit Data Register (TDR) contains data. 
1  The Transmit Data Register is empty. 
 
[bit 8] TBI: Transmit bus idle flag    This bit indicates that UART is not transmitting data. 
   When transmit data is written in the Transmit Data Register (TDR), this bit is set to 0. 
   If the Transmit Data Register is empty (TDRE=1) and not transmitting data, this bit is set to 1. 
   When the UPCL bit of the Serial Control Register (SCR) is set to 1, the TBI bit is set to 1. 
   If this bit is 1 and if the transmit bus idle interrupt is enabled (SCR:TBIE=1), a transmit interrupt 
request is output. 
 
Bit Description 
0 During  data transmission 
1  No data transmission 
 
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7. UART (Async Serial Interface) Registers 
 
7.4.  Extended Communication Control Register (ESCR) 
The Extended Communication Control Register (ESCR) is used to set a transmit/receive data 
length, enable/disable a parity bit, select a parity bit, invert the serial data format and set stop 
bit length selection. 
 bit 15 ... 8 7 6 5 4 3 2 1 0 
Field (SSR) FLWEN ESBLINV PEN P L2 L1 L0 
Attribute     R/W R/W R/W  R/W R/W R/W R/W R/W 
Initial 
value     0 0 0 0 0 0 0 0 
 
[bit 7] FLWEN: Flow control enable bit  Selects to enable or disable ha rdware flow control operation. 
   If set to 0, hardware flow control is disabled. 
   If set to 1, hardware flow control is enabled. 
 
Bit Description 
0  Disables hardware flow control. 
1  Enables hardware flow control. 
 
 
  Set this b it when

 data transmission and  reception 
 is disabled (SCR:TXE=0, RXE=0). 
   Set this bit to 1 only when hardware flow control is desired.   
 
[bit 6] ESBL: Extension stop bit length select bit  This bit sets a stop  b

it length (the frame end mark of the transmit data). 
If set to SBL=0 and ESCR:ESBL=0, the stop bit length is set to one bit. 
If set to SBL=1 and ESCR:ESBL=0, the stop bit length is set to two bits. 
If set to SBL=0 and ESCR:ESBL=1, the stop bit length is set to three bits. 
If set to SBL=1 and ESCR:ESBL=1, the  stop bit length is set to four bits. 
Bit Description 
SMR.SBL=0 1  bit 0 
SMR.SBL=1 2 bits 
SMR.SBL=0 3  bits 1 
SMR.SBL=1 4 bits 
 
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7. UART (Async Serial Interface) Registers 
 
   In receive operation, only the first bit of the
  stop bit data is detected. 
   Always set this bit when transmission is disabled (SCR:TXE=0). 
 
[bit 5] INV: Inverted serial data format bit  Selects NRZ or inverted  

NRZ for the serial data format. 
Bit Description 
0 NRZ  format 
1 Inverted NRZ format 
 
[bit 4] PEN: Parity enable bit (only functions in operation mode 0)  Sets to add (for transmission) and detect  (for reception) a parity bit or not to.   
   If set to 0, no parity is added. 
   If set to 1, a parity is added. 
 
Bit Description 
0 Disables  parity.  
1 Enables  parity.  
 
 
In operation m o

de 1, this bit is internally fixed at 0. 
 [bit 3] P: Parity select bit (only functions in operation mode 0)  When set to enable p a

rity (ESCR:PEN=1, this bit is  set to either odd-number parity 1 or even-number 
parity 0. 
   If set to 0, set to even-number parity. 
   If set to 1, set to odd-number parity. 
 
Bit Description 
0 Even-number  parity 
1 Odd-number parity 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 2:0] L2, L1, L0: Data length select bit These bits set a length of transmit/receive data. 
- If set to 0b000, the data length is set to eight bits. 
- If set to 0b001, the data length is set to five bits. 
- If set to 0b010, the data length is set to six bits. 
- If set to 0b011, the data length is set to seven bits. 
- If set to 0b100, the data length is set to nine bits. 
Bit 2  Bit 1Bit 0  Description 
0 0 0  8-bit length 
0 0 1 5-bit length 
0 1 0 6-bit length 
0 1 1 7-bit length 
1 0 0 9-bit length 
 
 
  Any setting  o

ther than the above is inhibited. 
   In operati o

n mode 1, set the data length to seven or eight bits. Any other setting is inhibited. 
 
 
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7. UART (Async Serial Interface) Registers 
 
7.5.  Receive Data Register/Transmit Data Register (RDR/TDR) 
The Receive and Transmit Data Registers are allocated at the same address. This register 
functions as the Receive Data Register when data is read from it. This register operates as 
the Transmit Data Register when data is written in it. 
When FIFO operation is enabled, the RDR/TDR address functions as the FIFO read/write 
address. 
 Receive Data Register (RDR) 
 
bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      R R R R R  R R R R 
Initial 
value     0  0 
0 0 0 0 0 0 0 
 
The Receive Data Register (RDR) is a 9-bit data  buffer register for serial data reception. 
   When serial data signals are sent to the Serial Input  pin (SIN pin), they are converted by a shift register 
and stored in the Receive Data Register (RDR). 
   The high-order bits are sequen tially set to 0 according to the data length, as follows. 
Data lengthD8 D7 D6 D5D4 D3D2 D1D0 
9 bits  X X  X X X X X X X 
8 bits  0 X X  X X X X X X 
7 bits  0 0 X X  X X X X X 
6 bits  0 0 0 X X  X X X X 
5 bits 0 0  0 0 X X X  X X 
(X represents the receive data bit.) 
   When the received data is stored in the Receive Da ta Register (RDR), the receive data full flag bit 
(SSR:RDRF) is set to 1. If a receive interrupt is  enabled (SSR:RIE=1), a receive interrupt request is 
generated. 
   The Receive Data Register (RDR) must be read only  when the receive data full flag bit (SSR:RDRF) is 
1. When data is read from the Receive Data Regist er (RDR), the receive data full flag bit (SSR:RDRF) 
is cleared to 0 automatically. 
   If a receive error occurs (when SSR:PE, ORE or FRE is  1), data in the Receive Data Register (RDR) 
becomes invalid. 
   In operation mode 1 (multiprocessor  mode), 7-bit or 8-bit long operation takes place and the received AD 
bit is stored in the D8 bit. 
   For 9-bit long data transfer and  in operation mode 1, data must be read from RDR by 16-bit data 
accessing. 
 
  If the Receive  

FIFO is used and if the preset amount of data is received in the Receive FIFO buffer, 
SSR:RDRF is set to 1. 
   If th e 

receive FIFO is used and if this buffer  is emptied, the SSR:RDRF bit is cleared to 0. 
   If a receive error occurs when receive FIFO is used  (SSR:PE, ORE, or FRE is 1), the receive FIFO 
enable bit is cleared and the receive data  is not stored in the receive FIFO buffer. 
 
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7. UART (Async Serial Interface) Registers 
 
 Transmit Data Register (TDR) 
 
bit 15 ... 98 7 6 5 4 3 2 1 0 
Field  D8 D7 D6 D5 D4 D3 D2 D1 D0 
Attribute      W W W W W  W W W W 
Initial 
value     1  1 
1 1 1 1 1 1 1 
 
The Transmit Data Register (TDR) is a 9-bit data buffer register for serial data transmission. 
   If data transmission is enabled (SCR:TXE=1 ) and if the transmit data is written in the Transmit Data 
Register (TDR), the transmit data is transferred to  the Transmit Shift Register. The transmit data is then 
converted into serial data and sent out from the serial data output pin (the SOUT pin). 
   The high-order bits are sequentially made inva lid according to the data length as follows. 
Data length D8 D7  D6 D5 D4D3 D2D1  D0 
9 bits  X X  X X X X  X X  X 
8 bits  Invalid X X X X X  X X X 
7 bits Invalid Invalid X X X X  X X X 
6 bits Invalid Invalid Invalid X X X  X X X 
5 bits Invalid Invalid InvalidInvalid X X  X X X 
  When the transmit data is written in the Transmit Da ta Register (TDR), the transmit data empty flag 
(SSR:TDRE) is cleared to 0. 
   When the transmit data is transferred to the transmit sh ift register and data transmission is started, and if 
transmit FIFO is disabled or if tr ansmit FIFO is empty, the transmit data empty flag (SSR:TDRE) is set 
to 1. 
   If the transmit data empty flag (SSR:TDRE) is 1, tran smit data can be written. If a transmit interrupt is 
enabled, a transmit interrupt occurs. Perform transmit  data write after a transmit interrupt is generated or 
when the transmit interrupt data empty flag (SSR:TDRE) is 1. 
   If the transmit data empty flag (SSR:TDRE) is 0 and transmit FIFO is disabled or the transmit FIFO 
b u f f e r   i s   f u l l , no transmit data can be written. 
   In operation mode 1 (multiprocessor  mode), 7-bit or 8-bit long operation takes place and the AD bit is 
sent by writing to the D8 bit. 
   For 9-bit long data transfer and  in operation mode 1, data must be written in TDR by 16-bit data 
accessing. 
 
  The Tr ansm

it Data Register is a write-only register . While the Receive Data Register is a read-only 
register
 . As the transmit and receive  registers are allocated at the same  address, the write and read values 
differ from each other. Therefore, the INC/DE C instruction and other read-modify-write (RMW) 
instructions cannot be used. 
   For the transmit data empty flag (SSR:TDRE)  set timing when transmit FIFO is used, see 2.4 Interrupt 
an d flag set timi
n

g when transmit FIFO is used . 
 
 
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7. UART (Async Serial Interface) Registers 
 
7.6.  Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) 
Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0) are used to set a frequency 
division ratio of serial clocks. Also, an external clock can be selected as the clock source of 
the reload counter. 
 
bit 15 14 1312 11 109 8 7 6 5 4 3 2 1 0 
Field EXT (BGR1) (BGR0) 
Attribute  R/W R/W R/W R/W R/W R/W R/WR/W R/WR/W R/WR/W R/W R/W R/WR/W
Initial 
value  0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
 
   The Baud Rate Generator Registers are used to set a frequency division ra tio of serial clocks. 
   The BGR1 register corresponds to the high-order  bits, and the BGR0 register corresponds to the 
low-order bits. The reload value to be counted can  be written, and the BGR1/0 set value can be read. 
   When the reload value is written in Baud Rate  Generator Registers 1 and 0 (BGR1 and BGR0), the 
reload counter starts its counting. 
   The EXT bit (bit 15) specifies to use the clock source of  reload counter as the internal clock or use an 
external clock. If EXT=0 is set, an internal clock is  used. If EXT=1 is set, an external clock is used. 
 
[bit 15] EXT: External clock select bit 
Bit Description 
0  Uses the internal clock. 
1  Uses an external clock. 
 
[bit 14:8] BGR1: Baud Rate Generator Register 1 
Bit 14:8  Description 
Write Write data in reload counter bit 8 to 14. 
Read  Reads the BGR1 set value. 
 
[bit 7:0] BGR0: Baud Rate Generator Register 0 
Bit 7:0  Description 
Write Write data in reload counter bit 0 to 7. 
Read  Reads the BGR0 set value. 
 
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7. UART (Async Serial Interface) Registers 
 
   Data must be written in the Baud Rate Generator  Registers (BGR1 and BGR0) by 16-bit
  data accessing. 
   If the current values of Baud Rate Generator Registers (BGR1, BGR0) are changed, the new values are 
reloaded only after the counter value has reached 15h00. In order to validate the new set values 
immediately, change the BGR1/0 set values  and execute the programmable clear (UPCL). 
   If the reload value is an even number, in the receive  serial clock, the width of a LOW signal is longer 
than that of a HIGH signal by one bus clock cycl e. If the value is an odd number, the width of a LOW 
signal is the same as that of a HIGH signal. 
   Set a value 4 or higher to BGR1/0. Note that da ta may not be received successfully depending on the 
baud rate error and reload value settings. 
   To change the setting to an extern al clock (EXT=1) while the Baud Rate Generator is running, write 0 
to the Baud Rate Generators 1 and 0 (BGR1, BGR0),  execute Programmable Clear (UPCL) and then set 
for an external clock (EXT=1). 
 
 
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7. UART (Async Serial Interface) Registers 
 
7.7.  FIFO Control Register 1 (FCR1) 
The FIFO Control Register (FCR1) is used to set the FIFO test, select the transmit or receive 
FIFO, enable the transmit FIFO interrupt, and control the interrupt flag. 
 bit 15 14 13 12 11 10 9 8 7 ... 0 
Field FTST1 FTST0 - FLSTEFRIIEFDRQFTIE FSEL (FCR0) 
Attribute  R/W R/W  - R/W R/W  R/W R/W R/W    
Initial 
value  0 0 - 0 0 1 0 0    
 
[bit 15:14] FTST1, FTST0: FIFO test bits  They are FIFO Test bits. 
They must always be set to 0. 
Bit 15:14  Description 
0 Disables the FIFO test. 
1  Enables the FIFO test. 
 
 
If this  b

it is set to 1, the FIFO test is executed. 
 [bit 13] Unused bit  This bit val u

e is undefined when read. 
This bit has no effect when written. 
 
[bit 12] FLSTE: Re-transmit data lost detect enable bit  This bit enables the FIFO re-transmit data lost flag (FLST) detection. 
If set to 0, the FLST bit detection is disabled. 
If set to 1, the FLST bit detection is enabled. 
Bit Description 
0  Disables the Data Lost detection. 
1  Enables the Data Lost detection. 
 
 
If you wish  t

o set this bit to 1, set the FSET bit to 1 first, and then set this bit to 1. 
 
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7. UART (Async Serial Interface) Registers 
 
[bit 11] FRIIE: Receive FIFO idle detection enable bit This bit sets to detect the receive id le state if the receive FIFO contains  valid data and if it continues more 
than 8-bit hours. If the r eceive interrupt is enabled (SCR:RIE=1), a  receive interrupt is generated when the 
receive idle state is detected. 
If set to 0, a detection of receive idle state is disabled. 
If set to 1, a detection of receive idle state is enabled. 
Bit Description 
0  Disables the receive FIFO idle detection. 
1  Enables the receive FIFO idle detection. 
 
 
In case of usin g Receive

 FIFO, set this bit to 1. 
 [bit 10] FDRQ: Transmit FIFO data request bit  This bit reque sts for t

he transmit FIFO data. 
If this bit is 1, the transmit data is being requested. At this time, if a transmit FIFO interrupt is enabled 
(FTIE=1), a transmit FIFO interrupt request is output. 
The FDRQ bit is set when: 
   The FBYTE (for transmission) is 0 (Transmit FIFO is empty). 
 
The FDRQ bit is reset when: 
   This bit is set to 0. 
   Transmit FIFO is filled with data. 
 
Bit Description 
0  Does not request for the transmit FIFO data. 
1  Requests for the transmit FIFO data. 
 
 
  0 written  

when transmit FIFO is enabled is valid. 
   If the FBYTE (for tra n

smission) is 0, this bit cannot be set to 0. 
   If this bit is set to 1, it has no effect on the operation. 
   If a read-modify-write instruction is issued, 1 is read. 
 
[bit 9] FTIE: Transmit FIFO interrupt enable bit  This bit enables a tran sm

it FIFO interrupt. If this bit is  set to 1, an interrupt occurs when the FDRQ bit is 
set to 1. 
Bit Description 
0  Disables the transmit FIFO interrupt. 
1  Enables the transmit FIFO interrupt. 
 
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