Fujitsu Series 3 Manual
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4. Dedicated Baud Rate Generator
4.1. Baud rate settings
The following explains how to set the baud rate, and also a result of serial clock frequency
calculation.
Calculating the baud rate
Two 15-bit reload counters are set using the Baud Rate Generator Registers 1 and 0 (BGR1 and BGR0).
The baud rate is obtained in the following formulas.
(1) Reload value
(2) Calculation example
To set the 16MHz bus clock, use the internal clock, and set the 19200-bps baud rate, set the reload
value as follows. Reload value:
V = (16 x 1000000)/19200 - 1 = 832
Therefore, the baud rate is:
b = (16 x 1000000)/(832 + 1) = 19208bps
(3) Baud rate error
The baud rate error can be calculated by the following equation.
Error (%) = (Calculated value - Target value)/Target value x 100
Example: To set the 20MHz bus clock and 153600-bps target baud rate: Reload value = (20 x 1000000)/153600 - 1 = 129
Baud rate (Calculated value) = (20 x 1000000)/(129 + 1) = 153846 (bps)
Error (%) = (153846 - 153600)/153600 x 100 = 0.16 (%)
V = / b - 1
V : Reload value b: Baud rate
:Bus clock frequency or external clock frequency
If the relo
ad value is set to 0, the reload counter is stopped.
If the reload
value is an even number, in the receive serial clock, the width of a LOW signal is longer
than that of a HIGH signal by one bus clock cycle. If the value is odd, the serial clock has the same
HIGH and LOW signal width.
Set the reload value to 4 or more. Note that data may not be received normally due to the baud rate error
and reload value setting.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 19-2: UART \050Async Serial Interface\051
MN706-00002-1v0-E
815
MB9Axxx/MB9Bxxx Series
4. Dedicated Baud Rate Generator Reload value and baud rate for each bus clock frequency Table 4-1 Reload values and baud rates 8 MHz 10 MHz 16 MHz 20 MHz 24 MHz 32 MHz Baud rate (bps) Value ERRValue ERR ValueERRValueERRValueERR Value ERR 4 M - - - - - 0 4 0 5 0 7 0 2.5 M - - - 0 - - - - - - - - 2 M - 0 4 0 7 0 9 0 11 0 15 0 1 M 7 0 9 0 15 0 19 0 23 0 31 0 500000 15 0 19 0 31 0 39 0 47 0 63 0 460800 - - - - - - - - 51 -0.16 - - 250000 31 0 39 0 63 0 79 0 95 0 127 0 230400 - - - - - - - - 103 -0.16 - - 153600 51 -0.16 64 -0.16 103 -0.16 129 -0.16 155 -0.16 207 -0.16 125000 63 0 79 0 127 0 159 0 191 0 255 0 115200 68 -0.64 86 0.22 138 0.08173 0.22 207 -0.16 277 0.08 76800 103 -0.16 129 -0.16 207 -0.16259 -0.16 311 -0.16 416 0.08 57600 138 0.08 173 0.22 277 0.08 346 -0.16 416 0.08 555 0.08 38400 207 -0.16 259 -0.16 416 0.08520 0.03 624 0 832 -0.04 28800 277 0.08 346
4. Dedicated Baud Rate Generator Allowable baud rate range for data reception The following shows the ra nge of baud rate error allowed fo r the destination to receive data. Set the reception baud rate error by using the following formulas to ensure that the value falls within the allowable range. Figure 4-1 Allowable baud rate range for data reception bit 7 1 bit Stop state Parity bit 0 Start Flmax bit 7 bit 1 Stop state Parity bit0 Start FLmin Start bit 0 Parity Stop statebit7 bit 1 11 xFL ) Single data frame ( FL Sampling UART transfer rate Allowable MIN transfer rate Allowable MAX transfer rate As shown in the figure, after detection of the start b it, the sampling timing of incoming data is determined by the counter set in the BGR1/0 register. Data can be received successfully if the bit sequence including the stop bit matches the sampling timing. If this applies to a reception of 11 bits, a theoretical explanation can be given in the following. Assuming that the sampling timing margin is one bus clock ( ), the minimum allowable transfer rate (FLmin) is determined as follows: FLmin = (11bit x (V+1) - (V+1)/2 + 2)/ = (21V + 25)/2 (s) V: Reload value, : Bus clock Thus, the maximum baud rate that allows the destination to receive data (BGmax) is determined as follows. BGmax = 11/FLmin = 22 /(21V+25) (bps) V: Reload value, : Bus clock When data is received at the maximum allowable transfer rate (FLmax), the starting point of the incoming 11th bit is sampled. Thus, the maximum allowable transfer rate (FLmax) is determined as follows: 10/11 x Flmax = (11bit x (V+1) – (V+1)/2 )/ V: Reload value, : Bus clock Flmax = (21/20 x 11 x (V+1)/ Assuming that the sampling timing margin ( ) is two clocks, the maximum allowable transfer rate (Flmax) is determined as follows: 10/11 x Flmax = (11bit x (V+1) – (V+1)/2 – 2)/ V: Reload value, : Bus clock Flmax = (21/20 x 11 x (V+1) – 44/20)/ = (231V + 187)/20 (s) V: Reload value, : Bus clock Accordingly, the minimum baud rate that allows the de stination to receive data (BGmin) is determined as follows: BGmin=11/FLmax=220 /(231V+187) (bps) V: Reload value, : Bus clock FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 817 MB9Axxx/MB9Bxxx Series
4. Dedicated Baud Rate Generator From the above formulas for obtaining the minimum/maximum baud rate, the allowable error between UART and the destination is obtained as follows. Reload value (V)Maximum allowable baud rate error Minimum allowable baud rate error 3 0% 0 10 +2.98% -3.08% 50 +4.37% -4.40% 100 +4.56% -4.58% 200 +4.66% -4.67% 32767 +4.76% -4.76% Receive accuracy depe nds on the number of bits per fra me, bus clock, and reload value. The higher the bus clock and frequency division ratio are, the higher the accuracy becomes. External clock Writing 1 to the EXT bit of the Baud Rate Generator Register (BGR) causes the baud rate generator to divide the external clocks frequency. The external cl ock signal synchronizes with the internal clock o n UART. Therefore, an external clock that does not allow synchronization causes unstable operation. Functions of reload counter There are two types of reload counte rs: The transmit reload counter and the receive reload counter, both functioning as a dedicated baud rate generator. Each reload counter consists of a 15-bit register for the reload value, and generates transmitting and receiving clocks from the external or internal clock. Starting counting When the reload value is written to the Baud Rate Ge nerator Register (BGR1 or BGR0), the reload counter starts counting. Restarting The reload counter restarts counting in the following conditions. Common to transmit and receive reload counters A programmable reset (SCR:UPCL bit) Receive reload counter Detection of the start bits falling edge in asynchronous mode FUJITSU SEMICONDUCTOR LIMITED CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 818 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 5. Setting Procedure and Program Flow in Operation Mode 0 (Async Normal Mode) Operation mode 0 enables asynchronous bi-directional serial communications. CPU-to-CPU connection Select the bi-directional communication in operation mode 0 (normal mode). Connect two CPUs to each other as shown in Figure 5-1. Figure 5-1 A connection example of bi-directional communications in UART operation mode 0 (with flow control disabled) CPU_1 (Master)CPU_2 (Slave) SOT SIN SCKSOT SIN SCK Figure 5-2 A connection example of bi-directional communications in UART operation mode 0 (with flow control disabled) CPU_1 (Master)CPU_2 (Slave) SOT SIN SCK CTS RTSSOT SIN SCK CTS RTS CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 819 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Flowcharts If FIFO is not used Figure 5-3 An example of bidirectional communication flowchart (if FIFO is not used) (Transmit side) Start Set to the relevant operation mode.(Set to mode 0.) Set the 1-byte data in TDR and start communication. RDRF=1 Read and process the receive data. (Receive side) Send data. Start Set the operation mode. (So as to have it match the setting on the transmit side.) RDRF=1 Read and process the receive data. Send the 1-byte data. Yes Yes No No Send data. (ANS) CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 820 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED If FIFO is used Figure 5-4 An example of bidirectional communication flowchart (if FIFO is used) (Transmit side) Start Set the operation mode. (Set to mode 0.) Set N bytes to transmit FIFO. RDRF=1 (Receive side) Send data. Start RDRF=1 Yes Yes No No Send back data. - Enable the transmit/ receive FIFO. - Setting FBYTE Read and process the FBYTE data. Set the operation mode. (Set to mode 0.) Read and process the FBYTE data. Set the FDRQ bit to 0. Set N bytes to transmit FIFO. Set the FDRQ bit to 0. - Enable the transmit/ receive FIFO. - Setting FBYTE CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 821 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED 6. Setting Procedure and Program Flow in Operation Mode 1 (Async Multiprocessor Mode) In operation mode 1 (multiprocessor mode), co mmunications by master/slave connections with multiple CPUs. Either the master or slave function is available. CPU-to-CPU connection In a master/slave type communications, as shown in the figure, the communications system is configured with two common communication lines connected to the master CPU and multiple slave CPUs. UART can be used either as a master or a slave. Figure 6-1 A connection example for master/slave type communications on UART Master CPU Slave CPU#0 SOT SINSlave CPU#0 STO SIN STO SIN Function selection In master/slave communications, select the operatio n mode and data transfer system, as shown in Table 6-1. Table 6-1 Selection of master/slave type communications functions Operation mode Master mode CPU Slave mode CPU Data Parity Stop state Bit Bit direction Address transmission and reception AD=1 + 7 or 8 bits Address Data transmission and reception Mode 1 (A/D bit transmission) Mode 1 (A/D bit reception) AD=0 + 7 or 8 bits Data OFF One bit or 2 bits LSB or MSB first In operation mode 1, ope rate in word access mode for transmit/recei ve data (TDR/RDR). CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 822 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Communications procedure Communications start when the master CPU transmits address data. Address data is a data set whose D8 bit is 1, and used for selecting a slave CPU to co mmunicate with. Each slave CPU judges the address as programmed, and communicates with the master CPU if that address matches the assigned address. Figure 6-2 and Figure 6-3 show flowcharts of master/slave type communications (in multiprocessor mode). CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 823 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED Flowcharts If FIFO is not used Figure 6-2 An example flowchart for master/slave type communications (if FIFO buffer is not used) (Master CPU) Start Set the operation mode (set to mode 1). Set the SIN pin to serial data input. Set the SOT pin to serial data output. Set 7 or 8 data bits. Set 1 or 2 stop bits. No No Set the D8 bit to 1. Enables transmit/ receive operation. Transmits the slave address. Communicates with a slave CPU. Set the D8 bit to 0. Communications completed? Communicates with other slave CPUs. Disables transmit/ receive operation. End Yes Yes (Slave CPU) Start Set the operation mode. (Set to mode 1.) Set the SIN pin to serial data input. Set 7 or 8 data bits.Set 1 or 2 stop bits. Enables transmit/ receive operation. Receive byte D8 bit = 1 The slave address matches. Communicates with the master CPU. Communications completed? No No Yes Yes Yes No Set the SOT pin to serial data output. CHAPTER 19-2: UART \050Async Serial Interface\051 MN706-00002-1v0-E 824 MB9Axxx/MB9Bxxx Series