Fujitsu Series 3 Manual
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4. Register List
4.6. Analog Input Setting Register (ADE)
The ADE register sets a pin as an analog signal input pin of ADC.
Register Configuration
bit 31 16 15 0
Field reserved ADE
Attribute - R/W
Initial value - 0xFFFF
Register Function
[bit31:16] res : Reserved Bit
0xFFFF is read out from these bits.
When writing these bits, set 0xFFFF to them.
[bit15:0] ADE : Analog Input Setting Register Sets as an analog signal input pin.
bit15:0 Description
Reading Reads out the...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-284.png "Page 285
4. Register List
4.6. Analog Input Setting Register (ADE)
The ADE register sets a pin as an analog signal input pin of ADC.
Register Configuration
bit 31 16 15 0
Field reserved ADE
Attribute - R/W
Initial value - 0xFFFF
Register Function
[bit31:16] res : Reserved Bit
0xFFFF is read out from these bits.
When writing these bits, set 0xFFFF to them.
[bit15:0] ADE : Analog Input Setting Register Sets as an analog signal input pin.
bit15:0 Description
Reading Reads out the...")
4. Register List 4.2. Pull-up Setting Register (PCRx) The PCRx register sets pull-up of a pin. List of PCR Register Configuration 31 16 15 0 Initial value Attribute Support Reserved PCR0 0x001FR/W P0F to P00 Reserved PCR1 0x0000 R/W P1F to P10 Reserved PCR2 0x0000 R/W P2F to P20 Reserved PCR3 0x0000 R/W P3F to P30 Reserved PCR4 0x0000 R/W P4F to P40 Reserved PCR5 0x0000 R/W P5F to P50 Reserved PCR6 0x0000 R/W P6F to P60 Reserved PCR7 0x0000 R/W P7F to P70 Detailed Register Configuration bit 31 16 15 0 Field reserved PCRx Register Function [bit31:16] res : Register Bit 0x0000 is read out from these bits. When writing these bits, set them to 0x0000. [bit15:0] PCRx : Pull-up Setting Register x Sets pull-up of a pin bit15:0 Description Reading Can read out the setting value of the register. Writing 0 Disconnects the pull-up resistor of a pin. Writing 1 When a pin is in input status (for both GPIO and peripheral functions), the pull-up resistor is connected. When a pin is in output status, the pull-up resistor is disconnected. The x of PC Rx is a wildcard. PCRx indicates PCR0, PCR 1, PCR2, etc. The x of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, et c. PxF indicates P0F, P1F, P2F, etc. One register allows setting 16 pull-ups from PxF to Px0. Each bit in the register sets each pin individua lly. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of PCR0 sets P0F, the 14th bit of PCR0 sets P0E, and the 0th bit of PCR0 sets P00. As a JTAG pin is selected for P00 to P04, the initial value is 1. When using I 2C function, use external pull-up by setting PCRx=0. PCR8 is not avaliable. For a pin which is not available in your product, writing a value to the bit is invalid, and the read value is undefined. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 245 MB9Axxx/MB9Bxxx Series
4. Register List 4.3. Port input/output Direction Setting Register (DDRx) The DDRx register sets input/output direction of a pin. List of DDR Register Configuration 31 16 15 0 Initial value Attribute Support reserved DDR0 0x0000 R/W P0F to P00 reserved DDR1 0x0000 R/W P1F to P10 reserved DDR2 0x0000 R/W P2F to P20 reserved DDR3 0x0000 R/W P3F to P30 reserved DDR4 0x0000 R/W P4F to P40 reserved DDR5 0x0000 R/W P5F to P50 reserved DDR6 0x0000 R/W P6F to P60 reserved DDR7 0x0000 R/W P7F to P70 reserved DDR8 0x0000 R/W P8F to P80 Detailed Register Configuration bit 31 16 15 0 Field reserved DDRx Register Function [bit31:16] res : Reserved Bit 0x0000 is read out from these bits. When writing these bits, set them to 0x0000. [bit15:0] DDRx : Port input/output Direction Setting Register x Sets input/output direction of a pin. bit15:0 Description Reading Can read out the setting value of the register. Writing 0 Uses GPIO in input direction. If a pin is selected as an input/output pin of peripheral functions, this setting value is invalid. Writing 1 Uses GPIO in output direction. If a pin is selected as an input/output pin of peripheral functions, this setting value is invalid. The x of DDRx is a wildcard. DDRx indicates DDR0, DDR1, DDR2, e t c. The x of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, et c. PxF indicates P0F, P1F, P2F, etc. One register allows setting the input/output direction of 16 ports from PxF to Px0. Each bit in the register sets each pin individua lly. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of DDR0 sets P0F, the 14th bit of DDR0 sets P0E, and the 0th bit of DDR0 sets P00. If the output RTO of a multifunction timer is selected, in an emergency stop due to DTTIX signal, a DDR controls pin status. For more information, see the chapter MULTIFUNCTION TIMER. For a pin which is not available in your product, writing a value to the bit is invalid, and the read value is undefined. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 246 MB9Axxx/MB9Bxxx Series
4. Register List 4.4. Port Input Data Register (PDIRx) The PDIRx register indicates input data of a pin. List of PDIR Register Configuration 31 16 15 0 Initial value Attribute Support reserved PDIR0 0x0000 R P0F to P00 reserved PDIR1 0x0000 R P1F to P10 reserved PDIR2 0x0000 R P2F to P20 reserved PDIR3 0x0000 R P3F to P30 reserved PDIR4 0x0000 R P4F to P40 reserved PDIR5 0x0000 R P5F to P50 reserved PDIR6 0x0000 R P6F to P60 reserved PDIR7 0x0000 R P7F to P70 reserved PDIR8 0x0000 R P8F to P80 Detailed Register Configuration bit 31 16 15 0 Field reserved PDIRx Register Function [bit31:16] res : Reserved Bit 0x0000 is read out from these bits. When writing these bits, set them to 0x0000. [bit15:0] PDIRx : Port Input Data Register x Reads out input data of a pin. bit15:0 Description Reading 0 Regardless of pin function settings (PFR /EPFR/DDR/PDOR), it indicates that a pin is in the status of L level input or L level output. When a special pin is selected by ADE/SPSR, as input is cut off, 0 is always read out. Reading 1 Regardless of pin function settings (PFR /EPFR/DDR/PDOR), it indicates that a pin is in the status of H level input or H level output. Writing Writing does not affect anything. The x of PDIRx is a wildcard. PDIRx indicates PDIR0, PDIR1, PDIR2, etc. Th e x of Px0 and PxF is a wildcard. Px0 indicates P00, P10, P20, et c. PxF indicates P0F, P1F, P2F, etc. One register allows reading input data of 16 ports from PxF to Px0. Each bit in the register indicates the status of each pin individually. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of PDIR0 indicates P0F, the 14th bit of PDIR0 indicates P0E, and the 0th bit of PDIR0 indicates P00. 0 is always read for a bit value of the pin which is not available in your product. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 247 MB9Axxx/MB9Bxxx Series
4. Register List 4.5. Port Output Data Register x (PDORx) The PDORx register sets output data to a pin. List of PDOR Register Configuration 31 16 15 0 Initial value Attribute Support reserved PDOR0 0x0000 R/W P0F to P00 reserved PDOR1 0x0000 R/W P1F to P10 reserved PDOR2 0x0000 R/W P2F to P20 reserved PDOR3 0x0000 R/W P3F to P30 reserved PDOR4 0x0000 R/W P4F to P40 reserved PDOR5 0x0000 R/W P5F to P50 reserved PDOR6 0x0000 R/W P6F to P60 reserved PDOR7 0x0000 R/W P7F to P70 reserved PDOR8 0x0000 R/W P8F to P80 Detailed Register Configuration Bit 31 16 15 0 Field reserved PDORx Register Function [bit31:16] res : Reserved Bit 0x0000 is read out from these bits. When writing these bits, set them to 0x0000. [bit15:0] PDORx : Port Output Data Register x Sets output data of a pin. bit15:0 Description Reading Reads out the register value. Writing 0 Outputs L level to GPIO. If a pin is selected as GPIO input or peripheral functions input/output, a setting value is invalid. Writing 1 Outputs H level to GPIO. If a pin is selected as GPIO input or peripheral functions input/output, a setting value is invalid. The x of PDORx is a wildcard. PDORx indicates PDOR0, PDOR1, PDOR2, etc. The x o f Px 0 and PxF is a wildcard. Px0 indicates P00, P10, P20, et c. PxF indicates P0F, P1F, P2F, etc. One register allows setting output data of 16 ports from PxF to Px0. Each bit in the register sets each pin individua lly. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of PDOR0 sets P0F, the 14th bit of PDOR0 sets P0E, and the 0th bit of PDOR0 sets P00. For a pin which is not available in your product, writing a value to the bit is invalid, and the read value is undefined. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 248 MB9Axxx/MB9Bxxx Series
4. Register List 4.6. Analog Input Setting Register (ADE) The ADE register sets a pin as an analog signal input pin of ADC. Register Configuration bit 31 16 15 0 Field reserved ADE Attribute - R/W Initial value - 0xFFFF Register Function [bit31:16] res : Reserved Bit 0xFFFF is read out from these bits. When writing these bits, set 0xFFFF to them. [bit15:0] ADE : Analog Input Setting Register Sets as an analog signal input pin. bit15:0 Description Reading Reads out the register value. Writing 0 Uses a pin not as an analog input but digital input/output. Writing 1 Uses a pin as analog input. (An I/O cell will be in a state of input direction, input cut-off, and pull-up disconnection.) This r e gister sets ports from P1F to P10 as analog input pins. Each bit in t he register sets each pin individua lly. There is a one-to-one correspondence between bit assignment and the order of pins. For example, the 15th bit of ADE sets P1F (AN15), the 14th bit of ADE sets P1E (AN14), and the 0th bit of ADE sets P10 (AN00). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 249 MB9Axxx/MB9Bxxx Series
4. Register List 4.7. Extended Pin Function Setting Register (EPFRx) The EPFRx register assigns functions to a pin if there is more than one function. List of EPFRx Register Configuration 31 0Initial value Attribute Support EPFR00 0x00030000 R/W System function EPFR01 0x00000000 R/W EPFR02 0x00000000 R/W Multi-function timer Reserved - - - EPFR04 0x00000000 R/W EPFR05 0x00000000 R/W Base timer EPFR06 0x00000000 R/W External interrupt EPFR07 0x00000000 R/W EPFR08 0x00000000 R/W Multi-function serial EPFR09 0x00000000 R/W CAN/ADC trigger/QPRC EPFR10 0x00000000 R/W External bus FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 250 MB9Axxx/MB9Bxxx Series
4. Register List
4.8. Extended Pin Function Setting Register 00 (EPFR00)
The EPFR00 register assigns functions to a pin if there is more than one function.
Register Configuration
bit 31 30 29 28 27 26 25 24
Field Reserved TRC1E TRC0E
Attribute - R/W R/W
Initial value 1’b0 1’b0
bit 23 22 21 20 19 18 17 16
Field Reserved
JTAGEN1S JTAGEN0B
Attribute - R/W R/W
Initial value 1’b1 1’b1
bit 15 14 13 12 11 10 9 8
Field Reserved USB0PE -
Attribute - R/W -
Initial value 1’b0 -
bit 7 6 5 4 3 2 1 0
Field Reserved CROUTE NMIS
Attribute - R/W R/W
Initial value 1’b0 1’b0
Register Function
[bit31:26] res : Reserved Bit
0b000000 is read out from these bits.
When writing these bits, set them to 0b000000.
[bit25] TRC1E : TRACED Function Select Bit 1
Selects a function for TRACED2 and TRACED3.
bit Description
Reading Reads out the register value.
Writing 0 Does not use two pins of TRACED2 and TRACED3. [Initial value]
(A shared pin is available)
Writing 1
Uses two pins of TRACED2 and TRACED3.
[bit24] TRC0E : TRACED Function Select Bit 0
Selects a function for TRACECLK, TRACED0, and TRACED1 pins.
bit Description
Reading Reads out the register value.
Writing 0 Does not use three pins of TRACECLK, TRACED0, and TRACED1. [Initial value]
(A shared pin is available)
Writing 1
Uses three pins of TRACECLK, TRACED0, and TRACED1.
[bit23:18] res : Reserved Bit 0b000000 is read out from these bits.
When writing these bits, set them to 0b000000.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 9: I/O PORT
MN706-00002-1v0-E
251
MB9Axxx/MB9Bxxx Series
4. Register List [bit17] JTAGEN1S : JTAG Function Select Bit 1 Selects a function for TRSTX and TDI. bit Description Reading Reads out the register value. Writing 0 Does not use two pins of TRSTX and TDI. (A shared pin is available.) Writing 1 Uses two pins of TRSTX and TDI. [Initial value] [bit16] JTAGEN0B : JTAG Function Select Bit 0 Selects a function for TCK, TMS, and TDO pins. bit Description Reading Reads out the register value. Writing 0 Does not use three pins of TCK, TMS, and TDO. (A shared pin is available.) Writing 1 Uses three pins of TCK, TMS, and TDO. [Initial value] [bit15:10] res : Reserved Bit 0b000000 is read out from these bits. When writing these bits, set them to 0b000000. [bit9] USBP0E : USBch.0 Function Select Bit 1 Selects a function for USBch.0. bit Description Reading Reads out the register value. Writing 0 Does not produce output D+ resistor control signal (HCONTX) for USBch.0. [Initial value] (A shared pin is available.) Writing 1 Produces output D+ resistor control signal (HCONTX) for USBch.0. [bit8:2] res : Reserved Bit 0b0000000 is read out from these bits. When writing these bits, set them to 0b0000000. [bit1] CROUTE : Internal high-speed CR Oscillation Output Function Select Bit Selects internal high-speed CR oscillation output. bit Description Reading Reads out the register value. Writing 0 Does not produce internal high-sp eed CR oscillation output. [Initial value] Writing 1 Produces internal high-speed CR oscillation output. [bit0] NMIS : NMIX Function Select Bit Selects a function for the NMIX pin. bit Description Reading Reads out the register value. Writing 0 Does not use the NMIX pin. [Initial value] Writing 1 Uses the NMIX pin. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 252 MB9Axxx/MB9Bxxx Series
4. Register List
4.9. Extended Pin Function Setting Register 01 (EPFR01)
The EPFR01 register assigns functions to a pin of the multifunction timer Unit0.
Register Configuration
bit 31 30 29 28 27 26 25 24
Field IC03S IC02S IC01S
Attribute R/W R/W R/W
Initial value 3’b000 3’b000 3’b000
bit 23 22 21 20 19 18 17 16
Field IC01S IC00S FRCK0S DTTI0S
Attribute R/W R/W R/W
Initial value 3’b000 2’b00 2’b00
bit 15 14 13 12 11 10 9 8
Field Reserved DTTI0CRTO05E RTO04E
Attribute - R/W R/W R/W
Initial value - 1’b0 2’b00 2’b00
bit 7 6 5 4 3 2 1 0
Field RTO03E RTO02E RTO01E RTO00E
Attribute R/W R/W R/W R/W
Initial value 2’b00 2’b00 2’b00 2’b00
Register Function
[bit31:29] IC03S : IC03 Input Select Bit
Selects input for IC03.
bit31:29 Description
Reading Reads out the register value.
Writing 000 Uses IC03_0 at the input pin of the input capture IC03. [Initial value]
Writing 001 Same as Writing 000.
Writing 010 Uses IC03_1 at the input pin of the input capture IC03.
Writing 011 Setting is prohibited.
Writing 100 Uses internal macro MFSch.3LSYN for input of the input capture IC03.
Writing 101 Uses internal macro MFSch.7LSYN for input of the input capture IC03.
Writing 110 Setting is prohibited.
Writing 111 Uses the internal macro pin CRTRIM for input of the input capture IC03.
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 9: I/O PORT
MN706-00002-1v0-E
253
MB9Axxx/MB9Bxxx Series
4. Register List [bit28:26] IS02S : IC02 Input Select Bit Selects input for IC02. bit28:26 Description Reading Reads out the register value. Writing 000 Uses IC02_0 at the input pin of the input capture IC02. [Initial value] Writing 001 Same as Writing 000. Writing 010 Uses IC02_1 at the input pin of the input capture IC02. Writing 011 Setting is prohibited. Writing 100 Uses internal macro MFSch.2LSYN for input of the input capture IC02. Writing 101 Uses internal macro MFSch.6LSYN for input of the input capture IC02. Writing 110 Setting is prohibited. Writing 111 Setting is prohibited. [bit25:23] IC01S : IC01 Input Select Bit Selects input for IC01. bit25:23 Description Reading Reads out the register value. Writing 000 Uses IC01_0 at the input pin of the input capture IC01. [Initial value] Writing 001 Same as Writing 000. Writing 010 Uses IC01_1 at the input pin of the input capture IC01. Writing 011 Setting is prohibited. Writing 100 Uses internal macro MFSch.1LSYN for input of the input capture IC01. Writing 101 Uses internal macro MFSch.5LSYN for input of the input capture IC01. Writing 110 Setting is prohibited. Writing 111 Setting is prohibited. [bit22:20] IC00S : IC00 Input Select Bit Selects input for IC00. bit22:20 Description Reading Reads out the register value. Writing 000 Uses IC00_0 at the input pin of the input capture IC00. [Initial value] Writing 001 Same as Writing 000. Writing 010 Uses IC00_1 at the input pin of the input capture IC00. Writing 011 Setting is prohibited. Writing 100 Uses internal macro MFSch.0LSYN for input of the input capture IC00. Writing 101 Uses internal macro MFSch.4LSYN for input of the input capture IC00. Writing 110 Setting is prohibited. Writing 111 Setting is prohibited. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 9: I/O PORT MN706-00002-1v0-E 254 MB9Axxx/MB9Bxxx Series