Fujitsu Series 3 Manual

							MN706-00002-1v0-E FUJITSU SEMICONDUCTOR 
CONTRO

LLER MANUAL 
 
 
 
  
FUJ ITSU

 SEMICONDUCTOR CONFIDENTIAL 
 
 
 
 
 
 
FM3 
32-BIT MICROCONTROLLER 
MB9Axxx / MB9Bxxx Series 
PERIPHERAL MANUAL 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
For the information for microcontroller supports, see the following web site. 
 
http://edevice.fujitsu.com/micom/en-support/ 
 
 
 
 
 
FUJITSU SEMICONDUCTOR LIMITED 
  
						

							 
 
 
 FUJITSU SEMICON

DUCTOR LIMITED  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Preface 
 
 
Thank you for your continued use of Fujitsu semiconductor products. 
Read this manual and Data Sheet thoroughly  before using products in this series. 
 
 Purpose of this manual and intended readers 
This manual explains the functions and operations of this series and describes how it is used. The manual is 
intended for engineers engaged in the actual development of products using this series. 
*  This manual explains the architecture and operation of the peripheral modules, but does not cover the 
specifics of each device in the series. 
It is not intended to replace the device data sheets, but complement them. 
Users should refer to the respective data sheets of devices for device-specific details. 
 
  Trademark 
ARM and Cortex-M3 are the trademarks of AR M Limited in the EU and other countries. 
The company names and brand names herein are the tradem arks or registered trademarks of their respective 
owners. 
 
  Sample programs and development environment 
Fujitsu Semiconductor offers sample programs free of charge for using the peripheral functions of the FM3 
family. Fujitsu Semiconductor also makes available descriptions of the development environment required 
for this series. Feel free to use them to verify the operational specifications and usage of this Fujitsu 
Semiconductor microcontroller.   
  Microcontroller support information: 
http://edevice.fujitsu.com/micom/en-support/ 
* : Note that the sample programs are subject to change  without notice. Since they are offered as a way to 
demonstrate standard operations and usage, evaluate them sufficiently before running them on your 
system. 
Fujitsu Semiconductor assumes no responsibility for  any damage that may occur as a result of using a 
sample program. 
 
MN706-00002-1v0-E 
\0501\051 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 The contents of this document are  subject to change without notice. 
Customers are advised to consult with  sales representatives before ordering. 
 The information, such as descriptions of function and application circuit examples, in this document are presented 
solely for the purpose of reference to show examples of oper ations and uses of FUJITSU SEMICONDUCTOR device; 
FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such 
information. When you develop equipmen t incorporating the device based on such information, you must assume any 
responsibility arising out of such use of the informati on. FUJITSU SEMICONDUCTOR assumes no liability for any 
damages whatsoever arising out of the use of the information. 
 Any information in this document, including descriptions of  function and schematic diagrams, shall not be construed as 
license of the use or exercise of any intellectual property right , such as patent right or copyright, or any other right of 
FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of 
any third-partys intellectual property right or other right by usin g such information. FUJITSU SEMICONDUCTOR 
assumes no liability for any infringement of the intellectual  property rights or other rights of third parties which would 
result from the use of information contained herein. 
 The products described in this document are designed, deve loped and manufactured as contemplated for general use, 
including without limitation, ordinary industrial use, general office use, personal use,  and household use, but are not 
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless 
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal 
injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air 
traffic control, mass transport control, medical life support syst em, missile launch control in weapon system), or (2) for 
use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). 
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or 
damages arising in connection with above-mentioned uses of the products. 
 Any semiconductor devices have an inherent chance of failu re. You must protect against injury, damage or loss from 
such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire 
protection, and prevention of over-current levels and other abnormal operating conditions. 
 Exportation/release of any products descri bed in this document may require necessary procedures in  accordance with 
the regulations of the Foreign Exchange and Foreign Trade Control Law of  Japan and/or US export control laws. 
 The company names and brand names herein are the trademarks  or registered trademarks of their respective owners. 
 
Copyright ©2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved. 
MN706-00002-1v0-E 
\0502\051 
MB9Axxx/MB9Bxxx  Series  
						

							FUJITSU SEMICONDUCTOR LIMITED 
Related Manuals 
 
 
The manuals related to this series are listed below. See the manual appropriate to the applicable 
conditions. 
The contents of these manuals are subject to change without notice. Contact us to check the latest 
versions available. 
 
 Peripheral Manual 
  FM3 FAMILY MB9Axxx / MB9Bxxx SERIES PERIPHERAL MANUAL (this manual) 
 
  Data sheet 
For details about device-specific, el ectrical characteristics, package dime nsions, ordering information etc., 
see the following document. 
   MICROCONTROLLER 32 -bit ORIG INAL FM3 FAMILY DATA SHEET 
 
*  The data sheets for each series are provided.  See the appropriate data sheet for the series that you are using. 
 
  CPU Programming manual 
For details about ARM Cortex-M3 core, see the following documents that can be obtained from 
http://www.arm.com/. 
  Cortex-M3 Technical Reference Manual 
   ARMv7-M Architecture Application  Level  Reference  Manual 
 
  Flash Programming manual 
For details about the functions and operations of th e built-in flash memory, see the following document. 
   FM3 FAMILY FLASH PROGRAMMING MANUAL 
 
*  This manual is provided for each series.  See the appropriate manual for the series that you are using. 
 
MN706-00002-1v0-E 
\0503\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 FUJITSU SEMICONDUCTOR LIMITED 
 
FUJITSU SEMICONDUCTOR CONFIDENTIAL  iv 
How to Use This Manual 
 
 
  Finding a function 
The following methods can be used to search for the explanation of a desired function in this manual: 
  Search from the table of the contents 
The table of the contents lists the manual contents in the order of description. 
   Search from the register 
The address where each register is located is not descri bed in the text. To verify the address of a register, 
see Register Map in Appendixes. 
 
  About the chapters 
Basically, this manual explains 1 peripheral function per chapter. 
 
  Terminology 
This manual uses the following terminology. 
Term Explanation 
Word  Indicates access in units of 32 bits. 
Half word Indicates access in units of 16 bits. 
Byte  Indicates access in units of 8 bits. 
 
 Notations 
  The notations in bit configuration of the register  explanation of this manual are written as follows. 
   bit : bit number 
   Field : bit field name 
   Attribute : Attributes for r ead and write of each bit 
   R : Read only 
   W : Write only 
   R/W :  Readable/Writable 
   - : Undefined 
   Initial value : Initial value of the register after reset 
   0  :  Initial value is 0 
   1  :  Initial value is 1 
   X  :  Initial value is undefined 
 
   The multiple bits are written as follows in this manual. 
Example : bit7:0 indicates the bits from bit7 to bit0 
 
   The values such as for addresses ar e written as follows in this manual. 
   Hexadecimal number  :  0x is attached in the beginning of a value as a prefix (example : 0xFFFF) 
   Binary number  :  0b is attached in the beginning of a value as a prefix (example: 0b1111) 
   Decimal number  :  Written using numbers only (example : 1000) 
 
MN706-00002-1v0-E 
\0504\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CONTENTS 
CHAPTER 1: System Overview ........................................................................\
.....................1 
1. Bus Architecture ........................................................................\
.................................... ....2 
1.1. Bus Block Diagram................................................................\
......................................... .4 
2. Memory Architecture ........................................................................\
................................. 5 
2.1. Memory Map ........................................................................\
........................................ ... 6 
2.2. Peripheral  Address Map........................................................................\
.......................... 7 
3. Cortex-M3 Architecture ........................................................................\
.............................. 9 
4. Mode ........................................................................\
................................................ ....... 11 
4.1. How to Set Operating Mode........................................................................\
.................. 11 
4.2. Start up Seque nce........................................................................\
.................................. 12 
CHAPTER 2-1: Clock ........................................................................\
...................................13  
1. Clock Generation Unit Overview........................................................................\
.............14 
2. Clock Generation Unit C onfiguration/Block Diagram .......................................................15 
3. Clock Generation  Unit Operations........................................................................\
...........18 
3.1. Selecting t he clock mode ........................................................................\
...................... 18 
3.2. Internal bus clock freq uency division control ................................................................ 19 
3.3. PLL clock control ........................................................................\
................................. .. 20 
3.4. Oscillation stabilization wait time ........................................................................\
.......... 22 
3.5. Interrupt causes ........................................................................\
.................................. .. 23 
4. Clock Setup Procedure Examples........................................................................\
...........24 
5. Clock Generation Un it Register List ........................................................................\
........26 
5.1. System Clock Mode Cont rol Register (SCM_CTL)....................................................... 27 
5.2. System Clock Mode Stat us Register (SCM_STR) ........................................................ 29 
5.3. Base Clock Prescale r Register (BSC_PSR) ................................................................. 31 
5.4. APB0 Prescaler Re gister (APBC0_PSR)...................................................................... 32 
5.5. APB1 Prescaler Re gister (APBC1_PSR)...................................................................... 33 
5.6. APB2 Prescaler Re gister (APBC2_PSR)...................................................................... 34 
5.7. Software Watchdog Clock Prescaler Regi ster (SWC_PSR)......................................... 35 
5.8. Trace Clock Prescale r Register (TTC_PSR) ................................................................ 36 
5.9. Clock Stabilization Wait  Time Register (CSW_TMR) .................................................... 37 
5.10. PLL Clock Stabilization Wait Time Setup Register  (PSW_TMR) ................................ 39 
5.11. PLL Control Register 1 (PLL_ CTL1) ........................................................................\
... 40 
5.12. PLL Control Regi ster 2 (PLL_CTL2) ........................................................................\
... 41 
5.13. Debug Break Watc hdog Timer Control Register (DBWDT_CTL) ............................... 42 
5.14. Interrupt Enable R egister (INT_ENR) ........................................................................\
. 43 
5.15. Interrupt Status  Register (INT_STR) ........................................................................\
... 44 
5.16. Interrupt Clear R egister (INT_CLR) ........................................................................\
.... 45 
6. Clock Generation Unit Usage Prec autions......................................................................47 
FUJITSU SEMICONDUCT OR LIMITED 
MN706-00002-1v0-E 
\0505\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 2-2: High-Speed CR Trimming ........................................................................\
...49 
1. High-Speed CR Trimming Function Overview .................................................................50 
2. High-Speed CR Trimming Function  Configuration and Block Diagram............................51 
3. High-Speed CR Trimming Function Oper ation ................................................................52 
4. High-Speed CR Trimming Function Setup Procedur e Example ......................................53 
5. High-Speed CR Trimming Function Regist er List ............................................................59 
5.1. High-speed CR oscillation Frequency Division Setup  Register (MCR_PSR) ............... 60 
5.2. High-speed CR osc illation Frequency Trimming R egister (MCR_FTRM) .................... 61 
5.3. High-Speed CR Oscillator Register  Write-Protect Register (MCR_RLR) ..................... 62 
6. High-Speed CR Trimming Function Usage Pr ecautions ..................................................63 
CHAPTER 3: Resets ........................................................................\
....................................65  
1. Overview ........................................................................\
.................................................66 
2. Confi guration ........................................................................\
....................................... ....67 
3. Explanation of  Operations ........................................................................\
.......................68 
3.1. Reset Causes........................................................................\
...................................... .. 69 
3.2. Resetting Insi de the Device ........................................................................\
.................. 72 
3.2.1. Resets to Cortex-M3 ........................................................................\
............................7 3 
3.2.2. Resets to Peripheral Circuit ........................................................................\
.................74 
3.3. Rese t Sequence......................................................................\
...................................... 75 
3.4. Operations After  Resets are Cleared ........................................................................\
.... 77 
4. Registers ........................................................................\
........................................... ......78 
4.1. Reset Cause Register (RST_STR: ReSeT STatus Register) ....................................... 79 
CHAPTER 4: Low-voltage Detection........................................................................\
............83 
1. Overview ........................................................................\
............................................ .....84 
2. Confi guration ........................................................................\
....................................... ....85 
3. Explanation of  Operations ........................................................................\
.......................87 
4. Setup Procedure Exampl es ........................................................................\
.....................90 
5. Registers ........................................................................\
........................................... ......91 
5.1. Low-voltage Detection Voltage Control Register (LVD_CTL) ....................................... 92 
5.2. Low-voltage Detection Inte rrupt Register (LVD_STR) .................................................. 94 
5.3. Low-voltage Detection Interrupt  Clear Register (LVD_CLR) ........................................ 95 
5.4. Low-voltage Detection Voltage Protection Register  (LVD_RLR) .................................. 96 
5.5. Low-voltage Detection Circuit  Status Register (LVD_STR2) ........................................ 97 
CHAPTER 5: Low Power Consumption Mode .....................................................................99 
1. Overview of Low Po wer Consumption Mode ................................................................. 100 
2. Configuration of  CPU Operation Modes........................................................................\
105 
3. Operations of  Standby Modes ........................................................................\
............... 110 
3.1. Operations of SLEEP modes (high speed CR sleep, main sleep, PLL sleep,   
low speed CR sleep, and  sub sleep modes) ........................................................... 113 
3.2. Operations of TIMER modes (high speed CR timer, main timer, PLL timer,    low speed CR timer, an d sub timer modes)............................................................. 115 
3.3. Operations of STOP m ode ........................................................................\
.................. 117 
4. Standby Mode Setting Procedure Examples.................................................................120 
5. List of Low Power Co nsumption Registers ....................................................................122 
5.1. Standby Mode Control  Register (STB_CTL)............................................................... 123 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\0506\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 6: Interrupts ........................................................................\
..............................125 
1. Overview ........................................................................\
...............................................126 
2. Stru cture ........................................................................\
........................................... .....127 
3. Exception and Inte rrupt Vectors........................................................................\
............128 
4. Registers ........................................................................\
........................................... ....131 
4.1. DMA Request Selection Register (DRQSEL) ............................................................. 133 
4.2. EXC02 Batch Read Re gister (EXC02MON) ............................................................... 136 
4.3. IRQ00 Batch Read Re gister (IRQ00MON) ................................................................. 137 
4.4. IRQ01 Batch Read Re gister (IRQ01MON) ................................................................. 138 
4.5. IRQ02 Batch Read Re gister (IRQ02MON) ................................................................. 139 
4.6. IRQ03 Batch Read Re gister (IRQ03MON) ................................................................. 140 
4.7. IRQ04/05 Batch Read  Register (IRQxxMON) ............................................................ 141 
4.8. IRQ06 Batch Read Re gister (IRQ06MON) ................................................................. 142 
4.9. IRQ07/09/11/13/15/17/19/21 Batc h Read Register (IRQxxMON)............................... 144 
4.10. IRQ08/10/12/14/16/18/20/22 Batch Read Register  (IRQxxMON) ............................ 145 
4.11. IRQ23 Batch Read Register (IRQ 23MON) ............................................................... 146 
4.12. IRQ24 Batch Read R egister (IRQ24MON) ............................................................... 147 
4.13. IRQ25/26/27 Batch Read  Register (IRQxxMON) ..................................................... 149 
4.14. IRQ28 Batch Read R egister (IRQ28MON) ............................................................... 150 
4.15. IRQ29 Batch Read R egister (IRQ29MON) ............................................................... 152 
4.16. IRQ30 Batch Read R egister (IRQ30MON) ............................................................... 153 
4.17. IRQ31 Batch Read R egister (IRQ31MON) ............................................................... 155 
4.18. IRQ32/33 Batch Read  Register (IRQxxMON) .......................................................... 157 
4.19. IRQ34 Batch Read R egister (IRQ34MON) ............................................................... 158 
4.20. IRQ35 Batch Read R egister (IRQ35MON) ............................................................... 159 
4.21. IRQ36/37 Batch Read  Register (IRQxxMON) .......................................................... 160 
4.22. IRQ38/39/40/41/42/43/44/45 Batch Read Register  (IRQxxMON) ............................ 161 
4.23. IRQ46/47 Batch Read  Register (IRQxxMON) .......................................................... 162 
5. Usage Wa rnings........................................................................\
....................................16 3 
CHAPTER 7: External Interrupt and NMI Control Sections................................................165 
1. Overview ........................................................................\
............................................ ...166 
2. Block  Diagram ........................................................................\
....................................... 167 
3. Operations and Setti ng Procedure Examples................................................................168 
3.1. Operations of external  interrupt control section .......................................................... 169 
3.2. Operations of NM I control section........................................................................\
....... 171 
3.3. Returning from  timer or stop mode........................................................................\
..... 172 
4. Registers ........................................................................\
........................................... ....174 
4.1. Enable Interrupt Request Register [ENIR] .................................................................. 175 
4.2. External Interrupt Re quest Register [EIRR] ................................................................ 176 
4.3. External Interrupt  Clear Register [EICL] ..................................................................... 177 
4.4. External Interrupt  Level Register [ELVR] .................................................................... 178 
4.5. Non Maskable Interrupt Request Register  [NMIRR] ................................................... 179 
4.6. Non Maskable Interrupt Clear Register  [NMICL] ........................................................ 180 
FUJITSU SEMICO NDUCTOR LIMITED 
MN706-00002-1v0-E 
\0507\051 
MB9Axxx/MB9Bxxx  Series  
						

							 
 
 
CHAPTER 8: DMAC........................................................................\
...................................181 
1. Overview of DMAC ........................................................................\
................................ 182 
2. Configuration of DM AC......................................................................\
............................183 
2.1. DMAC and System Configur ation ........................................................................\
....... 184 
2.2. I/O Signal s of DMAC ........................................................................\
........................... 186 
3. Functions and Oper ations of DMAC........................................................................\
......188 
3.1. Software-Blo ck Transfer........................................................................\
...................... 189 
3.2. Software-Bur st Transfer........................................................................\
...................... 191 
3.3. Hardware-Dem and Transfer ........................................................................\
............... 192 
3.4. Hardware-Blo ck Transfer & Burst Transfer ................................................................. 193 
3.5. Channel Prio rity Control ........................................................................\
...................... 195 
4. DMAC C ontrol ........................................................................\
.......................................1 96 
4.1. Overview of DMAC Control ........................................................................\
................. 197 
4.2. DMAC Operation and Control Pr ocedure for Software Transfer ................................ 198 
4.3. DMAC Operation and Control Proce dure for Hardware (EM=0) Transfer .................. 205 
4.4. DMAC Operation and Control Proce dure for Hardware (EM=1) Transfer .................. 214 
5. Registers of DMAC........................................................................\
................................218  
5.1. List of Registers ........................................................................\
................................. . 219 
5.2. Entire DMAC Configur ation Register (DMACR) ......................................................... 220 
5.3. Configuration A  Register (DMACA)........................................................................\
..... 222 
5.4. Configuration B  Register (DMACB) ........................................................................\
.... 225 
5.5. Transfer Source Addr ess Register (DMACSA) ........................................................... 229 
5.6. Transfer Dest ination Address  Regi ster (DMACDA) .................................................... 230 
5.7. Notes on Register Se tting ........................................................................\
................... 231 
CHAPTER 9: I/O PORT ........................................................................\
.............................233 
1. Overview ........................................................................\
............................................ ...234 
2. Configuration, Block Diagram, and O peration ...............................................................235 
3. Setup Procedure Exampl e........................................................................\
.....................241 
4. Regist er List ........................................................................\
....................................... ...242 
4.1. Port Function Setting Register (PFRx)........................................................................\
 244 
4.2. Pull-up Setting R egister (PCRx) ........................................................................\
......... 245 
4.3. Port input/output Direct ion Setting Register (DDRx)................................................... 246 
4.4. Port Input Data  Register (PDIRx)........................................................................\
........ 247 
4.5. Port Output Data Register x  (PDORx) ........................................................................\
 248 
4.6. Analog Input Setti ng Register (ADE)........................................................................\
... 249 
4.7. Extended Pin Function Se tting Register (EPFRx) ...................................................... 250 
4.8. Extended Pin Function Se tting Register 00 (EPFR00) ............................................... 251 
4.9. Extended Pin Function Se tting Register 01 (EPFR01) ............................................... 253 
4.10. Extended Pin Function Setting Register 02  (EPFR02) ............................................. 257 
4.11. Extended Pin Function Se tting Register 04 (EPFR04) ............................................. 261 
4.12. Extended Pin Function Setting Register 05  (EPFR05) ............................................. 265 
4.13. Extended Pin Function Setting Register 06  (EPFR06) ............................................. 269 
4.14. Extended Pin Function Setting Register 07  (EPFR07) ............................................. 273 
4.15. Extended Pin Function Setting Register 08  (EPFR08) ............................................. 277 
4.16. Extended Pin Function Setting Register 09  (EPFR09) ............................................. 282 
4.17. Extended Pin Function Setting Register 10  (EPFR10) ............................................. 286 
4.18. Special Port Setti ng Register (SPSR)....................................................................... 292 
5. Usage Prec autions........................................................................\
................................294  
FUJITSU SEMICONDUCTOR LIMITED 
MN706-00002-1v0-E 
\0508\051 
MB9Axxx/MB9Bxxx  Series