Fujitsu Series 3 Manual
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4. Registers of Multifunction Timer
Timer PPG Mode
The operation in Timer-PPG mode is as follows (see the List of Output Details).
Each channel of WFG has two flags: WFG timer ac tive flag0 and WFG timer active flag1. This mode
outputs a waveform using these flags.
The CH_GATE signal outputs WFG timer active flag1, WFG timer active flag0, or the logic OR signal of
each signal by GTEN[1:0] setting.
The RTO(1) and RTO(0) signals output these active fl ags, CH_PPG signal, or the logic AND...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-635.png "Page 636
4. Registers of Multifunction Timer
Timer PPG Mode
The operation in Timer-PPG mode is as follows (see the List of Output Details).
Each channel of WFG has two flags: WFG timer ac tive flag0 and WFG timer active flag1. This mode
outputs a waveform using these flags.
The CH_GATE signal outputs WFG timer active flag1, WFG timer active flag0, or the logic OR signal of
each signal by GTEN[1:0] setting.
The RTO(1) and RTO(0) signals output these active fl ags, CH_PPG signal, or the logic AND...")
![Page 640
4. Registers of Multifunction Timer
PPG Dead Timer Mode
The operation in PPG dead timer mode is as follows (see the List of Output Details).
The CH_GATE signal outputs the RT(1) signal, RT(0) signal or logic OR signal by GTEN[1:0] setting.
As for the RTO(1) and RTO(0) sign als, the non-overlap signal that has the dead time set by WFG timer
based on the CH_PPG signal is output.
In this mode, the RT(0) and RT(1) signals are used only for the output of the CH_GATE signal.
Figure 4-27 shows...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-639.png "Page 640
4. Registers of Multifunction Timer
PPG Dead Timer Mode
The operation in PPG dead timer mode is as follows (see the List of Output Details).
The CH_GATE signal outputs the RT(1) signal, RT(0) signal or logic OR signal by GTEN[1:0] setting.
As for the RTO(1) and RTO(0) sign als, the non-overlap signal that has the dead time set by WFG timer
based on the CH_PPG signal is output.
In this mode, the RT(0) and RT(1) signals are used only for the output of the CH_GATE signal.
Figure 4-27 shows...")
![Page 644
5. Other Matters
Ta b l e 5 - 1 shows the register settings of OCFS and ICFS of MFT-unit0 and wher e they are connected.
Table 5-1 OCFS and ICFS Register Settings for MFT-unit0
(For Model Containing 2 Multifunction Timer Units)
Register Name Setting Function
0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(0). FSO0[3:0]
0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(0).
0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(1).
OCFS
FSO1[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(1).
0011...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-643.png "Page 644
5. Other Matters
Ta b l e 5 - 1 shows the register settings of OCFS and ICFS of MFT-unit0 and wher e they are connected.
Table 5-1 OCFS and ICFS Register Settings for MFT-unit0
(For Model Containing 2 Multifunction Timer Units)
Register Name Setting Function
0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(0). FSO0[3:0]
0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(0).
0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(1).
OCFS
FSO1[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(1).
0011...")
![Page 645
5. Other Matters
5.1.2. PPG Timer Unit Connected to WFG
The PPG timer unit to be connected to WFG varies depending on the multifunction timer unit
used. This section explains the connection of the PPG timer unit and the selection method.
MFT-unit1
PPG timer unit ch.8, ch.10 and ch.12 are connected to WFG of MFTunit1, as shown in Figure 5-2.
Figure 5-2 Diagram of WFG-PPG Connection at MFTunit1
SEL
SEL
SEL
PPG8
CH10_PPG
CH54_PPG CH54_GATECH32_GATE CH10_GATEGATE8
CH32_PPG
WFSA10.PSEL[1:0]...](http://img.usermanuals.tech/thumb/26/104930/w64_series-3-manual-1526392501_d-644.png "Page 645
5. Other Matters
5.1.2. PPG Timer Unit Connected to WFG
The PPG timer unit to be connected to WFG varies depending on the multifunction timer unit
used. This section explains the connection of the PPG timer unit and the selection method.
MFT-unit1
PPG timer unit ch.8, ch.10 and ch.12 are connected to WFG of MFTunit1, as shown in Figure 5-2.
Figure 5-2 Diagram of WFG-PPG Connection at MFTunit1
SEL
SEL
SEL
PPG8
CH10_PPG
CH54_PPG CH54_GATECH32_GATE CH10_GATEGATE8
CH32_PPG
WFSA10.PSEL[1:0]...")
5. Other Matters 5. Other Matters 5.1 Connection of Model Containing Multiple MFT’s 5.2 Treatment of Event Detect Register and Interrupt FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 605 MB9Axxx/MB9Bxxx Series
5. Other Matters 5.1. Connection of Model Containing Multiple MFT’s This section describes the connection of models that contain multiple MFT’s. For models containing more than one multifunction timer unit, the connection of the I/O signals of the multifunction timer varies depending on the unit. This section describes such connection differences for each multifunction timer unit. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 606 MB9Axxx/MB9Bxxx Series
5. Other Matters
5.1.1. Selection of FRT Connected to OCU and ICU
OCU and ICU are configured to be able to select FRT for other multifunction timer units. This
section explains FRT connection between multifunction timer units and the selection method.
Model Containing Two MFT’s
Figure 5-1 shows a diagram of FRT connected between mu ltifunction timer u nits for a model containing 2
multifunction timer units.
Figure 5-1 Diagram of FRT Connected between Multifunction Timer Units (For Model Containing 2 Multifunction Timer Units)
MFT-unit0 FRT-ch.0MFT-unit0 FRT-ch.1 MFT-unit1 FRT-ch.0 MFT-unit1 FRT-ch.1
ADCMP 3ch
FRTch.2
FRTch.1
FRTch.0
OCU 6ch
ICU 4ch
MFT unit0
FRTS
FRTS
FRTS FRTS
ADCMP 3ch
FRTch.2
FRTch.1
FRTch.0
OCU 6ch
ICU 4ch
MFT unit1
FRTS
FRTS
FRTS FRTS
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER 15: Multifunction Timer
MN706-00002-1v0-E
607
MB9Axxx/MB9Bxxx Series
5. Other Matters Ta b l e 5 - 1 shows the register settings of OCFS and ICFS of MFT-unit0 and wher e they are connected. Table 5-1 OCFS and ICFS Register Settings for MFT-unit0 (For Model Containing 2 Multifunction Timer Units) Register Name Setting Function 0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(0). FSO0[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(0). 0011 Connects FRT-ch.0 of MFT unti1 to OCU ch.(1). OCFS FSO1[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to OCU ch.(1). 0011 Connects FRT-ch.0 of MFT unti1 to ICU ch.(0). FSI0[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to ICU ch.(0). 0011 Connects FRT-ch.0 of MFT unti1 to ICU ch.(1). ICFS FSI1[3:0] 0100 Connects FRT-ch.1 of MFT unti1 to ICU ch.(1). Ta b l e 5 - 2 shows the register settings of OCFS and ICFS of MFT-unit1 and whe r e they are connected. Table 5-2 OCFS and ICFS Register Settings for MFT-unit1 (For Model Containing 2 Multifunction Timer Units) Register Name Setting Function 0011 Connects FRT-ch.0 of MFT unti0 to OCU ch.(0). FSO0[3:0] 0100 Connects FRT-ch.1 of MFT unti0 to OCU ch.(0). 0011 Connects FRT-ch.0 of MFT unti0 to OCU ch.(1). OCFS FSO1[3:0] 0100 Connects FRT-ch.1 of MFT unti0 to OCU ch.(1). 0011 Connects FRT-ch.0 of MFT unti0 to ICU ch.(0). FSI0[3:0] 0100 Connects FRT-ch.1 of MFT unti0 to ICU ch.(0). 0011 Connects FRT-ch.0 of MFT unti0 to ICU ch.(1). ICFS FSI1[3:0] 0100 Connects FRT-ch.1 of MFT unti0 to ICU ch.(1). FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 608 MB9Axxx/MB9Bxxx Series
5. Other Matters 5.1.2. PPG Timer Unit Connected to WFG The PPG timer unit to be connected to WFG varies depending on the multifunction timer unit used. This section explains the connection of the PPG timer unit and the selection method. MFT-unit1 PPG timer unit ch.8, ch.10 and ch.12 are connected to WFG of MFTunit1, as shown in Figure 5-2. Figure 5-2 Diagram of WFG-PPG Connection at MFTunit1 SEL SEL SEL PPG8 CH10_PPG CH54_PPG CH54_GATECH32_GATE CH10_GATEGATE8 CH32_PPG WFSA10.PSEL[1:0] WFSA32.PSEL[1:0] WFSA54.PSEL[1:0] WFG ch.10 WFG ch.32 WFG ch.54 WFSA10.PSEL[1:0] WFSA32.PSEL[1:0] WFSA54.PSEL[1:0] PPG10 PPG12 GATE10 GATE12 SEL SEL SEL In case of WFG in MFTunit1, the following is selected by the setting of the WFSA.PSEL[1:0] register. [bit9:8] WFSA.PSEL[1:0] Process Value Function 00 Sets the output destination of the GATE signal to PPG timer unit ch.8. Sets the input source of the PPG signal to PPG timer unit ch.8. 01 Sets the output destination of the GATE signal to PPG timer unit ch.10. Sets the input source of the PPG signal to PPG timer unit ch.10. 10 Sets the output destination of the GATE signal to PPG timer unit ch.12. Sets the input source of the PPG signal to PPG timer unit ch.12. Write 11 Setting prohibited Read - Reads the register setting. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 609 MB9Axxx/MB9Bxxx Series
5. Other Matters 5.2. Treatment of Event Detect Register and Interrupt This section provides notes on the event detect register in the multifunction timer unit, the operation and control of interrupt-related circuits. Configuration of Circuit Figure 5-3 shows the configuration of th e interru pt signal generator. Figure 5-3 Configuration of Interrupt Signal Generator Interrupt enable register Event detectregister Interrupt signal （To:Interrupt controller ） Read value （To:CPU） Read vaule （To:CPU） Event : set 1 CPU 0 write : clear 0 CPU 0/1 write Event detect register Each function block has an event detect register to no tify CPU that a specific event (e.g. detection of the rising edge of the input signal at ICU) has occurred . This register indicates 0 when the relevant event has not occurred. It is set to 1, when the event occurs. Interrupt enable register There is an interrupt enable register to specify whether or not to notify CPU of the above event as an interrupt. As shown in the figure, the logic AND of the values in the event detect register and the interrupt enable register is connected to the in terrupt controller (NVIC) as an interrupt signal. Writing to and reading from each register The event detect register can be read from CPU at any time, regardless of the value in the interrupt enable register. It can be cleared by writing 0, but cannot be set by writing 1. The interrupt enable register allows any value to be set from CPU and can be read. Circuit Operation Operation when the interrupt enable register is set to 0 (interrupt disabled) Even when an event occurs and 1 is set to the event detect register, no interrupt occurs. In this case, the occurrence of the event can be reco gnized by reading from the event de tect register regularly via CPU. Operation when the interrupt enable regist er is set to 1 (interrupt enabled) When an event occurs and 1 is set to the event det ect register, the interrupt signal is asserted and an interrupt occurs. CPU can recognize the oc currence of the event by the interrupt. Clearing Event Detect Register Generally, the event detect register ca nnot be cleared automatically. In order to recognize the occurrence of the next event after 1 is set to the event detect register, the event detect register must be cleared via CPU beforehand. If it is not cleared via CPU, CPU cannot recognize the occurrence of the succeeding events. FUJITSU SEMICO NDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 610 MB9Axxx/MB9Bxxx Series
5. Other Matters Returning from Interrupt Processing When an interrupt is processed using an interrupt sign al, it is necessary to clear the event detect register when returning from the interrupt processing, deasse rt the interrupt signal, and then return from the interrupt. Returning from an interrupt without deasse rting the interrupt signal will result in the same interrupt process taking place again w ith no way out of that process. Value Written to Event Detect Register The write value and read value of the event detect register have the following meanings: Writing 0 : Clears the register. Writing 1 : Does nothing. Reading 0 : No event occurred. Reading 1 : Event occurred. Because the event detect register is in the configura tion described above, when a value is read from the event detect register via CPU, the value can not be normally written back. This is due to the following reason. When 0 is successfully read from th e event detect register at a certain point, it indicates that the event has yet to occur at that point. Next, writing the value back to the event detect register without change (i.e. writing 0) means instructing the event detect register to be cleared. If an event occurs during the period from the reading via CPU to the writing the value back , the register will be cleared, preventing that event from being recognized. For the above reason, when writing to the event detect register, 1 must be always written (i.e. doing nothing), unless the register is intended to be cleared. An example is provided below. The ICSA10 register is in the following configuration based on the 8-bit register. Bit 7 6 5 4 3 2 1 0 Field ICP1 ICP0 ICE1 ICE0 EG1[1:0] EG0[1:0] The ICP1 and ICP0 registers are event detect registers that notify CPU of an event upon edge detection at ICU-ch1 and ICU-ch.0, respectively. If 01111111 is read from these registers at a certain point, for example, it indicates that a valid edge is detected (ICP0=1) at ch.0 and no valid edge is detected (ICP1=0) at ch.1. Then, write 0 back to bit6 in order to clear the ICP0 register. At that point, it is not possible to set the value in the ICP0 register to 0 and write 00111111 back due to the reason explained above. It is because information about any possible detection of an event at ch.1 will be cleared during the period from reading from the register to writing the value back. Therefore, in order to clear the ICP0 register, it is necessary to write 10111111 back with bit6=0 and bit7=1. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 611 MB9Axxx/MB9Bxxx Series
5. Other Matters Read Value Mask Function at RMW Access Since the above procedure is complicated, a masking function is provided to mask the read value of the event detect register to 1 at RMW access for the value to be written back. In this model, RMW access occurs, when write access is made to the bit-banding alias area. Write access to the bit-banding alias area is the RMW acces s used to read all of ther register bits in the address area where the target bit exists, rewrite only the target bit and write all the register bits back. In the example of the ICSA10 register provided earlier, assume that the value 01111111 is read at a certain point. To write 0 to bit6 so that th e ICP0 register will be cleared, write access to the normal address area requires bit7=1 and bit6=0 to be written. However, if 0 is written to bit6 by write access to the bit-banding alias area, the hardware performs the following operation: It read the value in the ICSA10 register. At this point, the ICP1 and ICP0 registers return a read value masked to 1 becau se of the RMW access. In other words, the value to be read is 11111111. Write to the ICSA10 register the value 10111111, where only the value of bit6(ICP0) has been replaced with 0. bit7 can not be cleared because the device operates as described above. How to write back the value of bit6 is described in this example. In case of writing back the values of bit7 and bit5 to bit0, the read values of bit7 and bit6 are masked to 1 also ; therefore, it is unnecessary to consid er the writing back value. For this reason, this configuration allows rewriting the regist er without considering the writing back value to the event detection register in case of writin g access to the bit-banding alias area. * Read access to the bit-banding alias area is not RMW access; therefore the value of the register is unmasked when reading. List of Event Detect Registers and Interrupt Enable Registers Ta b l e 5 - 3 shows a list of the event detect registers and interrupt enable reg isters that exist in the multifunction timer unit as well as their interrupt signals. FUJITSU SEMICONDUCTOR LIMITED CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 612 MB9Axxx/MB9Bxxx Series
5. Other Matters FUJITSU SEMICONDUCTOR LIMITED CHAPTER: Multifunction Timer FUJITSU SEMICONDUCTOR CONFIDENTIAL 120 Table 5-3 List of Event Detect Registers and Interrupt Enable Registers Block Name Target Event Event Detect Register Interrupt Enable Register Name of Interrupt Signal FRT ch.0 Detection of FRT0 == 0x0000 TCSA0.IRQZFTCSA0.IRQZE Zero value detection interrupt FRT ch.1 Detection of FRT1 == 0x0000 TCSA1.IRQZFTCSA1.IRQZE Zero value detection interrupt FRT ch.2 Detection of FRT2 == 0x0000 TCSA2.IRQZFTCSA2.IRQZE Zero value detection interrupt FRT ch.0 Detection of FRT0 == TCCP0 TCSA0.ICLR TCSA0.ICRE Peak value detection interrupt FRT ch.1 Detection of FRT1 == TCCP1 TCSA1.ICLR TCSA1.ICRE Peak value detection interrupt FRT ch.2 Detection of FRT2 == TCCP2 TCSA2.ICLR TCSA2.ICRE Peak value detection interrupt OCU ch.0 Detection of FRT == OCCP0 OCSA10.IOP0OCSA10.IOE0 Match detection interrupt OCU ch.1 Detection of FRT == OCCP1 OCSA10.IOP1OCSA10.IOE1 Match detection interrupt OCU ch.2 Detection of FRT == OCCP2 OCSA32.IOP0OCSA32.IOE0 Match detection interrupt OCU ch.3 Detection of FRT == OCCP3 OCSA32.IOP1OCSA32.IOE1 Match detection interrupt OCU ch.4 Detection of FRT == OCCP4 OCSA54.IOP0OCSA54.IOE0 Match detection interrupt OCU ch.5 Detection of FRT == OCCP5 OCSA54.IOP1OCSA54.IOE1 Match detection interrupt ICU ch.0 Detection of valid edge ICSA10.ICP0 ICSA10.ICE0 Input signal edge detection interrupt ICU ch.1 Detection of valid edge ICSA10.ICP1 ICSA10.ICE1 Input signal edge detection interrupt ICU ch.2 Detection of valid edge ICSA32.ICP0 ICSA32.ICE0 Input signal edge detection interrupt ICU ch.3 Detection of valid edge ICSA32.ICP1 ICSA32.ICE1 Input signal edge detection interrupt The interrupts shown in Ta b l e 5 - 4 below do not have an interrupt enable register, as they are dedicated to interrupts (i.e. p o lling not assumed). If 1 is set to the interrupt flag when the target event occurs, an interrupt occurs. Table 5-4 List of Interrupt Flag Registers and Interrupt Enable Registers Block Name Target Event Interrupt Flag Register Interrupt Enable Register Name of Interrupt Signal NZCL Input of emergency motor shutdown signal WFIR.DTIF None DTIF interrupt WFG ch.10 Completion of WFG10 timer count WFIR.TMIF10None WFG10 timer interrupt WFG ch.32 Completion of WFG32 timer count WFIR.TMIF32None WFG32 timer interrupt WFG ch.54 Completion of WFG54 timer count WFIR.TMIF54None WFG54 timer interrupt CHAPTER 15: Multifunction Timer MN706-00002-1v0-E 613 MB9Axxx/MB9Bxxx Series
FUJITSU SEMICONDUCTOR LIMITED MN706-00002-1v0-E 614 MB9Axxx/MB9Bxxx Series